## ## This file is part of the coreboot project. ## ## Copyright (C) 2015 Timothy Pearson , Raptor Engineering ## Copyright (C) 2007 AMD ## Written by Yinghai Lu for AMD. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 r 0 unused #394 7 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level 416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved enumerations #ID value text 1 0 Disable 1 1 Enable 2 0 Enable 2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency 6 1 Alert 6 2 Critical 6 3 Error 6 4 Warning 6 5 Notice 6 6 Information 6 7 Debug 6 8 Spew 8 0 DDR2-800 8 1 DDR2-667 8 2 DDR2-533 8 3 DDR2-400 9 0 off 9 1 87.5% 9 2 75.0% 9 3 62.5% 9 4 50.0% 9 5 37.5% 9 6 25.0% 9 7 12.5% 10 0 Disabled 10 1 40ns 10 2 80ns 10 3 160ns 10 4 320ns 10 5 640ns 10 6 1.28us 10 7 2.56us 10 8 5.12us 10 9 10.2us 10 10 20.5us 10 11 41us 10 12 81.9us 10 13 163.8us 10 14 327.7us 10 15 655.4us 10 16 1.31ms 10 17 2.62ms 10 18 5.24ms 10 19 10.49ms 10 20 20.97sms 10 21 42ms 10 22 84ms checksums checksum 392 983 984