fw_config
	field RETIMER 0 1
		option RETIMER_UNKNOWN			0
		option RETIMER_BYPASS			1
		option RETIMER_JHL8040			2
	end
	field STORAGE 2 3
		option STORAGE_UNKNOWN			0
		option STORAGE_UFS			1
		option STORAGE_NVME			2
	end
	field WIFI_BT 4 4
		option WIFI_BT_CNVI			0
		option WIFI_BT_PCIE			1
	end
	field AUDIO 5 7
		option AUDIO_UNKNOWN			0
		option AUDIO_REALTEK_ALC256		1
	end
	field UFC 8 9
		option UFC_NONE				0
		option UFC_OV2740			1
	end
end

chip soc/intel/alderlake
	device domain 0 on
		device ref dtt on
			chip drivers/intel/dptf
				## sensor information
				register "options.tsr[0].desc" = ""DRAM_SOC""
				register "options.tsr[1].desc" = ""Fan-Inlet""

				# TODO: below values are initial reference values only
				## Active Policy
				register "policies.active" = "{
						[0] = {
								.target = DPTF_TEMP_SENSOR_1,
								.thresholds = {
												TEMP_PCT(85, 90),
												TEMP_PCT(80, 80),
												TEMP_PCT(75, 70),
												TEMP_PCT(70, 60),
												TEMP_PCT(65, 50),
												TEMP_PCT(60, 40),
								}
						}
				}"

				## Passive Policy
				register "policies.passive" = "{
						[0] = DPTF_PASSIVE(CPU,		CPU,		   97, 5000),
						[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 85, 5000),
						[2] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_1, 85, 5000),
				}"

				## Critical Policy
				register "policies.critical" = "{
						[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
						[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      95, SHUTDOWN),
						[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      95, SHUTDOWN),
				}"

				register "controls.power_limits" = "{
						.pl1 = {
									.min_power = 15000,
									.max_power = 15000,
									.time_window_min = 28 * MSECS_PER_SEC,
									.time_window_max = 32 * MSECS_PER_SEC,
									.granularity = 200,
								},
						.pl2 = {
									.min_power = 55000,
									.max_power = 55000,
									.time_window_min = 28 * MSECS_PER_SEC,
									.time_window_max = 32 * MSECS_PER_SEC,
									.granularity = 1000,
								}
				}"

				## Charger Performance Control (Control, mA)
				register "controls.charger_perf" = "{
						[0] = { 255, 1700 },
						[1] = {  24, 1500 },
						[2] = {  16, 1000 },
						[3] = {   8,  500 }
				}"

				## Fan Performance Control (Percent, Speed, Noise, Power)
				register "controls.fan_perf" = "{
						[0] = {  90, 6700, 220, 2200, },
						[1] = {  80, 5800, 180, 1800, },
						[2] = {  70, 5000, 145, 1450, },
						[3] = {  60, 4900, 115, 1150, },
						[4] = {  50, 3838,  90,  900, },
						[5] = {  40, 2904,  55,  550, },
						[6] = {  30, 2337,  30,  300, },
						[7] = {  20, 1608,  15,  150, },
						[8] = {  10,  800,  10,  100, },
						[9] = {   0,    0,   0,   50, }
				}"

				## Fan options
				register "options.fan.fine_grained_control" = "1"
				register "options.fan.step_size" = "2"

				device generic 0 on end
			end
		end # DTT
		device ref igpu on
			chip drivers/gfx/generic
				register "device_count" = "6"
				# DDIA for eDP
				register "device[0].name" = ""LCD0""
				register "device[0].type" = "panel"
				# DDIB for HDMI
				# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
				register "device[1].name" = ""DD01""
				# TCP0 (DP-1) for port C0
				register "device[2].name" = ""DD02""
				register "device[2].use_pld" = "true"
				register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
				# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
				register "device[3].name" = ""DD03""
				# TCP2 (DP-3) for port C2
				register "device[4].name" = ""DD04""
				register "device[4].use_pld" = "true"
				register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
				# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
				register "device[5].name" = ""DD05""
				device generic 0 on end
			end
		end # Integrated Graphics Device
		device ref pch_espi on
			chip ec/google/chromeec
				use conn0 as mux_conn[0]
				use conn1 as mux_conn[1]
				device pnp 0c09.0 on end
			end
		end
		device ref pmc hidden
			chip drivers/intel/pmc_mux
				device generic 0 on
					chip drivers/intel/pmc_mux/conn
						use usb2_port1 as usb2_port
						use tcss_usb3_port1 as usb3_port
						device generic 0 alias conn0 on end
					end
					chip drivers/intel/pmc_mux/conn
						use usb2_port3 as usb2_port
						use tcss_usb3_port3 as usb3_port
						device generic 1 alias conn1 on end
					end
				end
			end
		end
		device ref tcss_xhci on
			chip drivers/usb/acpi
				device ref tcss_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref tcss_usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref tcss_usb3_port3 on end
					end
				end
			end
		end
		device ref xhci on
			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C0 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
						device ref usb2_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-C Port C2 (MLB)""
						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 SD Bridge""
						register "type" = "UPC_TYPE_INTERNAL"
						device ref usb2_port5 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Camera""
						register "type" = "UPC_TYPE_INTERNAL"
						register "has_power_resource" = "1"
						register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
						device ref usb2_port7 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Type-A Port A0 (DCI)""
						register "type" = "UPC_TYPE_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb2_port9 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB2 Bluetooth""
						register "type" = "UPC_TYPE_INTERNAL"
						register "has_power_resource" = "1"
						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
						device ref usb2_port10 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A0 (DCI)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc" = ""USB3 Type-A Port A1 (DB)""
						register "type" = "UPC_TYPE_USB3_A"
						register "use_custom_pld" = "true"
						register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
						device ref usb3_port3 on end
					end
				end
			end
		end
		device ref tcss_dma0 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port1 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref tcss_dma1 on
			chip drivers/intel/usb4/retimer
				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
				use tcss_usb3_port3 as dfp[0].typec_port
				device generic 0 on end
			end
		end
		device ref pcie4_0 on
			# Enable CPU PCIE RP 1 using CLK 3
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_req = 3,
				.clk_src = 3,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			probe STORAGE STORAGE_NVME
		end
		device ref pcie_rp5 on
			register "pch_pcie_rp[PCH_RP(5)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
			chip soc/intel/common/block/pcie/rtd3
				# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
				register "srcclk_pin" = "1"
				device generic 0 on end
			end
			probe WIFI_BT WIFI_BT_PCIE
		end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				register "add_acpi_dma_property" = "true"
				register "enable_cnvi_ddr_rfim" = "true"
				device generic 0 on end
			end
			probe WIFI_BT WIFI_BT_CNVI
		end
		device ref ish on
			chip drivers/intel/ish
				register "add_acpi_dma_property" = "true"
				device generic 0 on end
			end
			probe STORAGE STORAGE_UFS
		end
		device ref ufs on
			probe STORAGE STORAGE_UFS
		end
	end
end