# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/cezanne

	register "common_config.acp_config" = "{
		.acp_pin_cfg = I2S_PINS_I2S_TDM,
		.acp_i2s_wake_enable = 0,
		.acp_pme_enable = 0,
		.dmic_present = 1,
	}"

	# eSPI Configuration
	register "common_config.espi_config" = "{
		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
		.generic_io_range[0] = {
			.base = 0x62,
			/*
			 * Only 0x62 and 0x66 are required. But, this is not supported by
			 * standard IO decodes and there are only 4 generic I/O windows
			 * available. Hence, open a window from 0x62-0x67.
			 */
			.size = 5,
		},
		.generic_io_range[1] = {
			.base = 0x800,   /* EC_HOST_CMD_REGION0 */
			.size = 256,     /* EC_HOST_CMD_REGION_SIZE * 2 */
		},
		.generic_io_range[2] = {
			.base = 0x900,   /* EC_LPC_ADDR_MEMMAP */
			.size = 255,     /* EC_MEMMAP_SIZE */
		},
		.generic_io_range[3] = {
			.base = 0x200,   /* EC_LPC_ADDR_HOST_DATA */
			.size = 8,       /* 0x200 - 0x207 */
		},

		.io_mode = ESPI_IO_MODE_QUAD,
		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
		.crc_check_enable = 1,
		.alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN,
		.periph_ch_en = 1,
		.vw_ch_en = 1,
		.oob_ch_en = 0,
		.flash_ch_en = 0,

		/*
		 * b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH,
		 * but eSPI gets configured in verstage which is in RO.
		 * We have already locked RO for guybrush devices so we need
		 * make it so x86 coreboot re-initializes the vw_irq_polarity.
		 * This leaves another problem, verstage also runs in S0i3, but
		 * we don't run any other x86 coreboot stages, so we need to
		 * figure out a way to reset the eSPI polarity.
		 */
		.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1),
	}"

	# Enable S0i3 support
	register "s0ix_enable" = "1"

	# Enable STT support
	register "stt_control" = "1"
	register "stt_pcb_sensor_count" = "2"
	register "stt_min_limit" = "0"
	register "stt_m1" = "0x03A0"
	register "stt_m2" = "0xFFC9"
	register "stt_m3" = "0"
	register "stt_m4" = "0"
	register "stt_m5" = "0"
	register "stt_m6" = "0"
	register "stt_c_apu" = "0x0901"
	register "stt_c_gpu" = "0"
	register "stt_c_hs2" = "0"
	register "stt_alpha_apu" = "0x199A"
	register "stt_alpha_gpu" = "0"
	register "stt_alpha_hs2" = "0"
	register "stt_skin_temp_apu" = "0x2D00"
	register "stt_skin_temp_gpu" = "0"
	register "stt_skin_temp_hs2" = "0"
	register "stt_error_coeff" = "0x21"
	register "stt_error_rate_coefficient" = "0xCCD"

	register "system_configuration" = "2"

	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
	# I2C Pad Control RX Select Configuration
	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad
	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # Touchscreen
	register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # Audio/SAR
	register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC

	# general purpose PCIe clock output configuration
	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
	register "gpp_clk_config[2]" = "GPP_CLK_REQ"
	register "gpp_clk_config[3]" = "GPP_CLK_REQ"
	register "gpp_clk_config[4]" = "GPP_CLK_OFF"
	register "gpp_clk_config[5]" = "GPP_CLK_OFF"
	register "gpp_clk_config[6]" = "GPP_CLK_OFF"

	register "pspp_policy" = "DXIO_PSPP_BALANCED"

	register "usb_phy_custom" = "1"
	register "usb_phy" = "{
		/* Left USB C0 Port */
		.Usb2PhyPort[0] = {
			.compdstune = 3,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 1,
			.txpreemppulsetune = 0,
			.txrisetune = 1,
			.txvreftune = 6,
			.txhsxvtune = 3,
			.txrestune = 1,
		},
		/* Left USB A0 Port or WWAN */
		.Usb2PhyPort[1] = {
			.compdstune = 3,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 1,
			.txpreemppulsetune = 0,
			.txrisetune = 1,
			.txvreftune = 6,
			.txhsxvtune = 3,
			.txrestune = 1,
		},
		/* User facing camera */
		.Usb2PhyPort[2] = {
			.compdstune = 1,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 2,
			.txpreemppulsetune = 0,
			.txrisetune = 2,
			.txvreftune = 3,
			.txhsxvtune = 3,
			.txrestune = 2,
		},
		/* World facing camera */
		.Usb2PhyPort[3] = {
			.compdstune = 1,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 2,
			.txpreemppulsetune = 0,
			.txrisetune = 2,
			.txvreftune = 3,
			.txhsxvtune = 3,
			.txrestune = 2,
		},
		/* Right USB C1 Port */
		.Usb2PhyPort[4] = {
			.compdstune = 3,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 1,
			.txpreemppulsetune = 0,
			.txrisetune = 1,
			.txvreftune = 6,
			.txhsxvtune = 3,
			.txrestune = 1,
		},
		/* Right USB A1 Port */
		.Usb2PhyPort[5] = {
			.compdstune = 5,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 1,
			.txpreemppulsetune = 0,
			.txrisetune = 1,
			.txvreftune = 9,
			.txhsxvtune = 3,
			.txrestune = 1,
		},
		/* WiFi / Bluetooth */
		.Usb2PhyPort[6] = {
			.compdstune = 1,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 2,
			.txpreemppulsetune = 0,
			.txrisetune = 2,
			.txvreftune = 3,
			.txhsxvtune = 3,
			.txrestune = 2,
		},
		/* Smart Card */
		.Usb2PhyPort[7] = {
			.compdstune = 1,
			.sqrxtune = 3,
			.txfslstune = 3,
			.txpreempamptune = 2,
			.txpreemppulsetune = 0,
			.txrisetune = 2,
			.txvreftune = 3,
			.txhsxvtune = 3,
			.txrestune = 2,
		},
		/* Left USB C0 Port */
		.Usb3PhyPort[0] = {
			.tx_term_ctrl=2,
			.rx_term_ctrl=2,
			.tx_vboost_lvl_en=1,
			.tx_vboost_lvl=5,
		},
		/* Left USB A0 Port or WWAN */
		.Usb3PhyPort[1] = {
			.tx_term_ctrl=2,
			.rx_term_ctrl=2,
			.tx_vboost_lvl_en=1,
			.tx_vboost_lvl=5,
		},
		/* Right USB C1 Port */
		.Usb3PhyPort[2] = {
			.tx_term_ctrl=2,
			.rx_term_ctrl=2,
			.tx_vboost_lvl_en=1,
			.tx_vboost_lvl=5,
		},
		/* Right USB A1 Port */
		.Usb3PhyPort[3] = {
			.tx_term_ctrl=2,
			.rx_term_ctrl=2,
			.tx_vboost_lvl_en=1,
			.tx_vboost_lvl=5,
		},
		.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
		.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
		.BatteryChargerEnable = 0,
		.PhyP3CpmP4Support = 0,
	}"

	device domain 0 on
		device ref iommu on end

		device ref gpp_bridge_0 on
			chip drivers/pcie/generic
				register "wake_gpe" = "GEVENT_8"
				register "wake_deepest" = "ACPI_S0"
				register "name" = ""WLAN""
				device pci 00.0 on end
			end
		end # WLAN
		device ref gpp_bridge_1 on end # SD
		device ref gpp_bridge_2 on end # WWAN
		device ref gpp_bridge_3 on
			# Required so the NVMe gets placed into D3 when entering S0i3.
			chip drivers/pcie/rtd3/device
				register "name" = ""NVME""
				device pci 00.0 on end
			end
		end # NVMe

		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
			device ref gfx on end # Internal GPU (GFX)
			device ref gfx_hda on end # GFX HD Audio Controller
			device ref crypto on end # Crypto Coprocessor
			device ref xhci_0 on # USB 3.1 (USB0)
				chip drivers/usb/acpi
					device ref xhci_0_root_hub on
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
							register "use_custom_pld" = "true"
							register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
							device ref usb3_port0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
							device ref usb3_port1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
							device ref usb2_port0 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Left Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(1, 2))"
							device ref usb2_port1 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""User-Facing Camera""
							register "type" = "UPC_TYPE_INTERNAL"
							device ref usb2_port2 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""World-Facing Camera""
							register "type" = "UPC_TYPE_INTERNAL"
							device ref usb2_port3 on end
						end
					end
				end
			end
			device ref xhci_1 on # USB 3.1 (USB1)
				chip drivers/usb/acpi
					device ref xhci_1_root_hub on
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))"
							device ref usb3_port4 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
							device ref usb3_port5 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-C Port""
							register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))"
							device ref usb2_port4 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Right Type-A Port""
							register "type" = "UPC_TYPE_USB3_A"
                                                        register "use_custom_pld" = "true"
                                                        register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
							device ref usb2_port5 on end
						end
						chip drivers/usb/acpi
							register "desc" = ""Bluetooth""
							register "type" = "UPC_TYPE_INTERNAL"
							register "has_power_resource" = "true"
							register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_132)"
							# TODO(rrangel): Find data sheet
							register "enable_delay_ms" = "500"
							register "enable_off_delay_ms" = "10"
							register "use_gpio_for_status" = "true"
							device ref usb2_port6 on end
						end
					end
				end
			end
			device ref acp on
				chip drivers/amd/i2s_machine_dev
					register "hid" = ""AMDI1019""
					device generic 0.0 on end
				end
			end # Audio
		end

		device ref lpc_bridge on
			chip ec/google/chromeec
				device pnp 0c09.0 alias chrome_ec on end
			end
		end
	end # domain

	device ref i2c_3 on
		chip drivers/i2c/tpm
			register "hid" = ""GOOG0005""
			register "desc" = ""Cr50 TPM""
			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_85)"
			register "power_managed_mode" = "CONFIG(PSP_S0I3_RESUME_VERSTAGE) ?
							 TPM_KERNEL_POWER_MANAGED : TPM_DEFAULT_POWER_MANAGED"
			device i2c 50 alias cr50 on end
		end
	end

	device ref uart_0 on end # UART0

	# See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/guybrush/baseboard.c;l=221
	# for the EC configuration.
	#
	# EC is configured to power off the system at 105C, so add a two degree
	# buffer so the OS can gracefully shutdown.
	#
	# EC is configured to assert PROCHOT at 100C. That drastically lowers
	# performance. Instead we will tell the OS to start throttling the CPUs
	# at 95C in hopes that we don't hit the PROCHOT limit.
	#
	# We set use_acpi1_thermal_zone_scope because the Chrome ec.asl
	# performs a `Notify` to the `_\TZ` scope.
	chip drivers/acpi/thermal_zone
		register "description" = ""SOC""
		use chrome_ec as temperature_controller
		register "sensor_id" = "0"
		register "polling_period" = "10"
		register "critical_temperature" = "103"
		register "passive_config.temperature" = "95"
		register "use_acpi1_thermal_zone_scope" = "true"

		device generic 0 on end
	end
	chip drivers/acpi/thermal_zone
		register "description" = ""Charger""
		use chrome_ec as temperature_controller
		register "sensor_id" = "1"
		register "polling_period" = "10"
		register "critical_temperature" = "103"
		register "passive_config.temperature" = "95"
		register "use_acpi1_thermal_zone_scope" = "true"

		device generic 1 on end
	end
	chip drivers/acpi/thermal_zone
		register "description" = ""Memory""
		use chrome_ec as temperature_controller
		register "sensor_id" = "2"
		register "polling_period" = "10"
		register "critical_temperature" = "103"
		register "passive_config.temperature" = "95"
		register "use_acpi1_thermal_zone_scope" = "true"

		device generic 2 on end
	end
	chip drivers/acpi/thermal_zone
		register "description" = ""CPU""
		use chrome_ec as temperature_controller
		register "sensor_id" = "3"
		register "polling_period" = "10"
		register "critical_temperature" = "103"
		register "passive_config.temperature" = "95"
		register "use_acpi1_thermal_zone_scope" = "true"

		device generic 3 on end
	end
end	# chip soc/amd/cezanne