##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/i945
	device domain 0 on
		device pci 00.0 on # Host bridge
			subsystemid 0x17aa 0x2015
		end
		device pci 01.0 on # PCI-e
			device pci 00.0 on # VGA
				subsystemid 0x17aa 0x20a4
			end
		end
		chip southbridge/intel/i82801gx
			device pci 1c.0 on # Ethernet
				subsystemid 0x17aa 0x2001
			end
			device pci 1c.1 on end # WLAN
			device pci 1c.2 on end # PCIe port 3
			device pci 1c.3 on end # PCIe port 4
			device pci 1e.0 on # PCI Bridge
				chip southbridge/ti/pci1x2x
					device pci 00.0 on
						subsystemid 0x17aa 0x2012
					end
				end
			end
			device pci 1f.0 on # PCI-LPC bridge
				chip ec/lenovo/h8
					register "has_bdc_detection" = "1"
					register "bdc_gpio_num" = "7"
					register "bdc_gpio_lvl" = "0"
				end
				chip superio/nsc/pc87384
					device pnp 2e.2 off # Serial Port / IR
						irq 0x70 = 4
					end
				end
			end
			device pci 1f.1 on # IDE
				subsystemid 0x17aa 0x200c
			end
			device pci 1f.3 on # SMBUS
				chip drivers/i2c/ck505
					register "mask" = "{ 0xff, 0xff, 0xff,
						 0xff, 0xff, 0xff, 0xff, 0xff,
						 0xff, 0xff, 0xff, 0xff }"
					register "regs" = "{ 0x2e, 0xf7, 0x3c,
						 0x20, 0x01, 0x00, 0x1b, 0x01,
						 0x54, 0xff, 0xff, 0x07 }"
				end
			end
		end
	end
end