# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-only

config NORTHBRIDGE_AMD_PI
	bool
	default y if CPU_AMD_PI
	default n
	select CBMEM_TOP_BACKUP

if NORTHBRIDGE_AMD_PI

config BOTTOMIO_POSITION
	hex "Bottom of 32-bit IO space"
	default 0xD0000000
	help
	  If PCI peripherals with big BARs are connected to the system
	  the bottom of the IO must be decreased to allocate such
	  devices.

	  Declare the beginning of the 128MB-aligned MMIO region.  This
	  option is useful when PCI peripherals requesting large address
	  ranges are present.

config CONSOLE_VGA_MULTI
	bool
	default n

config S3_VGA_ROM_RUN
	bool
	default n

source "src/northbridge/amd/pi/00630F01/Kconfig"
source "src/northbridge/amd/pi/00730F01/Kconfig"
source "src/northbridge/amd/pi/00660F01/Kconfig"

config HW_MEM_HOLE_SIZEK
	hex
	default 0x200000

config HEAP_SIZE
	hex
	default 0xc0000

config NUM_OF_IOAPICS
	int
	default 3

endif # NORTHBRIDGE_AMD_PI