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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/{
mainboard_vendor = "Artec";
mainboard_name = "DBE62";
cpus { };
apic@0 {
/config/("northbridge/amd/geodelx/apic");
};
domain@0 {
/config/("northbridge/amd/geodelx/domain");
pci@1,0 {
/config/("northbridge/amd/geodelx/pci");
/* Video RAM has to be in 2MB chunks. */
geode_video_mb = "16";
};
pci@1,1 {
/* This is the graphics device, but since the memory
* controller needs to know geode_video_mb, the
* phase2_init is done there. The rest are default ops.
*/
};
pci@1,2 { /* AES */
};
pci@f,0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x00001002";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EFFD";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
/* 0:IDE; 1:FLASH on CS0, 2:FLASH on CS1, 3:FLASH on CS2, 4:FLASH on CS3. */
enable_ide_nand_flash = "2";
/* we use com2 since that is on the dongle */
com2_enable = "1";
/* Set com2 address to be COM1 */
com2_address = "0x3f8";
/* Set com2 IRQ to be what is usually COM1 */
com2_irq = "4";
/* USB Port Power Handling setting. */
pph = "0xf5";
};
pci@f,1 { /* NAND Flash */
/config/("southbridge/amd/cs5536/nand");
/* Timings */
nandf_data = "0x01200120";
nandf_ctl = "0x00000120";
};
};
};
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