1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* A7 : SRCCLK_OE7# ==> NC */
PAD_NC(GPP_A7, NONE),
/* A17 : DISP_MISCC ==> NC */
PAD_NC(GPP_A17, NONE),
/* A19 : DDSP_HPD1 ==> NC */
PAD_NC(GPP_A19, NONE),
/* A20 : DDSP_HPD2 ==> NC */
PAD_NC(GPP_A20, NONE),
/* A21 : DDPC_CTRCLK ==> NC */
PAD_NC(GPP_A21, NONE),
/* A22 : DDPC_CTRLDATA ==> NC */
PAD_NC(GPP_A22, NONE),
/* B3 : PROC_GP2 ==> eMMC_PERST_L */
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B5 : ISH_I2C0_SDA ==> NC */
PAD_NC(GPP_B5, NONE),
/* B6 : ISH_I2C0_SCL ==> NC */
PAD_NC(GPP_B6, NONE),
/* B15 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_B15, NONE),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> NC */
PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> NC */
PAD_NC(GPP_D5, NONE),
/* D7 : SRCCLKREQ2# ==> NC */
PAD_NC(GPP_D7, NONE),
/* D13 : ISH_UART0_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
/* D14 : ISH_UART0_TXD ==> NC */
PAD_NC(GPP_D14, NONE),
/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC(GPP_D16, NONE),
/* D17 : UART1_RXD ==> NC */
PAD_NC(GPP_D17, NONE),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
PAD_CFG_GPO(GPP_E0, 1, PLTRST),
/* E3 : PROC_GP0 ==> NC */
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* E23 : DDPA_CTRLDATA ==> NC */
PAD_NC(GPP_E23, NONE),
/* F20 : EXT_PWR_GATE# ==> NC */
PAD_NC(GPP_F20, NONE),
/* H20 : IMGCLKOUT1 ==> NC */
PAD_NC(GPP_H20, NONE),
/* H21 : IMGCLKOUT2 ==> Privacy screen */
PAD_CFG_GPO(GPP_H21, 0, DEEP),
/* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE),
/* H23 : SRCCLKREQ5# ==> NC */
PAD_NC(GPP_H23, NONE),
/* R6 : I2S_PCH_TX_SPKR_RX ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : I2S_PCH_RX_SPKR_TX ==> NC */
PAD_NC(GPP_R7, NONE),
/* S4 : SNDW2_CLK ==> NC */
PAD_NC(GPP_S4, NONE),
/* S5 : SNDW2_DATA ==> NC */
PAD_NC(GPP_S5, NONE),
/* S6 : SNDW3_CLK ==> NC */
PAD_NC(GPP_S6, NONE),
/* S7 : SNDW3_DATA ==> NC */
PAD_NC(GPP_S7, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
/*
* D1 : ISH_GP1 ==> FP_RST_ODL
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
* FPMCU not working after a S3 resume. This is a known issue.
*/
PAD_CFG_GPO(GPP_D1, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
PAD_CFG_GPO(GPP_E0, 0, DEEP),
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
|
