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chip soc/intel/elkhartlake
device cpu_cluster 0 on
device lapic 0 on end
end
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_F"
register "pmc_gpe0_dw2" = "GPP_E"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Disabled"
register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{
.enable = 1,
.mode = IBECC_ALL
}"
# USB related UPDs
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # X125/X135
register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # X125/X135
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # X145/X155
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # X145/X155
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB Panel
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # USB Panel
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED
# Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true"
register "PcieRpLtrDisable[5]" = "true"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "0"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"
# LPSS Serial IO (I2C/UART/GSPI) related UPDs
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
register "SerialIoUartDmaEnable" = "{
[PchSerialIoIndexUART0] = 1,
[PchSerialIoIndexUART1] = 1,
[PchSerialIoIndexUART2] = 1,
}"
# TSN GBE related UPDs
register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
register "PchTsnGbeSgmiiEnable" = "1"
register "common_soc_config" = "{
.i2c[2] = {
.speed = I2C_SPEED_STANDARD,
},
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 08.0 off end # GNA
device pci 09.0 off end # CPU Intel Trace Hub
device pci 10.0 off end # I2C6
device pci 10.1 off end # I2C7
device pci 10.5 on end # Integrated Error Handler
device pci 11.0 off end # Intel PSE UART0
device pci 11.1 off end # Intel PSE UART1
device pci 11.2 off end # Intel PSE UART2
device pci 11.3 off end # Intel PSE UART3
device pci 11.4 off end # Intel PSE UART4
device pci 11.5 off end # Intel PSE UART5
device pci 11.6 off end # Intel PSE IS20
device pci 11.7 off end # Intel PSE IS21
device pci 12.0 on end # GSPI2
device pci 12.3 on end # Management Engine UMA Access
device pci 12.4 on end # Management Engine PTT DMA Controller
device pci 12.5 off end # UFS0
device pci 12.7 off end # UFS1
device pci 13.0 off end # Intel PSE GSPI0
device pci 13.1 off end # Intel PSE GSPI1
device pci 13.2 off end # Intel PSE GSPI2
device pci 13.3 off end # Intel PSE GSPI3
device pci 13.4 off end # Intel PSE GPIO0
device pci 13.5 off end # Intel PSE GPIO1
device pci 14.0 on end # USB3.1 xHCI
device pci 14.1 off end # USB3.1 xDCI (OTG)
device pci 15.0 on end # I2C0
device pci 15.1 on end # I2C1
device pci 15.2 on # I2C2
# Enable external RTC chip
chip drivers/i2c/rx6110sa
register "bus_speed" = "I2C_SPEED_STANDARD"
register "pmon_sampling" = "PMON_SAMPL_256_MS"
register "bks_on" = "0"
register "bks_off" = "1"
register "iocut_en" = "1"
register "set_user_date" = "1"
register "user_year" = "04"
register "user_month" = "07"
register "user_day" = "01"
register "user_weekday" = "4"
device i2c 0x32 on end # RTC RX6110 SA
end
end
device pci 15.3 on end # I2C3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 on end # Management Engine Interface 2
device pci 16.4 on end # Management Engine Interface 3
device pci 16.5 on end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 18.0 off end # Intel PSE I2C7
device pci 18.1 off end # Intel PSE CAN0
device pci 18.2 off end # Intel PSE CAN1
device pci 18.3 off end # Intel PSE QEP0
device pci 18.4 off end # Intel PSE QEP1
device pci 18.5 off end # Intel PSE QEP2
device pci 18.6 off end # Intel PSE QEP3
device pci 19.0 on end # I2C4
device pci 19.1 on end # I2C5
device pci 19.2 on end # UART2
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
device pci 1a.3 off end # Intel Safety Island
device pci 1b.0 off end # Intel PSE I2C0
device pci 1b.1 off end # Intel PSE I2C1
device pci 1b.2 off end # Intel PSE I2C2
device pci 1b.3 off end # Intel PSE I2C3
device pci 1b.4 off end # Intel PSE I2C4
device pci 1b.5 off end # Intel PSE I2C5
device pci 1b.6 off end # Intel PSE I2C6
device pci 1c.0 on end # RP1 (pcie0 single VC)
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.3 on end # RP4 (pcie0 single VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1c.5 on end # RP6 (pcie2 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0
device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1
device pci 1d.3 off end # Intel PSE DMA0
device pci 1d.4 off end # Intel PSE DMA1
device pci 1d.5 off end # Intel PSE DMA2
device pci 1d.6 off end # Intel PSE PWM
device pci 1d.7 off end # Intel PSE ADC
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1
device pci 1e.2 off end # GSPI0
device pci 1e.3 off end # GSPI1
device pci 1e.4 on end # PCH Time-Sensitive Networking GbE
device pci 1e.6 on end # HPET
device pci 1e.7 on end # IOAPIC
device pci 1f.0 on # eSPI Interface
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.1 on end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 off end # Intel cAVS/HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI (flash & TPM)
device pci 1f.7 off end # PCH Intel Trace Hub
end
end
|
