1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
Name (PICP, Package () {
/* D31: cAVS, SMBus, GbE, Nothpeak */
Package () { 0x001FFFFF, 0, 0, 16 },
Package () { 0x001FFFFF, 1, 0, 17 },
Package () { 0x001FFFFF, 2, 0, 18 },
Package () { 0x001FFFFF, 3, 0, 19 },
/* D30: SerialIo and SCS */
Package () { 0x001EFFFF, 0, 0, 20 },
Package () { 0x001EFFFF, 1, 0, 21 },
Package () { 0x001EFFFF, 2, 0, 22 },
Package () { 0x001EFFFF, 3, 0, 23 },
/* D29: PCI Express Port 9-16 */
Package () { 0x001DFFFF, 0, 0, 16 },
Package () { 0x001DFFFF, 1, 0, 17 },
Package () { 0x001DFFFF, 2, 0, 18 },
Package () { 0x001DFFFF, 3, 0, 19 },
/* D28: PCI Express Port 1-8 */
Package () { 0x001CFFFF, 0, 0, 16 },
Package () { 0x001CFFFF, 1, 0, 17 },
Package () { 0x001CFFFF, 2, 0, 18 },
Package () { 0x001CFFFF, 3, 0, 19 },
/* D27: PCI Express Port 17-20 */
Package () { 0x001BFFFF, 0, 0, 16 },
Package () { 0x001BFFFF, 1, 0, 17 },
Package () { 0x001BFFFF, 2, 0, 18 },
Package () { 0x001BFFFF, 3, 0, 19 },
/* D25: SerialIo */
Package () { 0x0019FFFF, 0, 0, 32 },
Package () { 0x0019FFFF, 1, 0, 33 },
Package () { 0x0019FFFF, 2, 0, 34 },
/* D22: CSME (HECI, IDE-R, KT redirection */
Package () { 0x0016FFFF, 0, 0, 16 },
Package () { 0x0016FFFF, 1, 0, 17 },
Package () { 0x0016FFFF, 2, 0, 18 },
Package () { 0x0016FFFF, 3, 0, 19 },
/* D21: SerialIo */
Package () { 0x0015FFFF, 0, 0, 16 },
Package () { 0x0015FFFF, 1, 0, 17 },
Package () { 0x0015FFFF, 2, 0, 18 },
Package () { 0x0015FFFF, 3, 0, 19 },
/* D20: xHCI, OTG, Thermal, Camera */
Package () { 0x0014FFFF, 0, 0, 16 },
Package () { 0x0014FFFF, 1, 0, 17 },
Package () { 0x0014FFFF, 2, 0, 18 },
Package () { 0x0014FFFF, 3, 0, 19 },
/* D19: Integrated Sensor Hub */
Package () { 0x0013FFFF, 0, 0, 20 },
/* P.E.G. Root Port D1F0 */
Package () { 0x0001FFFF, 0, 0, 16 },
Package () { 0x0001FFFF, 1, 0, 17 },
Package () { 0x0001FFFF, 2, 0, 18 },
Package () { 0x0001FFFF, 3, 0, 19 },
/* SA IGFX Device */
Package () { 0x0002FFFF, 0, 0, 16 },
/* SA Thermal Device */
Package () { 0x0004FFFF, 0, 0, 16 },
/* SA SkyCam Device */
Package () { 0x0005FFFF, 0, 0, 16 },
/* SA GMM Device */
Package () { 0x0008FFFF, 0, 0, 16 },
})
Name (PICN, Package () {
/* D31: cAVS, SMBus, GbE, Nothpeak */
Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
/* D29: PCI Express Port 9-16 */
Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
/* D28: PCI Express Port 1-8 */
Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
/* D27: PCI Express Port 17-20 */
Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
/* D23 */
Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
/* D22: CSME (HECI, IDE-R, KT redirection */
Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
/* D20: xHCI, OTG, Thermal, Camera */
Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
/* P.E.G. Root Port D1F0 */
Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
/* SA IGFX Device */
Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
/* SA Thermal Device */
Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
/* SA Skycam Device */
Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
/* SA GMM Device */
Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
})
Method (_PRT)
{
If (PICM) {
Return (^PICP)
} Else {
Return (^PICN)
}
}
|
