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| author | Ray Ni <ray.ni@intel.com> | 2019-06-12 11:04:52 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-07-10 16:00:06 +0800 |
| commit | 7c5010c7f88b790f4524c4a5311819e3af5e2752 (patch) | |
| tree | af076f1cc126259a437744a5667da6a0327258a8 | |
| parent | 7e56f8928d8461d820a81a50908adf648279f1dc (diff) | |
| download | edk2-7c5010c7f88b790f4524c4a5311819e3af5e2752.tar.gz edk2-7c5010c7f88b790f4524c4a5311819e3af5e2752.tar.bz2 edk2-7c5010c7f88b790f4524c4a5311819e3af5e2752.zip | |
MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
5-level paging is documented in white paper:
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf
Commit f8113e25001e715390127f23e2197252cbd6d1a2
changed Cpuid.h already.
This patch updates IA32_CR4 structure to include LA57 field.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index ebd7dd274c..a22bfc9fad 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -5324,7 +5324,8 @@ typedef union { UINT32 OSXMMEXCPT:1; ///< Operating System Support for
///< Unmasked SIMD Floating Point
///< Exceptions.
- UINT32 Reserved_0:2; ///< Reserved.
+ UINT32 Reserved_2:1; ///< Reserved.
+ UINT32 LA57:1; ///< Linear Address 57bit.
UINT32 VMXE:1; ///< VMX Enable
UINT32 Reserved_1:18; ///< Reserved.
} Bits;
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