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| author | Wenyi Xie <xiewenyi2@huawei.com> | 2021-05-27 20:04:26 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-06-02 07:55:57 +0000 |
| commit | b5379899b38ed84561db6dc07dc4641a049ae238 (patch) | |
| tree | e41a7bb9fa9cdb31916a3ef1052b906acf2897e3 | |
| parent | b233eb1849ac01bdd5b24ea84460a2e481a4c5a9 (diff) | |
| download | edk2-b5379899b38ed84561db6dc07dc4641a049ae238.tar.gz edk2-b5379899b38ed84561db6dc07dc4641a049ae238.tar.bz2 edk2-b5379899b38ed84561db6dc07dc4641a049ae238.zip | |
MdeModulePkg/Xhci: Fix TRT when data length is 0
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418
According to xhci spec, at USB packet level, a Control Transfer
consists of multiple transactions partitioned into stages: a
setup stage, an optional data stage, and a terminating status
stage. If Data Stage does not exist, the Transfer Type flag(TRT)
should be No Data Stage.
So if data length equals to 0, TRT is set to 0.
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 13 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 13 |
2 files changed, 18 insertions, 8 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index dc36945962..7cbc9a8502 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -298,10 +298,15 @@ XhcCreateTransferTrb ( TrbStart->TrbCtrSetup.IOC = 1;
TrbStart->TrbCtrSetup.IDT = 1;
TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
- if (Urb->Ep.Direction == EfiUsbDataIn) {
- TrbStart->TrbCtrSetup.TRT = 3;
- } else if (Urb->Ep.Direction == EfiUsbDataOut) {
- TrbStart->TrbCtrSetup.TRT = 2;
+ if (Urb->DataLen > 0) {
+ if (Urb->Ep.Direction == EfiUsbDataIn) {
+ TrbStart->TrbCtrSetup.TRT = 3;
+ } else if (Urb->Ep.Direction == EfiUsbDataOut) {
+ TrbStart->TrbCtrSetup.TRT = 2;
+ } else {
+ DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));
+ ASSERT (FALSE);
+ }
} else {
TrbStart->TrbCtrSetup.TRT = 0;
}
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c index 32d72ef03c..5b9892a1cb 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -291,10 +291,15 @@ XhcPeiCreateTransferTrb ( TrbStart->TrbCtrSetup.IOC = 1;
TrbStart->TrbCtrSetup.IDT = 1;
TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;
- if (Urb->Ep.Direction == EfiUsbDataIn) {
- TrbStart->TrbCtrSetup.TRT = 3;
- } else if (Urb->Ep.Direction == EfiUsbDataOut) {
- TrbStart->TrbCtrSetup.TRT = 2;
+ if (Urb->DataLen > 0) {
+ if (Urb->Ep.Direction == EfiUsbDataIn) {
+ TrbStart->TrbCtrSetup.TRT = 3;
+ } else if (Urb->Ep.Direction == EfiUsbDataOut) {
+ TrbStart->TrbCtrSetup.TRT = 2;
+ } else {
+ DEBUG ((DEBUG_ERROR, "XhcPeiCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n"));
+ ASSERT (FALSE);
+ }
} else {
TrbStart->TrbCtrSetup.TRT = 0;
}
|