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| author | Harry Liebel <Harry.Liebel@arm.com> | 2014-08-04 08:44:11 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-04 08:44:11 +0000 |
| commit | 87280982b803cebd4b47980ec09eaa45a13d7676 (patch) | |
| tree | a488febeb11c1c1949949ee6fe67bf44dfeb4880 /BaseTools | |
| parent | 4a00645100049d31dd8937b0ada6db40e56fe2c6 (diff) | |
| download | edk2-87280982b803cebd4b47980ec09eaa45a13d7676.tar.gz edk2-87280982b803cebd4b47980ec09eaa45a13d7676.tar.bz2 edk2-87280982b803cebd4b47980ec09eaa45a13d7676.zip | |
BaseTools: Add AArch64 ADR_PREL_LO21 and R_AARCH64_CONDBR19
relocations
- ADR_PREL_LO21: support for loading a PC relative label offset.
- R_AARCH64_CONDBR19: support for conditional branch instruction (ELF64 code: 280).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Yingke Liu <yingke.d.liu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15745 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BaseTools')
| -rw-r--r-- | BaseTools/Source/C/GenFw/Elf64Convert.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c index 606c7284f7..3f9a11a4bc 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -1,7 +1,7 @@ /** @file
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
-Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
@@ -690,6 +690,18 @@ WriteSections64 ( switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_AARCH64_ADR_PREL_LO21:
+ if (Rel->r_addend != 0 ) { /* TODO */
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_ADR_PREL_LO21 Need to fixup with addend!.");
+ }
+ break;
+
+ case R_AARCH64_CONDBR19:
+ if (Rel->r_addend != 0 ) { /* TODO */
+ Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_CONDBR19 Need to fixup with addend!.");
+ }
+ break;
+
case R_AARCH64_LD_PREL_LO19:
if (Rel->r_addend != 0 ) { /* TODO */
Error (NULL, 0, 3000, "Invalid", "AArch64: R_AARCH64_LD_PREL_LO19 Need to fixup with addend!.");
@@ -784,6 +796,12 @@ WriteRelocations64 ( } else if (mEhdr->e_machine == EM_AARCH64) {
// AArch64 GCC uses RELA relocation, so all relocations has to be fixed up. ARM32 uses REL.
switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_AARCH64_ADR_PREL_LO21:
+ break;
+
+ case R_AARCH64_CONDBR19:
+ break;
+
case R_AARCH64_LD_PREL_LO19:
break;
|