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| author | Pierre Gondois <pierre.gondois@arm.com> | 2023-10-04 15:53:55 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-08-01 13:41:01 +0000 |
| commit | 368f9b62a2f284b95b90e5083fcc3f434c3a35c2 (patch) | |
| tree | f18f7651520cd07cdf3b2f046b22dd8173d92f8a /CryptoPkg | |
| parent | 9403422f214acf2a82821836bbf6dcdee2beb491 (diff) | |
| download | edk2-368f9b62a2f284b95b90e5083fcc3f434c3a35c2.tar.gz edk2-368f9b62a2f284b95b90e5083fcc3f434c3a35c2.tar.bz2 edk2-368f9b62a2f284b95b90e5083fcc3f434c3a35c2.zip | |
CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
Add AARCH64 specific implementations of:
- OPENSSL_cpuid_setup(), probing hardware capabilitie
(presence of FEAT_AES, etc.)
- OPENSSL_rdtsc(), returning non-trusted entropy by accessing
system counter.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Diffstat (limited to 'CryptoPkg')
| -rw-r--r-- | CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf | 1 | ||||
| -rw-r--r-- | CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf | 1 | ||||
| -rw-r--r-- | CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c | 107 |
3 files changed, 109 insertions, 0 deletions
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf index 3d4917b29f..912fd07f09 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf @@ -1329,6 +1329,7 @@ # Autogenerated files list ends here
[Sources.AARCH64]
+ OpensslStub/AArch64Cap.c
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
$(OPENSSL_PATH)/crypto/aes/aes_cfb.c
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf index 715c483536..8f8b94c3ac 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf @@ -1432,6 +1432,7 @@ # Autogenerated files list ends here
[Sources.AARCH64]
+ OpensslStub/AArch64Cap.c
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
$(OPENSSL_PATH)/crypto/aes/aes_cfb.c
diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c new file mode 100644 index 0000000000..e45961a87b --- /dev/null +++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c @@ -0,0 +1,107 @@ +/** @file
+ Arm capabilities probing.
+
+ Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <openssl/types.h>
+#include "crypto/arm_arch.h"
+
+#include <Library/BaseLib.h>
+
+/** Get bits from a value.
+
+ Shift the input value from 'shift' bits and apply 'mask'.
+
+ @param value The value to get the bits from.
+ @param shift Index of the bits to read.
+ @param mask Mask to apply to the value once shifted.
+
+ @return The desired bitfield from the value.
+**/
+#define GET_BITFIELD(value, shift, mask) \
+ ((value >> shift) & mask)
+
+UINT32 OPENSSL_armcap_P = 0;
+
+void
+OPENSSL_cpuid_setup (
+ void
+ )
+{
+ UINT64 Isar0;
+
+ OPENSSL_armcap_P = 0;
+ Isar0 = ArmReadIdAA64Isar0Reg ();
+
+ /* Access to EL0 registers is possible from higher ELx. */
+ OPENSSL_armcap_P |= ARMV8_CPUID;
+ /* Access to Physical timer is possible. */
+ OPENSSL_armcap_P |= ARMV7_TICK;
+
+ /* Neon support is not guaranteed, but it is assumed to be present.
+ Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support
+ */
+ OPENSSL_armcap_P |= ARMV7_NEON;
+
+ if (GET_BITFIELD (
+ Isar0,
+ ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_AES_MASK
+ ) != 0)
+ {
+ OPENSSL_armcap_P |= ARMV8_AES;
+ }
+
+ if (GET_BITFIELD (
+ Isar0,
+ ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA1_MASK
+ ) != 0)
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA1;
+ }
+
+ if (GET_BITFIELD (
+ Isar0,
+ ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA2_MASK
+ ) != 0)
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA256;
+ }
+
+ if (GET_BITFIELD (
+ Isar0,
+ ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_AES_MASK
+ ) >= ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK)
+ {
+ OPENSSL_armcap_P |= ARMV8_PMULL;
+ }
+
+ if (GET_BITFIELD (
+ Isar0,
+ ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA2_MASK
+ ) >= ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK)
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA512;
+ }
+}
+
+/** Read system counter value.
+
+ Used to get some non-trusted entropy.
+
+ @return Lower bits of the physical counter.
+**/
+uint32_t
+OPENSSL_rdtsc (
+ void
+ )
+{
+ return (UINT32)ArmReadCntPctReg ();
+}
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