OvmfPkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the OvmfPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>

1 files changed, 110 insertions, 93 deletions

diff --git a/OvmfPkg/Bhyve/PlatformPei/Platform.c b/OvmfPkg/Bhyve/PlatformPei/Platform.c
index c23b906733..eba7c60fce 100644
--- a/OvmfPkg/Bhyve/PlatformPei/Platform.c
+++ b/OvmfPkg/Bhyve/PlatformPei/Platform.c
@@ -36,7 +36,7 @@
 #include "Platform.h"

 #include "Cmos.h"

 

-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {

+EFI_MEMORY_TYPE_INFORMATION  mDefaultMemoryTypeInformation[] = {

   { EfiACPIMemoryNVS,       0x004 },

   { EfiACPIReclaimMemory,   0x008 },

   { EfiReservedMemoryType,  0x004 },

@@ -47,8 +47,7 @@ EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
   { EfiMaxMemoryType,       0x000 }

 };

 

-

-EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {

+EFI_PEI_PPI_DESCRIPTOR  mPpiBootMode[] = {

   {

     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,

     &gEfiPeiMasterBootModePpiGuid,

@@ -56,27 +55,26 @@ EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
   }

 };

 

+UINT16  mHostBridgeDevId;

 

-UINT16 mHostBridgeDevId;

-

-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;

+EFI_BOOT_MODE  mBootMode = BOOT_WITH_FULL_CONFIGURATION;

 

-BOOLEAN mS3Supported = FALSE;

+BOOLEAN  mS3Supported = FALSE;

 

-UINT32 mMaxCpuCount;

+UINT32  mMaxCpuCount;

 

 VOID

 AddIoMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS        MemoryBase,

-  UINT64                      MemorySize

+  EFI_PHYSICAL_ADDRESS  MemoryBase,

+  UINT64                MemorySize

   )

 {

   BuildResourceDescriptorHob (

     EFI_RESOURCE_MEMORY_MAPPED_IO,

-      EFI_RESOURCE_ATTRIBUTE_PRESENT     |

-      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-      EFI_RESOURCE_ATTRIBUTE_TESTED,

+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |

+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

+    EFI_RESOURCE_ATTRIBUTE_TESTED,

     MemoryBase,

     MemorySize

     );

@@ -84,23 +82,23 @@ AddIoMemoryBaseSizeHob (
 

 VOID

 AddReservedMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS        MemoryBase,

-  UINT64                      MemorySize,

-  BOOLEAN                     Cacheable

+  EFI_PHYSICAL_ADDRESS  MemoryBase,

+  UINT64                MemorySize,

+  BOOLEAN               Cacheable

   )

 {

   BuildResourceDescriptorHob (

     EFI_RESOURCE_MEMORY_RESERVED,

-      EFI_RESOURCE_ATTRIBUTE_PRESENT     |

-      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-      (Cacheable ?

-       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

-       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

-       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :

-       0

-       ) |

-      EFI_RESOURCE_ATTRIBUTE_TESTED,

+    EFI_RESOURCE_ATTRIBUTE_PRESENT     |

+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

+    (Cacheable ?

+     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

+     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

+     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :

+     0

+    ) |

+    EFI_RESOURCE_ATTRIBUTE_TESTED,

     MemoryBase,

     MemorySize

     );

@@ -108,53 +106,50 @@ AddReservedMemoryBaseSizeHob (
 

 VOID

 AddIoMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS        MemoryBase,

-  EFI_PHYSICAL_ADDRESS        MemoryLimit

+  EFI_PHYSICAL_ADDRESS  MemoryBase,

+  EFI_PHYSICAL_ADDRESS  MemoryLimit

   )

 {

   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));

 }

 

-

 VOID

 AddMemoryBaseSizeHob (

-  EFI_PHYSICAL_ADDRESS        MemoryBase,

-  UINT64                      MemorySize

+  EFI_PHYSICAL_ADDRESS  MemoryBase,

+  UINT64                MemorySize

   )

 {

   BuildResourceDescriptorHob (

     EFI_RESOURCE_SYSTEM_MEMORY,

-      EFI_RESOURCE_ATTRIBUTE_PRESENT |

-      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

-      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

-      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

-      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

-      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |

-      EFI_RESOURCE_ATTRIBUTE_TESTED,

+    EFI_RESOURCE_ATTRIBUTE_PRESENT |

+    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |

+    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |

+    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |

+    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |

+    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |

+    EFI_RESOURCE_ATTRIBUTE_TESTED,

     MemoryBase,

     MemorySize

     );

 }

 

-

 VOID

 AddMemoryRangeHob (

-  EFI_PHYSICAL_ADDRESS        MemoryBase,

-  EFI_PHYSICAL_ADDRESS        MemoryLimit

+  EFI_PHYSICAL_ADDRESS  MemoryBase,

+  EFI_PHYSICAL_ADDRESS  MemoryLimit

   )

 {

   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));

 }

 

-

 VOID

 MemMapInitialization (

   VOID

   )

 {

-  UINT64        PciIoBase;

-  UINT64        PciIoSize;

-  RETURN_STATUS PcdStatus;

+  UINT64         PciIoBase;

+  UINT64         PciIoSize;

+  RETURN_STATUS  PcdStatus;

 

   PciIoBase = 0xC000;

   PciIoSize = 0x4000;

@@ -165,7 +160,7 @@ MemMapInitialization (
   BuildGuidDataHob (

     &gEfiMemoryTypeInformationGuid,

     mDefaultMemoryTypeInformation,

-    sizeof(mDefaultMemoryTypeInformation)

+    sizeof (mDefaultMemoryTypeInformation)

     );

 

   //

@@ -179,7 +174,7 @@ MemMapInitialization (
     UINT32  PciBase;

     UINT32  PciSize;

 

-    TopOfLowRam = GetSystemMemorySizeBelow4gb ();

+    TopOfLowRam  = GetSystemMemorySizeBelow4gb ();

     PciExBarBase = 0;

     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {

       //

@@ -192,8 +187,9 @@ MemMapInitialization (
       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);

     } else {

       PciBase = (UINT32)PcdGet64 (PcdPciMmio32Base);

-      if (PciBase == 0)

+      if (PciBase == 0) {

         PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;

+      }

     }

 

     //

@@ -242,10 +238,14 @@ MemMapInitialization (
       // uncacheable reserved memory right here.

       //

       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);

-      BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,

-        EfiReservedMemoryType);

+      BuildMemoryAllocationHob (

+        PciExBarBase,

+        SIZE_256MB,

+        EfiReservedMemoryType

+        );

     }

-    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);

+

+    AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);

 

     //

     // On Q35, the IO Port space is available for PCI resource allocations from

@@ -287,8 +287,8 @@ PciExBarInitialization (
   )

 {

   union {

-    UINT64 Uint64;

-    UINT32 Uint32[2];

+    UINT64    Uint64;

+    UINT32    Uint32[2];

   } PciExBarBase;

 

   //

@@ -327,13 +327,13 @@ MiscInitialization (
   VOID

   )

 {

-  UINTN         PmCmd;

-  UINTN         Pmba;

-  UINT32        PmbaAndVal;

-  UINT32        PmbaOrVal;

-  UINTN         AcpiCtlReg;

-  UINT8         AcpiEnBit;

-  RETURN_STATUS PcdStatus;

+  UINTN          PmCmd;

+  UINTN          Pmba;

+  UINT32         PmbaAndVal;

+  UINT32         PmbaOrVal;

+  UINTN          AcpiCtlReg;

+  UINT8          AcpiEnBit;

+  RETURN_STATUS  PcdStatus;

 

   //

   // Disable A20 Mask

@@ -370,11 +370,16 @@ MiscInitialization (
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;

       break;

     default:

-      DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",

-        __FUNCTION__, mHostBridgeDevId));

+      DEBUG ((

+        DEBUG_ERROR,

+        "%a: Unknown Host Bridge Device ID: 0x%04x\n",

+        __FUNCTION__,

+        mHostBridgeDevId

+        ));

       ASSERT (FALSE);

       return;

   }

+

   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);

   ASSERT_RETURN_ERROR (PcdStatus);

 

@@ -417,17 +422,17 @@ MiscInitialization (
   }

 }

 

-

 VOID

 BootModeInitialization (

   VOID

   )

 {

-  EFI_STATUS    Status;

+  EFI_STATUS  Status;

 

   if (CmosRead8 (0xF) == 0xFE) {

     mBootMode = BOOT_ON_S3_RESUME;

   }

+

   CmosWrite8 (0xF, 0x00);

 

   Status = PeiServicesSetBootMode (mBootMode);

@@ -437,13 +442,12 @@ BootModeInitialization (
   ASSERT_EFI_ERROR (Status);

 }

 

-

 VOID

 ReserveEmuVariableNvStore (

   )

 {

-  EFI_PHYSICAL_ADDRESS VariableStore;

-  RETURN_STATUS        PcdStatus;

+  EFI_PHYSICAL_ADDRESS  VariableStore;

+  RETURN_STATUS         PcdStatus;

 

   //

   // Allocate storage for NV variables early on so it will be

@@ -453,25 +457,25 @@ ReserveEmuVariableNvStore (
   //

   VariableStore =

     (EFI_PHYSICAL_ADDRESS)(UINTN)

-      AllocateRuntimePages (

-        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))

-        );

-  DEBUG ((DEBUG_INFO,

-          "Reserved variable store memory: 0x%lX; size: %dkb\n",

-          VariableStore,

-          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024

-        ));

+    AllocateRuntimePages (

+      EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))

+      );

+  DEBUG ((

+    DEBUG_INFO,

+    "Reserved variable store memory: 0x%lX; size: %dkb\n",

+    VariableStore,

+    (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024

+    ));

   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);

   ASSERT_RETURN_ERROR (PcdStatus);

 }

 

-

 VOID

 DebugDumpCmos (

   VOID

   )

 {

-  UINT32 Loop;

+  UINT32  Loop;

 

   DEBUG ((DEBUG_INFO, "CMOS:\n"));

 

@@ -479,6 +483,7 @@ DebugDumpCmos (
     if ((Loop % 0x10) == 0) {

       DEBUG ((DEBUG_INFO, "%02x:", Loop));

     }

+

     DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));

     if ((Loop % 0x10) == 0xf) {

       DEBUG ((DEBUG_INFO, "\n"));

@@ -486,27 +491,34 @@ DebugDumpCmos (
   }

 }

 

-

 VOID

 S3Verification (

   VOID

   )

 {

-#if defined (MDE_CPU_X64)

+ #if defined (MDE_CPU_X64)

   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {

-    DEBUG ((DEBUG_ERROR,

-      "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));

-    DEBUG ((DEBUG_ERROR,

+    DEBUG ((

+      DEBUG_ERROR,

+      "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",

+      __FUNCTION__

+      ));

+    DEBUG ((

+      DEBUG_ERROR,

       "%a: Please disable S3 on the QEMU command line (see the README),\n",

-      __FUNCTION__));

-    DEBUG ((DEBUG_ERROR,

-      "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));

+      __FUNCTION__

+      ));

+    DEBUG ((

+      DEBUG_ERROR,

+      "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n",

+      __FUNCTION__

+      ));

     ASSERT (FALSE);

     CpuDeadLoop ();

   }

-#endif

-}

 

+ #endif

+}

 

 /**

   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.

@@ -517,8 +529,8 @@ MaxCpuCountInitialization (
   VOID

   )

 {

-  UINT16        ProcessorCount = 0;

-  RETURN_STATUS PcdStatus;

+  UINT16         ProcessorCount = 0;

+  RETURN_STATUS  PcdStatus;

 

   //

   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount

@@ -528,6 +540,7 @@ MaxCpuCountInitialization (
     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);

     return;

   }

+

   //

   // Otherwise, set mMaxCpuCount to the value reported by QEMU.

   //

@@ -542,11 +555,14 @@ MaxCpuCountInitialization (
   ASSERT_RETURN_ERROR (PcdStatus);

   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);

   ASSERT_RETURN_ERROR (PcdStatus);

-  DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,

-    ProcessorCount));

+  DEBUG ((

+    DEBUG_INFO,

+    "%a: QEMU reports %d processor(s)\n",

+    __FUNCTION__,

+    ProcessorCount

+    ));

 }

 

-

 /**

   Perform Platform PEI initialization.

 

@@ -596,6 +612,7 @@ InitializePlatform (
     if (!FeaturePcdGet (PcdSmmSmramRequire)) {

       ReserveEmuVariableNvStore ();

     }

+

     PeiFvInitialization ();

     MemMapInitialization ();

     NoexecDxeInitialization ();