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| author | Tuan Phan <tphan@ventanamicro.com> | 2023-07-14 12:08:19 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-07-15 14:10:18 +0000 |
| commit | fbec9aec00c2cc10de439f2f0c3accb52488d32f (patch) | |
| tree | 8d4a4b2a4fd99133e0dec6aee51cfb5a3ec91923 /OvmfPkg/RiscVVirt | |
| parent | 7178047402c07d369a2a3a0b0e5118c5e3d90ddc (diff) | |
| download | edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.tar.gz edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.tar.bz2 edk2-fbec9aec00c2cc10de439f2f0c3accb52488d32f.zip | |
MdePkg/Register: RISC-V: Add satp mode bits shift definition
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'OvmfPkg/RiscVVirt')
0 files changed, 0 insertions, 0 deletions