UefiCpuPkg: Extend SMM CPU Service with rendezvous support.

REF? https://bugzilla.tianocore.org/show_bug.cgi?id=3815

This patch define a new Protocol with the new services
SmmWaitForAllProcessor(), which can be used by SMI handler
to optionally wait for other APs to complete SMM rendezvous in
relaxed AP mode.

A new library SmmCpuRendezvousLib is provided to abstract the service
into library API to simple SMI handler code.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Zhihao Li <zhihao.li@intel.com>

Signed-off-by: Zhihao Li <zhihao.li@intel.com>

4 files changed, 114 insertions, 9 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 5d624f8e9e..2ebf4543c3 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -1,7 +1,7 @@
 /** @file

 Implementation of SMM CPU Services Protocol.

 

-Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>

 SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

@@ -20,6 +20,13 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
   SmmRegisterExceptionHandler

 };

 

+//

+// EDKII SMM CPU Rendezvous Service Protocol instance

+//

+EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL  mSmmCpuRendezvousService = {

+  SmmCpuRendezvous

+};

+

 /**

   Gets processor information on the requested processor at the instant this call is made.

 

@@ -350,6 +357,7 @@ SmmRegisterExceptionHandler (
   @param ImageHandle The firmware allocated handle for the EFI image.

 

   @retval EFI_SUCCESS    EFI SMM CPU Services Protocol was installed successfully.

+  @retval OTHER          Fail to install Protocol.

 **/

 EFI_STATUS

 InitializeSmmCpuServices (

@@ -365,5 +373,64 @@ InitializeSmmCpuServices (
                     &mSmmCpuService

                     );

   ASSERT_EFI_ERROR (Status);

+  if (EFI_ERROR (Status)) {

+    return Status;

+  }

+

+  Status = gSmst->SmmInstallProtocolInterface (

+                    &Handle,

+                    &gEdkiiSmmCpuRendezvousProtocolGuid,

+                    EFI_NATIVE_INTERFACE,

+                    &mSmmCpuRendezvousService

+                    );

+  ASSERT_EFI_ERROR (Status);

+  return Status;

+}

+

+/**

+  Wait for all processors enterring SMM until all CPUs are already synchronized or not.

+

+  If BlockingMode is False, timeout value is zero.

+

+  @param This          A pointer to the EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL instance.

+  @param BlockingMode  Blocking mode or non-blocking mode.

+

+  @retval EFI_SUCCESS  All avaiable APs arrived.

+  @retval EFI_TIMEOUT  Wait for all APs until timeout.

+

+**/

+EFI_STATUS

+EFIAPI

+SmmCpuRendezvous (

+  IN EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL  *This,

+  IN BOOLEAN                            BlockingMode

+  )

+{

+  EFI_STATUS  Status;

+

+  //

+  // Return success immediately if all CPUs are already synchronized.

+  //

+  if (mSmmMpSyncData->AllApArrivedWithException) {

+    Status = EFI_SUCCESS;

+    goto ON_EXIT;

+  }

+

+  if (!BlockingMode) {

+    Status = EFI_TIMEOUT;

+    goto ON_EXIT;

+  }

+

+  //

+  // There are some APs outside SMM, Wait for all avaiable APs to arrive.

+  //

+  SmmWaitForApArrival ();

+  Status = mSmmMpSyncData->AllApArrivedWithException ? EFI_SUCCESS : EFI_TIMEOUT;

+

+ON_EXIT:

+  if (!mSmmMpSyncData->AllApArrivedWithException) {

+    DEBUG ((DEBUG_INFO, "EdkiiSmmWaitForAllApArrival: Timeout to wait all APs arrival\n"));

+  }

+

   return Status;

 }

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 882dee4fe2..13c2cb8da4 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1,7 +1,7 @@
 /** @file

 SMM MP service implementation

 

-Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>

 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>

 

 SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -293,10 +293,14 @@ SmmWaitForApArrival (
   // Sync with APs 1st timeout

   //

   for (Timer = StartSyncTimer ();

-       !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&

-       !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);

+       !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal);

        )

   {

+    mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);

+    if (mSmmMpSyncData->AllApArrivedWithException) {

+      break;

+    }

+

     CpuPause ();

   }

 

@@ -330,10 +334,14 @@ SmmWaitForApArrival (
     // Sync with APs 2nd timeout.

     //

     for (Timer = StartSyncTimer ();

-         !IsSyncTimerTimeout (Timer) &&

-         !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);

+         !IsSyncTimerTimeout (Timer);

          )

     {

+      mSmmMpSyncData->AllApArrivedWithException = AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);

+      if (mSmmMpSyncData->AllApArrivedWithException) {

+        break;

+      }

+

       CpuPause ();

     }

   }

@@ -1887,6 +1895,8 @@ InitializeMpSyncData (
     *mSmmMpSyncData->InsideSmm     = FALSE;

     *mSmmMpSyncData->AllCpusInSync = FALSE;

 

+    mSmmMpSyncData->AllApArrivedWithException = FALSE;

+

     for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) {

       mSmmMpSyncData->CpuData[CpuIndex].Busy =

         (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 26d07c5b5e..aed872836c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,7 @@
 /** @file

 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.

 

-Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>

 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>

 

 SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -428,6 +428,7 @@ typedef struct {
   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;

   volatile BOOLEAN              SwitchBsp;

   volatile BOOLEAN              *CandidateBsp;

+  volatile BOOLEAN              AllApArrivedWithException;

   EFI_AP_PROCEDURE              StartupProcedure;

   VOID                          *StartupProcArgs;

 } SMM_DISPATCHER_MP_SYNC_DATA;

@@ -1488,4 +1489,30 @@ IsRestrictedMemoryAccess (
   VOID

   );

 

+/**

+  Choose blocking or non-blocking mode to Wait for all APs.

+

+  @param[in]  This                  A pointer to the EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL instance.

+  @param[in]  BlockingMode          Blocking or non-blocking mode.

+

+  @retval EFI_SUCCESS               All APs have arrived SMM mode except SMI disabled APs.

+  @retval EFI_TIMEOUT               There are APs not in SMM mode in given timeout constraint.

+

+**/

+EFI_STATUS

+EFIAPI

+SmmCpuRendezvous (

+  IN  EDKII_SMM_CPU_RENDEZVOUS_PROTOCOL  *This,

+  IN  BOOLEAN                            BlockingMode

+  );

+

+/**

+  Insure when this function returns, no AP will execute normal mode code before entering SMM, except SMI disabled APs.

+

+**/

+VOID

+SmmWaitForApArrival (

+  VOID

+  );

+

 #endif

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index 0e88071c70..deef00f9c6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -4,7 +4,7 @@
 # This SMM driver performs SMM initialization, deploy SMM Entry Vector,

 # provides CPU specific services in SMM.

 #

-# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>

 # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>

 #

 # SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -107,7 +107,8 @@
   gEfiSmmReadyToLockProtocolGuid           ## NOTIFY

   gEfiSmmCpuServiceProtocolGuid            ## PRODUCES

   gEdkiiSmmMemoryAttributeProtocolGuid     ## PRODUCES

-  gEfiMmMpProtocolGuid                    ## PRODUCES

+  gEfiMmMpProtocolGuid                     ## PRODUCES

+  gEdkiiSmmCpuRendezvousProtocolGuid       ## PRODUCES

 

 [Guids]

   gEfiAcpiVariableGuid                     ## SOMETIMES_CONSUMES ## HOB # it is used for S3 boot.