diff options
| author | David Wei <david.wei@intel.com> | 2015-01-12 09:37:20 +0000 |
|---|---|---|
| committer | zwei4 <zwei4@Edk2> | 2015-01-12 09:37:20 +0000 |
| commit | 3cbfba02fef9dae07a041fdbf2e89611d72d6f90 (patch) | |
| tree | 0b3bf0783124d38a191e09736492c0141aa36c15 /Vlv2TbltDevicePkg/PlatformDxe | |
| parent | 6f785cfcc304c48ec04e542ee429df95e7b51bc5 (diff) | |
| download | edk2-3cbfba02fef9dae07a041fdbf2e89611d72d6f90.tar.gz edk2-3cbfba02fef9dae07a041fdbf2e89611d72d6f90.tar.bz2 edk2-3cbfba02fef9dae07a041fdbf2e89611d72d6f90.zip | |
Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to
https://svn.code.sf.net/p/edk2/code/trunk/edk2/,
which are for MinnowBoard MAX open source project.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'Vlv2TbltDevicePkg/PlatformDxe')
24 files changed, 7434 insertions, 0 deletions
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h b/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h new file mode 100644 index 0000000000..47a2d1a293 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h @@ -0,0 +1,252 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+--*/
+
+UINT32 mAzaliaVerbTableData12[] = {
+ //
+ // Audio Verb Table - 0x80862805
+ //
+ // Pin Widget 5 - PORT B
+ 0x20471C10,
+ 0x20471D00,
+ 0x20471E56,
+ 0x20471F18,
+
+ // Pin Widget 6 - PORT C
+ 0x20571C20,
+ 0x20571D00,
+ 0x20571E56,
+ 0x20571F18,
+
+ // Pin Widget 7 - PORT D
+ 0x20671C30,
+ 0x20671D00,
+ 0x20671E56,
+ 0x20671F58
+};
+
+
+PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = {
+ {
+ //
+ // VerbTable:
+ // Revision ID = 0xFF, support all steps
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0880
+ //
+ {
+ 0x10EC0880, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000A, // Number of Rear Jacks = 10
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // Revision ID >= 0x03
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x434D4980
+ //
+ {
+ 0x434D4980, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0x00, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x0009, // Number of Rear Jacks = 9
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // Lawndale Azalia Audio Codec Verb Table
+ // Revision ID = 0x00
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x11D41984
+ //
+ {
+ 0x11D41984, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0x04, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x0009, // Number of Rear Jacks = 9
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable:
+ // Revision ID = 0xFF, support all steps
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x11D41986
+ //
+ {
+ 0x11D41986, // Vendor ID/Device ID
+ 0x0001, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000A, // Number of Rear Jacks = 8
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (for Slim River, FFDS3)
+ // Revision ID = 0x00
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0272
+ //
+ {
+ 0x10EC0272, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0x00, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000E, // Number of Rear Jacks
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (for Buffalo Trail)
+ // Revision ID = 0x00
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0269
+ //
+ {
+ 0x10EC0269, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0x00, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000A, // Number of Rear Jacks
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (RealTek ALC888)
+ // Revision ID = 0xFF
+ // Codec Verb Table For Redfort
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0888
+ //
+ {
+ 0x10EC0888, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000B, // Number of Rear Jacks
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (RealTek ALC885)
+ // Revision ID = 0xFF
+ // Codec Verb Table For Redfort
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0885
+ //
+ {
+ 0x10EC0885, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000B, // Number of Rear Jacks
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (IDT 92HD81)
+ // Revision ID = 0xFF
+ // Codec Vendor: 0x111D7605
+ //
+ {
+ 0x111D76d5, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x0008, // Number of Rear Jacks
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (Intel VLV HDMI)
+ // Revision ID = 0xFF
+ // Codec Verb Table For EmeraldLake/LosLunas
+ // Codec Vendor: 0x80862804
+ //
+ {
+ 0x80862882, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x02, // Front panel support (1=yes, 2=no)
+ 0x0003, // Number of Rear Jacks
+ 0x0000 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (RealTek ALC262)
+ // Revision ID = 0xFF, support all steps
+ // Codec Verb Table For AZALIA
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0262
+ //
+ {
+ 0x10EC0262, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xFF, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000B, // Number of Rear Jacks = 11
+ 0x0002 // Number of Front Jacks = 2
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ },
+ {
+ //
+ // VerbTable: (RealTek ALC282)
+ // Revision ID = 0xff
+ // Codec Verb Table For Azalia on SharkBay-WhiteBluff refresh and Haswell ULT FFRD Harris Beach, WTM1, WTM2iCRB
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0282
+ //
+ {
+ 0x10EC0282, // Vendor ID/Device ID
+ 0x0000, // SubSystem ID
+ 0xff, // Revision ID
+ 0x01, // Front panel support (1=yes, 2=no)
+ 0x000C, // Number of Rear Jacks, 0x0010 for Harris Beach, 0x000B for WTM1 & WTM2iCRB
+ 0x0002 // Number of Front Jacks
+ },
+ 0 // Pointer to verb table data, need to be inited in the code.
+ }
+};
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c b/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c new file mode 100644 index 0000000000..5b6139b2d6 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c @@ -0,0 +1,228 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ BoardId.c
+
+Abstract:
+
+ Initialization for the board ID.
+
+ This code should be common across a chipset family of products.
+
+
+
+--*/
+
+#include "PchRegs.h"
+#include "PlatformDxe.h"
+#include <Guid/IdccData.h>
+#include <Guid/EfiVpdData.h>
+#include <Protocol/DataHub.h>
+
+
+extern EFI_GUID mPlatformDriverGuid;
+
+//
+// Global module data
+//
+UINT32 mBoardId;
+UINT8 mBoardIdIndex;
+EFI_BOARD_FEATURES mBoardFeatures;
+UINT16 mSubsystemDeviceId;
+UINT16 mSubsystemAudioDeviceId;
+CHAR8 BoardAaNumber[7];
+BOOLEAN mFoundAANum;
+
+/**
+
+ Write the boardid variable if it does not already exist.
+
+**/
+VOID
+InitializeBoardId (
+ )
+{
+
+ UINT32 BoardIdBufferSize;
+ EFI_IDCC_BOARD_FORM_FACTOR IdccBoardFormFactor;
+ EFI_DATA_HUB_PROTOCOL *DataHub;
+ EFI_STATUS Status;
+ DMI_DATA DmiDataVariable;
+ UINTN Size;
+#if defined(DUPLICATE_AA_NO_BASE_ADDR)
+ CHAR8 DuplicateAaNoAscii[sizeof(DmiDataVariable.BaseBoardVersion)];
+ UINTN iter;
+#endif
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0
+ UINT8 Data8;
+#endif
+
+ //
+ // Update data from the updatable DMI data area
+ //
+ Size = sizeof (DMI_DATA);
+ SetMem(&DmiDataVariable, Size, 0xFF);
+ Status = gRT->GetVariable (
+ DMI_DATA_NAME,
+ &gDmiDataGuid,
+ NULL,
+ &Size,
+ &DmiDataVariable
+ );
+
+#if defined(DUPLICATE_AA_NO_BASE_ADDR)
+ //
+ // Get AA# from flash descriptor region
+ //
+ EfiSetMem(DuplicateAaNoAscii, sizeof(DuplicateAaNoAscii), 0xFF);
+ FlashRead((UINT8 *)(UINTN)DUPLICATE_AA_NO_BASE_ADDR,
+ (UINT8 *)DuplicateAaNoAscii,
+ sizeof(DuplicateAaNoAscii));
+
+ //
+ // Validate AA# read from VPD
+ //
+ for (iter = 0; iter < sizeof(DuplicateAaNoAscii); iter++) {
+ if ((DuplicateAaNoAscii[iter] != 0xFF) &&
+ (DuplicateAaNoAscii[iter] != DmiDataVariable.BaseBoardVersion[iter])) {
+ DmiDataVariable.BaseBoardVersion[iter] = DuplicateAaNoAscii[iter];
+ }
+ }
+
+ Status = EFI_SUCCESS;
+#endif
+
+ mFoundAANum = FALSE;
+
+ //
+ // No variable...no copy
+ //
+ if (EFI_ERROR (Status)) {
+ mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the first entry
+ } else {
+ //
+ // This is the correct method of checking for AA#.
+ //
+ CopyMem(&BoardAaNumber, ((((UINT8*)&DmiDataVariable.BaseBoardVersion)+2)), 6);
+ BoardAaNumber[6] = 0;
+ for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {
+ if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber, BoardAaNumber, 6) == 0) {
+ mFoundAANum = TRUE;
+ break;
+ }
+ }
+
+ if(!mFoundAANum) {
+ //
+ // Add check for AA#'s that is programmed without the AA as leading chars.
+ //
+ CopyMem(&BoardAaNumber, (((UINT8*)&DmiDataVariable.BaseBoardVersion)), 6);
+ BoardAaNumber[6] = 0;
+ for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {
+ if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber, BoardAaNumber, 6) == 0) {
+ mFoundAANum = TRUE;
+ break;
+ }
+ }
+ }
+ }
+
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0
+ //
+ // If we can't find the BoardAA# in the table, find BoardId
+ //
+ if (mFoundAANum != TRUE) {
+ //
+ // BoardID BIT Location
+ // 0 GPIO33 (ICH)
+ // 1 GPIO34 (ICH)
+ //
+ Data8 = IoRead8(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2);
+
+ //
+ // BoardId[0]
+ //
+ mBoardId = (UINT32)((Data8 >> 1) & BIT0);
+ //
+ // BoardId[1]
+ //
+ mBoardId |= (UINT32)((Data8 >> 1) & BIT1);
+
+ for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {
+ if (mBoardIdDecodeTable[mBoardIdIndex].BoardId == mBoardId) {
+ break;
+ }
+ }
+#endif
+ if (mBoardIdIndex == mBoardIdDecodeTableSize) {
+ mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the first entry
+ }
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0
+ }
+#endif
+
+ mBoardFeatures = mBoardIdDecodeTable[mBoardIdIndex].Features;
+ mSubsystemDeviceId = mBoardIdDecodeTable[mBoardIdIndex].SubsystemDeviceId;
+ mSubsystemAudioDeviceId = mBoardIdDecodeTable[mBoardIdIndex].AudioSubsystemDeviceId;
+
+ //
+ // Set the BoardFeatures variable
+ //
+ BoardIdBufferSize = sizeof (mBoardFeatures);
+ gRT->SetVariable (
+ BOARD_FEATURES_NAME,
+ &gEfiBoardFeaturesGuid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ BoardIdBufferSize,
+ &mBoardFeatures
+ );
+
+ //
+ // Get the Data Hub protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiDataHubProtocolGuid,
+ NULL,
+ (VOID **) &DataHub
+ );
+ if (!(EFI_ERROR(Status))) {
+ //
+ // Fill out data
+ //
+ IdccBoardFormFactor.IdccHeader.Type = EFI_IDCC_BOARD_FORM_FACTOR_TYPE;
+ IdccBoardFormFactor.IdccHeader.RecordLength = sizeof(EFI_IDCC_BOARD_FORM_FACTOR);
+ if ((mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_ATX) || (mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX)) {
+ IdccBoardFormFactor.BoardFormFactor = ATX_FORM_FACTOR; // ATX
+ } else {
+ IdccBoardFormFactor.BoardFormFactor = BTX_FORM_FACTOR; // BTX
+ }
+
+ //
+ // Publish the Board Form Factor value for IDCC
+ //
+ Status = DataHub->LogData (
+ DataHub,
+ &gIdccDataHubGuid,
+ &mPlatformDriverGuid,
+ EFI_DATA_RECORD_CLASS_DATA,
+ &IdccBoardFormFactor,
+ sizeof(EFI_IDCC_BOARD_FORM_FACTOR)
+ );
+ }
+}
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c new file mode 100644 index 0000000000..cf9b904b2c --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c @@ -0,0 +1,134 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ BoardIdDecode.c
+
+Abstract:
+
+--*/
+
+#include "PchRegs.h"
+#include "PlatformDxe.h"
+#include "Platform.h"
+
+
+//
+// Define macros to build data structure signatures from characters.
+//
+#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
+#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
+#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \
+ (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G, H)) << 32))
+
+BOARD_ID_DECODE mBoardIdDecodeTable[] = {
+ //
+ // Board ID, Board Features bitmap, Subsystem Device ID
+ // This is a dummy entry that has to exist. Do not delete, just make a generic entry that fit for product.
+ //
+ {
+ MW_ITX_MPCIE_LVDS_LOEM_AA,
+ MW_ITX_MPCIE_LVDS_LOEM_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_LVDS |
+ B_BOARD_FEATURES_VERB_TABLE1,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID,
+ 0xD625,
+ EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
+ },
+
+ {
+ MW_ITX_MPCIE_LVDS_CHANNEL_AA,
+ MW_ITX_MPCIE_LVDS_CHANNEL_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_LVDS |
+ B_BOARD_FEATURES_VERB_TABLE1,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID,
+ 0xD625,
+ EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
+ },
+
+ {
+ MW_ITX_MPCIE_CHANNEL_AA,
+ MW_ITX_MPCIE_CHANNEL_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_VERB_TABLE1,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID,
+ 0xD625,
+ EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')
+ },
+
+ {
+ KT_ITX_MPCIE_LVDS_LOEM_AA,
+ KT_ITX_MPCIE_LVDS_LOEM_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_LVDS |
+ B_BOARD_FEATURES_VERB_TABLE2,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
+ 0xD626,
+ EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
+ },
+
+ {
+ KT_ITX_CHANNEL_AA,
+ KT_ITX_CHANNEL_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_NO_MINIPCIE |
+ B_BOARD_FEATURES_VERB_TABLE2,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
+ 0xD626,
+ EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
+ },
+
+ {
+ KT_ITX_LOEM_AA,
+ KT_ITX_LOEM_ID,
+ B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_SIO_COM2 |
+ B_BOARD_FEATURES_2_C0_MEMORY_SLOT |
+ V_BOARD_FEATURES_SLEEP_S3 |
+ B_BOARD_FEATURES_PS2WAKEFROMS5 |
+ B_BOARD_FEATURES_NO_MINIPCIE |
+ B_BOARD_FEATURES_VERB_TABLE2,
+ V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,
+ 0xD626,
+ EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')
+ }
+};
+
+UINTN mBoardIdDecodeTableSize = sizeof (mBoardIdDecodeTable) /
+ sizeof (mBoardIdDecodeTable[0]);
+
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h new file mode 100644 index 0000000000..8240cd87cc --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h @@ -0,0 +1,66 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ BoardIdDecode.h
+
+Abstract:
+
+ Header file for Platform Initialization Driver.
+
+Revision History
+
+++*/
+
+//
+// Board AA# and Board ID
+//
+#define DEFAULT_BOARD_AA "FFFFFF"
+
+//
+// Mount Washington (LVDS) LOEM
+//
+#define MW_ITX_MPCIE_LVDS_LOEM_AA "E93081"
+#define MW_ITX_MPCIE_LVDS_LOEM_ID 3
+
+//
+// Mount Washington (LVDS) Channel
+//
+#define MW_ITX_MPCIE_LVDS_CHANNEL_AA "E93080"
+#define MW_ITX_MPCIE_LVDS_CHANNEL_ID 3
+
+//
+// Mount Washington Channel
+//
+#define MW_ITX_MPCIE_CHANNEL_AA "E93082"
+#define MW_ITX_MPCIE_CHANNEL_ID 1
+
+//
+// Kinston (mPCIe + LVDS) LOEM
+//
+#define KT_ITX_MPCIE_LVDS_LOEM_AA "E93085"
+#define KT_ITX_MPCIE_LVDS_LOEM_ID 2
+
+//
+// Kinston (LVDS) Channel
+//
+#define KT_ITX_CHANNEL_AA "E93083"
+#define KT_ITX_CHANNEL_ID 0
+
+//
+// Kinston LOEM
+//
+#define KT_ITX_LOEM_AA "E93084"
+#define KT_ITX_LOEM_ID 0
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c b/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c new file mode 100644 index 0000000000..cc6ca3c44a --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c @@ -0,0 +1,207 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ ClockControl.c
+
+Abstract:
+
+ Sets platform/SKU specific clock routing information.
+
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include <Protocol/CK505ClockPlatformInfo.h>
+
+//
+// Default clock routing informtion (All On)
+//
+EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};
+
+//
+// Clock Settings
+//
+// Static clock table.
+// This should be used to define any clock settings that are static
+// (Always On or Always Off). Dynamic clocks should be set to enabled
+// in this table.
+//
+EFI_STATIC_SIGNALS mAtxStaticClocks[] = {
+ {SrcClk8, Enabled, All},
+ {SrcClk7, Enabled, All},
+ {SrcClk6, Enabled, All},
+ {SrcClk5, Enabled, All},
+ {SrcClk4, Enabled, All},
+ {SrcClk3, Enabled, All},
+ {SrcClk2, Enabled, All},
+ {SrcClk1, Enabled, All},
+ {SrcClk0, Enabled, All},
+ {Ref0, Enabled, All},
+ {Dot96, Enabled, All},
+ {Usb48, Enabled, All},
+ {PciClkF5, Enabled, All},
+ {PciClk0, Enabled, All},
+ {PciClk2, Enabled, All},
+ {PciClk3, Enabled, All},
+ {PciClk4, Disabled, All},
+ {Cr_B, EnabledWithSwitch, All},
+};
+
+//
+// ClockSxInfo Table
+// This is a list of clocks that need to be set to a known state when the
+// system enters S4 or S5.
+//
+EFI_STATIC_SIGNALS mAtxSxClocks[] = {
+ {SaveClockConfiguration, Disabled, All}
+};
+
+//
+// ATX settings structure
+//
+EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {
+ mAtxStaticClocks,
+ sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),
+ mAtxSxClocks,
+ sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])
+};
+
+#if defined( RVP_SUPPORT ) && RVP_SUPPORT
+//
+// RVP Clock Settings
+//
+// Static clock table.
+// This should be used to define any clock settings that are static
+// (Always On or Always Off). Dynamic clocks should be set to enabled
+// in this table.
+//
+//UPSD_TBD Check with Jan if any porting required.
+//
+EFI_STATIC_SIGNALS mRvpStaticClocks[] = {
+ {SrcClk11, Enabled, All}, // Not used/not present but leave coding enabled
+ {SrcClk10, Enabled, All}, // Not used/not present but leave coding enabled
+ {SrcClk9, Enabled, All}, // Not used/not present but leave coding enabled
+ {SrcClk8, Enabled, All}, // ICHSATAII
+ {SrcClk7, Enabled, All}, // DPL_REFSSCLKIN
+ {SrcClk6, Enabled, All}, // 100M_MCH
+ {SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:
+ // 0: turn on; 1: turn off
+ {SrcClk4, Enabled, All}, // ICHSATA
+ {SrcClk3, Enabled, All}, // 100M_ICH
+ {SrcClk2, Enabled, All}, // 100M_LAN
+ {SrcClk1, Enabled, All}, // 25M_LAN
+ {SrcClk0, Enabled, All}, // 96M_DREF
+ {Ref0, Enabled, All},
+ {Dot96, Enabled, All},
+ {Usb48, Enabled, All},
+ {PciClkF5, Enabled, All}, // 33M_ICH
+ {PciClk0, Enabled, All}, // 33M_RISER
+ {PciClk1, Enabled, All}, // 33M_RISER
+ {PciClk2, Enabled, All}, // VDD_Clock
+ {PciClk3, Enabled, All}, // 33M_S1
+ {PciClk4, Enabled, All}, // 33M_PA
+};
+
+//
+// Dynamic clock table
+// This is used to determine if a clock should be left on or turned off based
+// on the presence of a device. The bridge information is used so the bus
+// number for the device to be detected can be found.
+//
+
+//
+// ClockSxInfo Table
+// This is a list of clocks that need to be set to a known state when the
+// system enters S4 or S5.
+//
+EFI_STATIC_SIGNALS mRvpSxClocks[] = {
+ {SaveClockConfiguration, Disabled, All}
+};
+
+//
+// RVP settings structure
+//
+EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {
+ mRvpStaticClocks,
+ sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),
+ 0, // No clocks will be turned off mRvpDynamicClocks,
+ 0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),
+ mRvpSxClocks,
+ sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])
+};
+#endif
+
+VOID
+InitializeClockRouting(
+ )
+{
+ EFI_STATUS Status;
+ UINTN BoardIdVarSize;
+ EFI_BOARD_FEATURES BoardIdVar;
+ EFI_CLOCK_PLATFORM_INFO *ClockPolicy;
+ EFI_HANDLE Handle;
+
+ ClockPolicy = &mDefClockPolicy;
+
+ //
+ // Do modifications based on board type
+ //
+ BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);
+ Status = gRT->GetVariable (
+ BOARD_FEATURES_NAME,
+ &gEfiBoardFeaturesGuid,
+ NULL,
+ &BoardIdVarSize,
+ &BoardIdVar
+ );
+ if (!EFI_ERROR (Status)) {
+
+#if defined( RVP_SUPPORT ) && RVP_SUPPORT
+ if (BoardIdVar & B_BOARD_FEATURES_RVP) {
+ ClockPolicy = &mRvpClockSettings;
+ }
+#else
+
+ //
+ // Isolate board type information
+ //
+ BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |
+ B_BOARD_FEATURES_FORM_FACTOR_BTX |
+ B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |
+ B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);
+
+ if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||
+ BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {
+ ClockPolicy = &mAtxClockSettings;
+ }
+
+#endif
+
+ }
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiCk505ClockPlatformInfoGuid,
+ EFI_NATIVE_INTERFACE,
+ ClockPolicy
+ );
+ ASSERT_EFI_ERROR(Status);
+
+}
+
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h b/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h new file mode 100644 index 0000000000..08bdf07e60 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h @@ -0,0 +1,697 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ Configuration.h
+
+Abstract:
+
+ Driver configuration include file
+
+
+--*/
+
+#ifndef _CONFIGURATION_H
+#define _CONFIGURATION_H
+
+#define EFI_NON_DEVICE_CLASS 0x00
+#define EFI_DISK_DEVICE_CLASS 0x01
+#define EFI_VIDEO_DEVICE_CLASS 0x02
+#define EFI_NETWORK_DEVICE_CLASS 0x04
+#define EFI_INPUT_DEVICE_CLASS 0x08
+#define EFI_ON_BOARD_DEVICE_CLASS 0x10
+#define EFI_OTHER_DEVICE_CLASS 0x20
+
+//
+// Processor labels
+//
+#define PROCESSOR_HT_MODE 0x0100
+#define PROCESSOR_FSB_MULTIPLIER 0x0101
+#define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211
+
+//
+// Memory labels
+//
+#define MEMORY_SLOT1_SPEED 0x0200
+#define MEMORY_SLOT2_SPEED 0x0201
+#define MEMORY_SLOT3_SPEED 0x0202
+#define MEMORY_SLOT4_SPEED 0x0203
+#define END_MEMORY_SLOT_SPEED 0x020F
+#define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210
+#define UCLK_RATIO_CONTROL 0x0212
+
+//
+// Language label
+//
+#define FRONT_PAGE_ITEM_LANGUAGE 0x300
+
+//
+// Boot Labels
+//
+#define BOOT_DEVICE_PRIORITY_BEGIN 0x0400
+#define BOOT_DEVICE_PRIORITY_END 0x0401
+#define BOOT_OPTICAL_DEVICE_BEGIN 0x0410
+#define BOOT_OPTICAL_DEVICE_END 0x0411
+#define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420
+#define BOOT_REMOVABLE_DEVICE_END 0x0421
+#define BOOT_PXE_DEVICE_BEGIN 0x0430
+#define BOOT_PXE_DEVICE_END 0x0431
+#define BOOT_MENU_TYPE_BEGIN 0x0440
+#define BOOT_MENU_TYPE_END 0x0441
+#define BOOT_USB_DEVICE_BEGIN 0x0450
+#define BOOT_USB_DEVICE_END 0x0451
+#define BOOT_USB_FIRST_BEGIN 0x0460
+#define BOOT_USB_FIRST_END 0x0461
+#define BOOT_UEFI_BEGIN 0x0470
+#define BOOT_UEFI_END 0x0471
+#define BOOT_USB_UNAVAILABLE_BEGIN 0x0480
+#define BOOT_USB_UNAVAILABLE_END 0x0481
+#define BOOT_CD_UNAVAILABLE_BEGIN 0x0490
+#define BOOT_CD_UNAVAILABLE_END 0x0491
+#define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0
+#define BOOT_FDD_UNAVAILABLE_END 0x04A1
+#define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0
+#define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1
+#define BOOT_USB_OPT_LABEL_BEGIN 0x04C0
+#define BOOT_USB_OPT_LABEL_END 0x04C1
+
+#define VAR_EQ_ADMIN_NAME 0x0041 // A
+#define VAR_EQ_ADMIN_DECIMAL_NAME L"65"
+#define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B
+#define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66"
+#define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C
+#define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"
+#define VAR_EQ_CPU_EE_NAME 0x0045 // E
+#define VAR_EQ_CPU_EE_DECIMAL_NAME L"69"
+#define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F
+#define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"
+#define VAR_EQ_HT_MODE_NAME 0x0048 // H
+#define VAR_EQ_HT_MODE_DECIMAL_NAME L"72"
+#define VAR_EQ_AHCI_MODE_NAME 0x0049 // I
+#define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73"
+#define VAR_EQ_CPU_LOCK_NAME 0x004C // L
+#define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76"
+#define VAR_EQ_NX_MODE_NAME 0x004E // N
+#define VAR_EQ_NX_MODE_DECIMAL_NAME L"78"
+#define VAR_EQ_RAID_MODE_NAME 0x0052 // R
+#define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82"
+#define VAR_EQ_1394_MODE_NAME 0x0054 // T
+#define VAR_EQ_1394_MODE_DECIMAL_NAME L"84"
+#define VAR_EQ_USER_NAME 0x0055 // U
+#define VAR_EQ_USER_DECIMAL_NAME L"85"
+#define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V
+#define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86"
+#define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W
+#define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"
+#define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X
+#define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"
+#define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y
+#define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"
+#define VAR_EQ_UNCON_CPU_NAME 0x005B // ??
+#define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91"
+#define VAR_EQ_VAR_HIDE_NAME 0x005C // ??
+#define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92"
+#define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ??
+#define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"
+#define VAR_EQ_TPM_MODE_NAME 0x005E // ^
+#define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94"
+#define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ??
+#define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"
+#define VAR_EQ_ROEM_SKU_NAME 0x0060 // ??
+#define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96"
+#define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ??
+#define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"
+#define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ??
+#define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ??
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"
+#define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ??
+#define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"
+#define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ??
+#define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"
+#define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f
+#define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"
+#define VAR_EQ_2_MEMORY_NAME 0x0067 // ??
+#define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103"
+#define VAR_EQ_2_SATA_NAME 0x0068 // ??
+#define VAR_EQ_2_SATA_DECIMAL_NAME L"104"
+#define VAR_EQ_NEC_SKU_NAME 0x0069 // ??
+#define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105"
+#define VAR_EQ_AMT_MODE_NAME 0x006A // ??
+#define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106"
+#define VAR_EQ_LCLX_SKU_NAME 0x006B // ??
+#define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107"
+#define VAR_EQ_VT_NAME 0x006C
+#define VAR_EQ_VT_DECIMAL_NAME L"108"
+#define VAR_EQ_LT_NAME 0x006D
+#define VAR_EQ_LT_DECIMAL_NAME L"109"
+#define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ??
+#define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"
+#define VAR_EQ_HPET_NAME 0x006F
+#define VAR_EQ_HPET_DECIMAL_NAME L"111"
+#define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ??
+#define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112"
+#define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ??
+#define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113"
+#define VAR_EQ_CPU_CMP_NAME 0x0072
+#define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114"
+#define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ??
+#define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115"
+#define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ??
+#define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"
+#define VAR_EQ_AFSC_SETUP_NAME 0x0075
+#define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117"
+#define VAR_EQ_MINICARD_MODE_NAME 0x0076 //
+#define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118"
+#define VAR_EQ_VIDEO_IGD_NAME 0x0077 //
+#define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119"
+#define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 //
+#define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120"
+#define VAR_EQ_LEGACY_FREE_NAME 0x0079 //
+#define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121"
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122"
+#define VAR_EQ_CPU_FSB_NAME 0x007B //
+#define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123"
+#define VAR_EQ_SATA0_DEVICE_NAME 0x007C //
+#define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124"
+#define VAR_EQ_SATA1_DEVICE_NAME 0x007D //
+#define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125"
+#define VAR_EQ_SATA2_DEVICE_NAME 0x007E //
+#define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126"
+#define VAR_EQ_SATA3_DEVICE_NAME 0x007F //
+#define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127"
+#define VAR_EQ_SATA4_DEVICE_NAME 0x0080 //
+#define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128"
+#define VAR_EQ_SATA5_DEVICE_NAME 0x0081 //
+#define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129"
+#define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled
+#define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130"
+#define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083
+#define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"
+#define VAR_EQ_USB_2_NAME 0x0084 //
+#define VAR_EQ_USB_2_DECIMAL_NAME L"132"
+#define VAR_EQ_RVP_NAME 0x0085 //
+#define VAR_EQ_RVP_DECIMAL_NAME L"133"
+#define VAR_EQ_ECIR_NAME 0x0086
+#define VAR_EQ_ECIR_DECIMAL_NAME L"134"
+#define VAR_EQ_WAKONS5KB_NAME 0x0087
+#define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135"
+#define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088
+#define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136"
+#define VAR_EQ_FINGERPRINT_NAME 0x0089
+#define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137"
+#define VAR_EQ_BLUETOOTH_NAME 0x008A
+#define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138"
+#define VAR_EQ_WLAN_NAME 0x008B
+#define VAR_EQ_WLAN_DECIMAL_NAME L"139"
+#define VAR_EQ_1_PATA_NAME 0x008C
+#define VAR_EQ_1_PATA_DECIMAL_NAME L"140"
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141"
+#define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E
+#define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142"
+#define VAR_EQ_XE_MODE_CAP_NAME 0x008F
+#define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143"
+#define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090
+#define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"
+#define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091
+#define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"
+#define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ??
+#define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146"
+#define VAR_EQ_LVDS_NAME 0x0093
+#define VAR_EQ_LVDS_DECIMAL_NAME L"147"
+#define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094
+#define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148"
+#define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095
+#define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149"
+#define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096
+#define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150"
+#define VAR_EQ_PS2_HIDE_NAME 0x0097 // ??
+#define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"
+#define VAR_EQ_VIDEO_SLOT_NAME 0x0098
+#define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152"
+#define VAR_EQ_HDMI_SLOT_NAME 0x0099
+#define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153"
+#define VAR_EQ_SERIAL2_HIDE_NAME 0x009a
+#define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"
+
+
+#define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e
+#define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"
+
+
+#define VAR_EQ_MSATA_HIDE_NAME 0x009f
+#define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"
+
+
+#define VAR_EQ_PCI_SLOT1_NAME 0x00a0
+#define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"
+#define VAR_EQ_PCI_SLOT2_NAME 0x00a1
+#define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"
+
+//
+// Generic Form Ids
+//
+#define ROOT_FORM_ID 1
+
+//
+// Advance Page. Do not have to be sequential but have to be unique
+//
+#define CONFIGURATION_ROOT_FORM_ID 2
+#define BOOT_CONFIGURATION_ID 3
+#define ONBOARDDEVICE_CONFIGURATION_ID 4
+#define DRIVE_CONFIGURATION_ID 5
+#define FLOPPY_CONFIGURATION_ID 6
+#define EVENT_LOG_CONFIGURATION_ID 7
+#define VIDEO_CONFIGURATION_ID 8
+#define USB_CONFIGURATION_ID 9
+#define HARDWARE_MONITOR_CONFIGURATION_ID 10
+#define VIEW_EVENT_LOG_CONFIGURATION_ID 11
+#define MEMORY_OVERRIDE_ID 12
+#define CHIPSET_CONFIGURATION_ID 13
+#define BURN_IN_MODE_ID 14
+#define PCI_EXPRESS_ID 15
+#define MANAGEMENT_CONFIGURATION_ID 16
+#define CPU_CONFIGURATION_ID 17
+#define PCI_CONFIGURATION_ID 18
+#define SECURITY_CONFIGURATION_ID 19
+#define ZIP_CONFIGURATION_ID 20
+#define AFSC_FAN_CONTROL_ID 21
+#define VFR_FORMID_CSI 22
+#define VFR_FORMID_MEMORY 23
+#define VFR_FORMID_IOH 24
+#define VFR_FORMID_CPU_CSI 25
+#define VFR_FORMID_IOH_CONFIG 26
+#define VFR_FORMID_VTD 27
+#define VFR_FORMID_PCIE_P0 28
+#define VFR_FORMID_PCIE_P1 29
+#define VFR_FORMID_PCIE_P2 30
+#define VFR_FORMID_PCIE_P3 31
+#define VFR_FORMID_PCIE_P4 32
+#define VFR_FORMID_PCIE_P5 33
+#define VFR_FORMID_PCIE_P6 34
+#define VFR_FORMID_PCIE_P7 35
+#define VFR_FORMID_PCIE_P8 36
+#define VFR_FORMID_PCIE_P9 37
+#define VFR_FORMID_PCIE_P10 38
+#define VFR_FID_SKT0 39
+#define VFR_FID_IOH0 40
+#define VFR_FID_IOH_DEV_HIDE 41
+#define PROCESSOR_OVERRIDES_FORM_ID 42
+#define BUS_OVERRIDES_FORM_ID 43
+#define REF_OVERRIDES_FORM_ID 44
+#define MEMORY_INFORMATION_ID 45
+#define LVDS_WARNING_ID 46
+#define LVDS_CONFIGURATION_ID 47
+#define PCI_SLOT_CONFIGURATION_ID 48
+#define HECETA_CONFIGURATION_ID 49
+#define LVDS_EXPERT_CONFIGURATION_ID 50
+#define PCI_SLOT_7_ID 51
+#define PCI_SLOT_6_ID 52
+#define PCI_SLOT_5_ID 53
+#define PCI_SLOT_4_ID 54
+#define PCI_SLOT_3_ID 55
+#define PCI_SLOT_2_ID 56
+#define PCI_SLOT_1_ID 57
+#define BOOT_DISPLAY_ID 58
+#define CPU_PWR_CONFIGURATION_ID 59
+
+#define FSC_CONFIGURATION_ID 60
+#define FSC_CPU_TEMPERATURE_FORM_ID 61
+#define FSC_VTT_VOLTAGE_FORM_ID 62
+#define FSC_FEATURES_CONTROL_ID 63
+#define FSC_FAN_CONFIGURATION_ID 64
+#define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65
+#define FSC_FRONT_FAN_CONFIGURATION_ID 66
+#define FSC_REAR_FAN_CONFIGURATION_ID 67
+#define FSC_AUX_FAN_CONFIGURATION_ID 68
+#define FSC_12_VOLTAGE_FORM_ID 69
+#define FSC_5_VOLTAGE_FORM_ID 70
+#define FSC_3P3_VOLTAGE_FORM_ID 71
+#define FSC_2P5_VOLTAGE_FORM_ID 72
+#define FSC_VCC_VOLTAGE_FORM_ID 73
+#define FSC_PCH_TEMPERATURE_FORM_ID 74
+#define FSC_MEM_TEMPERATURE_FORM_ID 75
+#define FSC_VR_TEMPERATURE_FORM_ID 76
+#define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77
+#define FSC_5BACKUP_VOLTAGE_FORM_ID 78
+#define ROOT_MAIN_FORM_ID 79
+#define ROOT_BOOT_FORM_ID 80
+#define ROOT_MAINTENANCE_ID 81
+#define ROOT_POWER_FORM_ID 82
+#define ROOT_SECURITY_FORM_ID 83
+#define ROOT_PERFORMANCE_FORM_ID 84
+#define ROOT_SYSTEM_SETUP_FORM_ID 85
+
+#define ADDITIONAL_SYSTEM_INFO_FORM_ID 86
+
+#define THERMAL_CONFIG_FORM_ID 87
+
+#define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A
+#define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B
+#define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C
+#define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D
+#define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E
+#define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F
+#define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010
+#define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011
+
+//
+// Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
+//
+#define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000
+#define ADVANCE_VIDEO_CALLBACK_KEY 0x2001
+#define CONFIGURATION_FSC_CALLBACK_KEY 0x2002
+#define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003
+#define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004
+#define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005
+#define ADVANCE_LVDS_CALLBACK_KEY 0x2010
+
+//
+// Main Callback Keys. Do not have to be sequential but have to be unique
+//
+#define MAIN_LANGUAGE_CALLBACK_KEY 0x3000
+
+//
+// Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique
+//
+#define POWER_HARDWARE_CALLBACK_KEY 0x4000
+
+//
+// Performance Callback Keys. Do not have to be sequential but have to be unique
+//
+#define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000
+#define PERFORMANCE_CALLBACK_KEY 0x5001
+#define BUS_OVERRIDES_CALLBACK_KEY 0x5002
+#define MEMORY_CFG_CALLBACK_KEY 0x5003
+#define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004
+#define MEMORY_RATIO_CALLBACK_KEY 0x5005
+#define MEMORY_MODE_CALLBACK_KEY 0x5006
+
+//
+// Security Callback Keys. Do not have to be sequential but have to be unique
+//
+#define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000
+#define SECURITY_USER_CALLBACK_KEY 0x1001
+#define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002
+#define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004
+#define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008
+#define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010
+#define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020
+#define SECURITY_USER_HDD_CALLBACK_KEY 0x1040
+
+//
+// Boot Callback Keys. Do not have to be sequential but have to be unique
+//
+#define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004
+#define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006
+
+//
+// IDCC/Setup FSB Frequency Override Range
+//
+#define EFI_IDCC_FSB_MIN 133
+#define EFI_IDCC_FSB_MAX 240
+#define EFI_IDCC_FSB_STEP 1
+
+//
+// Reference voltage
+//
+#define EFI_REF_DAC_MIN 0
+#define EFI_REF_DAC_MAX 255
+#define EFI_GTLREF_DEF 170
+#define EFI_DDRREF_DEF 128
+#define EFI_DIMMREF_DEF 128
+
+//
+// Setup FSB Frequency Override Range
+//
+#define EFI_FSB_MIN 133
+#define EFI_FSB_MAX 240
+#define EFI_FSB_STEP 1
+#define EFI_FSB_AUTOMATIC 0
+#define EFI_FSB_MANUAL 1
+#define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1
+#define FSB_FREQ_ENTRY_TYPE UINT16_TYPE
+
+//
+// Setup processor multiplier range
+//
+#define EFI_PROC_MULT_MIN 5
+#define EFI_PROC_MULT_MAX 40
+#define EFI_PROC_MULT_STEP 1
+#define EFI_PROC_AUTOMATIC 0
+#define EFI_PROC_MANUAL 1
+#define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1
+#define PROC_MULT_ENTRY_TYPE UINT8_TYPE
+
+//
+// PCI Express Definitions
+//
+#define EFI_PCIE_FREQ_DEF 0x0
+
+#define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE
+#define PCIE_FREQ_ENTRY_7 0x7
+#define PCIE_FREQ_ENTRY_6 0x6
+#define PCIE_FREQ_ENTRY_5 0x5
+#define PCIE_FREQ_ENTRY_4 0x4
+#define PCIE_FREQ_ENTRY_3 0x3
+#define PCIE_FREQ_ENTRY_2 0x2
+#define PCIE_FREQ_ENTRY_1 0x1
+#define PCIE_FREQ_ENTRY_0 0x0
+
+#define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8
+#define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \
+ PCIE_FREQ_ENTRY_1, \
+ PCIE_FREQ_ENTRY_2, \
+ PCIE_FREQ_ENTRY_3, \
+ PCIE_FREQ_ENTRY_4, \
+ PCIE_FREQ_ENTRY_5, \
+ PCIE_FREQ_ENTRY_6, \
+ PCIE_FREQ_ENTRY_7 }
+
+
+#define PCIE_FREQ_PRECISION 2
+#define PCIE_FREQ_VALUE_7 10924
+#define PCIE_FREQ_VALUE_6 10792
+#define PCIE_FREQ_VALUE_5 10660
+#define PCIE_FREQ_VALUE_4 10528
+#define PCIE_FREQ_VALUE_3 10396
+#define PCIE_FREQ_VALUE_2 10264
+#define PCIE_FREQ_VALUE_1 10132
+#define PCIE_FREQ_VALUE_0 10000
+
+#define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \
+ PCIE_FREQ_VALUE_1, \
+ PCIE_FREQ_VALUE_2, \
+ PCIE_FREQ_VALUE_3, \
+ PCIE_FREQ_VALUE_4, \
+ PCIE_FREQ_VALUE_5, \
+ PCIE_FREQ_VALUE_6, \
+ PCIE_FREQ_VALUE_7 }
+
+//
+// Memory Frequency Definitions
+//
+#define MEMORY_REF_FREQ_ENTRY_DEF 0x08
+
+#define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_REF_FREQ_ENTRY_3 0x04
+#define MEMORY_REF_FREQ_ENTRY_2 0x00
+#define MEMORY_REF_FREQ_ENTRY_1 0x02
+#define MEMORY_REF_FREQ_ENTRY_0 0x01
+
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \
+ MEMORY_REF_FREQ_ENTRY_1, \
+ MEMORY_REF_FREQ_ENTRY_2, \
+ MEMORY_REF_FREQ_ENTRY_3 }
+
+#define MEMORY_REF_FREQ_PRECISION 0
+#define MEMORY_REF_FREQ_VALUE_3 333
+#define MEMORY_REF_FREQ_VALUE_2 267
+#define MEMORY_REF_FREQ_VALUE_1 200
+#define MEMORY_REF_FREQ_VALUE_0 133
+
+#define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \
+ MEMORY_REF_FREQ_VALUE_1, \
+ MEMORY_REF_FREQ_VALUE_2, \
+ MEMORY_REF_FREQ_VALUE_3 }
+
+
+//
+// Memory Reference Frequency Definitions
+//
+
+#define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_FREQ_ENTRY_3 0x4
+#define MEMORY_FREQ_ENTRY_2 0x3
+#define MEMORY_FREQ_ENTRY_1 0x2
+#define MEMORY_FREQ_ENTRY_0 0x1
+
+#define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \
+ MEMORY_FREQ_ENTRY_1, \
+ MEMORY_FREQ_ENTRY_2, \
+ MEMORY_FREQ_ENTRY_3 }
+
+
+#define MEMORY_FREQ_MULT_PRECISION 2
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120
+
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150
+
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200
+
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300
+
+#define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_333MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_266MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_200MHZ_VALUE_3 }
+
+#define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_1, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_2, \
+ MEMORY_FREQ_MULT_133MHZ_VALUE_3 }
+
+//
+// CAS Memory Timing Definitions
+//
+
+#define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TCL_ENTRY_3 0x2
+#define MEMORY_TCL_ENTRY_2 0x1
+#define MEMORY_TCL_ENTRY_1 0x0
+#define MEMORY_TCL_ENTRY_0 0x3
+
+#define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \
+ MEMORY_TCL_ENTRY_1, \
+ MEMORY_TCL_ENTRY_2, \
+ MEMORY_TCL_ENTRY_3 }
+
+
+#define MEMORY_TCL_PRECISION 0
+#define MEMORY_TCL_VALUE_3 3
+#define MEMORY_TCL_VALUE_2 4
+#define MEMORY_TCL_VALUE_1 5
+#define MEMORY_TCL_VALUE_0 6
+
+#define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \
+ MEMORY_TCL_VALUE_1, \
+ MEMORY_TCL_VALUE_2, \
+ MEMORY_TCL_VALUE_3 }
+
+
+//
+// TRCD Memory Timing Definitions
+//
+
+#define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TRCD_ENTRY_3 0x0
+#define MEMORY_TRCD_ENTRY_2 0x1
+#define MEMORY_TRCD_ENTRY_1 0x2
+#define MEMORY_TRCD_ENTRY_0 0x3
+
+#define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \
+ MEMORY_TRCD_ENTRY_1, \
+ MEMORY_TRCD_ENTRY_2, \
+ MEMORY_TRCD_ENTRY_3 }
+
+
+#define MEMORY_TRCD_PRECISION 0
+#define MEMORY_TRCD_VALUE_3 2
+#define MEMORY_TRCD_VALUE_2 3
+#define MEMORY_TRCD_VALUE_1 4
+#define MEMORY_TRCD_VALUE_0 5
+
+#define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \
+ MEMORY_TRCD_VALUE_1, \
+ MEMORY_TRCD_VALUE_2, \
+ MEMORY_TRCD_VALUE_3 }
+
+
+//
+// TRP Memory Timing Definitions
+//
+
+#define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE
+#define MEMORY_TRP_ENTRY_3 0x0
+#define MEMORY_TRP_ENTRY_2 0x1
+#define MEMORY_TRP_ENTRY_1 0x2
+#define MEMORY_TRP_ENTRY_0 0x3
+
+#define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4
+#define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \
+ MEMORY_TRP_ENTRY_1, \
+ MEMORY_TRP_ENTRY_2, \
+ MEMORY_TRP_ENTRY_3 }
+
+
+#define MEMORY_TRP_PRECISION 0
+#define MEMORY_TRP_VALUE_3 2
+#define MEMORY_TRP_VALUE_2 3
+#define MEMORY_TRP_VALUE_1 4
+#define MEMORY_TRP_VALUE_0 5
+
+#define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \
+ MEMORY_TRP_VALUE_1, \
+ MEMORY_TRP_VALUE_2, \
+ MEMORY_TRP_VALUE_3 }
+
+
+//
+// TRAS Memory Timing Definitions
+//
+#define MEMORY_TRAS_MIN 4
+#define MEMORY_TRAS_MAX 18
+#define MEMORY_TRAS_STEP 1
+#define MEMORY_TRAS_DEFAULT 13
+#define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1
+#define MEMORY_TRAS_TYPE UINT8_TYPE
+
+//
+// Uncore Multiplier Definitions
+//
+#define UCLK_RATIO_MIN 12
+#define UCLK_RATIO_MAX 30
+#define UCLK_RATIO_DEFAULT 20
+
+#endif // #ifndef _CONFIGURATION_H
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/ExI.c b/Vlv2TbltDevicePkg/PlatformDxe/ExI.c new file mode 100644 index 0000000000..2dad89f606 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/ExI.c @@ -0,0 +1,83 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ ExI.c
+
+Abstract:
+
+ ExI configuration based on setup option
+
+
+--*/
+
+
+#include "PlatformDxe.h"
+
+#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
+
+//
+// Procedure: GetPmcBase
+//
+// Description: This function read content of B:D:F 0:31:0, offset 44h (for
+// PmcBase)
+//
+// Input: None
+//
+// Output: 32 bit PmcBase
+//
+UINT32
+GetPmcBase (
+ VOID
+ )
+{
+ return (PchLpcPciCfg32 (R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR);
+}
+
+/**
+ Configure ExI.
+
+ @param ImageHandle Pointer to the loaded image protocol for this driver
+ @param SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The driver initializes correctly.
+**/
+VOID
+InitExI (
+ )
+{
+ EFI_STATUS Status;
+
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VarSize;
+
+ VarSize = sizeof(SYSTEM_CONFIGURATION);
+
+ Status = gRT->GetVariable(
+ L"Setup",
+ &gEfiNormalSetupGuid,
+ NULL,
+ &VarSize,
+ &SystemConfiguration
+ );
+
+ ASSERT_EFI_ERROR(Status);
+
+ if (SystemConfiguration.ExISupport == 1) {
+ MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32) BIT0+BIT1+BIT2);
+ } else if (SystemConfiguration.ExISupport == 0) {
+ MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2
+ }
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c b/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c new file mode 100644 index 0000000000..753eb54f22 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c @@ -0,0 +1,496 @@ +/** @file + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> + + + This program and the accompanying materials are licensed and made available under + + the terms and conditions of the BSD License that accompanies this distribution. + + The full text of the license may be found at + + http://opensource.org/licenses/bsd-license.php. + + + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + +Module Name: + + + PchPlatformPolicy.c + +Abstract: + + +--*/ + +#include "PlatformDxe.h" +#include <Protocol/PchPlatformPolicy.h> +#include <Protocol/VlvPlatformPolicy.h> +#include <Library/PchPlatformLib.h> + +#include "AzaliaVerbTable.h" +#include "Protocol/GlobalNvsArea.h" +#include "Protocol/DxePchPolicyUpdateProtocol.h" + +#define MOBILE_PLATFORM 1 +#define DESKTOP_PLATFORM 2 + +EFI_GUID gDxePchPolicyUpdateProtocolGuid = DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID; +DXE_PCH_POLICY_UPDATE_PROTOCOL mDxePchPolicyUpdate = { 0 }; + +/** + + Updates the feature policies according to the setup variable. + + @retval VOID + +**/ +VOID +InitPchPlatformPolicy ( + IN EFI_PLATFORM_INFO_HOB *PlatformInfo + ) +{ + DXE_PCH_PLATFORM_POLICY_PROTOCOL *DxePlatformPchPolicy; + EFI_STATUS Status; + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea; + UINT8 PortIndex; + EFI_HANDLE Handle; + PCH_STEPPING SocStepping = PchA0; + BOOLEAN ModifyVariable; + + ModifyVariable = FALSE; + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - Start\n")); + + Status = gBS->LocateProtocol (&gDxePchPlatformPolicyProtocolGuid, NULL, (VOID **) &DxePlatformPchPolicy); + ASSERT_EFI_ERROR (Status); + + // + // Locate the Global NVS Protocol. + // + Status = gBS->LocateProtocol ( + &gEfiGlobalNvsAreaProtocolGuid, + NULL, + (VOID **) &GlobalNvsArea + ); + ASSERT_EFI_ERROR (Status); + + // + // Update system information + // + DxePlatformPchPolicy->Revision = DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12; + + // + // General initialization + // + DxePlatformPchPolicy->BusNumber = 0; + + // + // VLV BIOS Spec Section 3.6 Flash Security Recommendation, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + // We always enable this as a platform policy. + // + DxePlatformPchPolicy->LockDownConfig->BiosInterface = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->LockDownConfig->BiosLock = mSystemConfiguration.SpiRwProtect; + + // + // DeviceEnables + // + DxePlatformPchPolicy->DeviceEnabling->Lan = mSystemConfiguration.Lan; + DxePlatformPchPolicy->DeviceEnabling->Azalia = mSystemConfiguration.PchAzalia; + DxePlatformPchPolicy->DeviceEnabling->Sata = mSystemConfiguration.Sata; + DxePlatformPchPolicy->DeviceEnabling->Smbus = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->DeviceEnabling->LpeEnabled = mSystemConfiguration.Lpe; + + DxePlatformPchPolicy->UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + + DxePlatformPchPolicy->UsbConfig->UsbXhciLpmSupport =mSystemConfiguration.UsbXhciLpmSupport; + + // + // Disable FFRD PR0 USB port2 for power saving since PR0 uses non-POR WWAN (but enable on PR0.3/PR0.5/PR1) + // + if ((PlatformInfo->BoardId == BOARD_ID_BL_FFRD) && (PlatformInfo->BoardRev == PR0)) + if (mSystemConfiguration.PchUsbPort[2] !=0) { + mSystemConfiguration.PchUsbPort[2]=0; + ModifyVariable = TRUE; + } + + + if (ModifyVariable) { + Status = gRT->SetVariable ( + NORMAL_SETUP_NAME, + &gEfiNormalSetupGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof(SYSTEM_CONFIGURATION), + &mSystemConfiguration + ); + } + + SocStepping = PchStepping(); + if (mSystemConfiguration.UsbAutoMode == 1) { // auto mode is enabled + if (PchA0 == SocStepping) { + // + // For A0, EHCI is enabled as default. + // + mSystemConfiguration.PchUsb20 = 1; + mSystemConfiguration.PchUsb30Mode = 0; + mSystemConfiguration.UsbXhciSupport = 0; + DEBUG ((EFI_D_INFO, "EHCI is enabled as default. SOC 0x%x\n", SocStepping)); + } else { + // + // For A1 and later, XHCI is enabled as default. + // + mSystemConfiguration.PchUsb20 = 0; + mSystemConfiguration.PchUsb30Mode = 1; + mSystemConfiguration.UsbXhciSupport = 1; + DEBUG ((EFI_D_INFO, "XHCI is enabled as default. SOC 0x%x\n", SocStepping)); + } + // + //overwrite the setting + // + Status = gRT->SetVariable( + NORMAL_SETUP_NAME, + &gEfiNormalSetupGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof(SYSTEM_CONFIGURATION), + &mSystemConfiguration + ); + } + + // + // USB Device 29 configuration + // + DxePlatformPchPolicy->UsbConfig->Usb20Settings[0].Enable = mSystemConfiguration.PchUsb20; + DxePlatformPchPolicy->UsbConfig->UsbPerPortCtl = mSystemConfiguration.PchUsbPerPortCtl; + if (mSystemConfiguration.PchUsbPerPortCtl != PCH_DEVICE_DISABLE) { + for (PortIndex = 0; PortIndex < PCH_USB_MAX_PHYSICAL_PORTS; PortIndex++) { + DxePlatformPchPolicy->UsbConfig->PortSettings[PortIndex].Enable = mSystemConfiguration.PchUsbPort[PortIndex]; + } + } + + DxePlatformPchPolicy->UsbConfig->EhciDebug = mSystemConfiguration.PchEhciDebug; + + // + // xHCI (USB 3.0) related settings from setup variable + // + DxePlatformPchPolicy->UsbConfig->Usb30Settings.XhciStreams = mSystemConfiguration.PchUsb30Streams; + + DxePlatformPchPolicy->UsbConfig->Usb30Settings.Mode = mSystemConfiguration.PchUsb30Mode; + + // + // Remove XHCI Pre-Boot Driver setup option selection from end-user view and automate loading of USB 3.0 BIOS driver based on XhciMode selection + // + switch (mSystemConfiguration.PchUsb30Mode) { + case 0: // Disabled + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0; + break; + case 1: // Enabled + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1; + break; + case 2: // Auto + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0; + break; + case 3: // Smart Auto + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1; + break; + default: + DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = mSystemConfiguration.UsbXhciSupport; + break; + } + + + + DxePlatformPchPolicy->UsbConfig->UsbOtgSettings.Enable = mSystemConfiguration.PchUsbOtg; + + DxePlatformPchPolicy->UsbConfig->PortSettings[0].Dock = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->UsbConfig->PortSettings[1].Dock = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->UsbConfig->PortSettings[2].Dock = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->UsbConfig->PortSettings[3].Dock = PCH_DEVICE_DISABLE; + + DxePlatformPchPolicy->UsbConfig->PortSettings[0].Panel = PCH_USB_FRONT_PANEL; + DxePlatformPchPolicy->UsbConfig->PortSettings[1].Panel = PCH_USB_FRONT_PANEL; + DxePlatformPchPolicy->UsbConfig->PortSettings[2].Panel = PCH_USB_BACK_PANEL; + DxePlatformPchPolicy->UsbConfig->PortSettings[3].Panel = PCH_USB_BACK_PANEL; + + // + // + // Enable USB Topology control and program the topology setting for every USB port + // See Platform Design Guide for description of topologies + // + // + // Port 0: ~5.3", Port 1: ~4.9", Port 2: ~4.7", Port 3: ~8.0" + // + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[0] = 0x53; + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[1] = 0x49; + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[2] = 0x47; + DxePlatformPchPolicy->UsbConfig->Usb20PortLength[3] = 0x80; + + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0; + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0; + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[2] = PchUsbOverCurrentPin1; + DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[3] = PchUsbOverCurrentPin1; + + DxePlatformPchPolicy->UsbConfig->Usb30OverCurrentPins[0] = PchUsbOverCurrentPinSkip;//PchUsbOverCurrentPin0; + + DxePlatformPchPolicy->EhciPllCfgEnable = mSystemConfiguration.EhciPllCfgEnable; + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() DxePlatformPchPolicy->EhciPllCfgEnable = 0x%x \n",DxePlatformPchPolicy->EhciPllCfgEnable)); + DxePlatformPchPolicy->PciExpressConfig->PcieDynamicGating = mSystemConfiguration.PcieDynamicGating; + for (PortIndex = 0; PortIndex < PCH_PCIE_MAX_ROOT_PORTS; PortIndex++) { + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Enable = mSystemConfiguration.IchPciExp[PortIndex]; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SlotImplemented = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FunctionNumber = PortIndex; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PhysicalSlotNumber = PortIndex; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Aspm = 4; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PmSci = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].ExtSync = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].HotPlug = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].AdvancedErrorReporting = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].UnsupportedRequestReport = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FatalErrorReport = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].NoFatalErrorReport = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].CorrectableErrorReport = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PmeInterrupt = 0; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnFatalError = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnNonFatalError = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnCorrectableError = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].CompletionTimeout = PchPciECompletionTO_Default; + } + + // + // SATA configuration + // + for (PortIndex = 0; PortIndex < PCH_AHCI_MAX_PORTS; PortIndex++) { + if (mSystemConfiguration.SataType == 0) { + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->LegacyMode = PCH_DEVICE_ENABLE; + } else { + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->LegacyMode = PCH_DEVICE_DISABLE; + } + if(mSystemConfiguration.Sata == 1){ + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + } else { + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_DISABLE; + } + if(0 == PortIndex){ + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug = PCH_DEVICE_DISABLE; + } else if(1 == PortIndex){ + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug = PCH_DEVICE_DISABLE; + } + + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].SpinUp = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].MechSw = PCH_DEVICE_DISABLE; + } + DxePlatformPchPolicy->SataConfig->RaidAlternateId = PCH_DEVICE_DISABLE; + DxePlatformPchPolicy->SataConfig->Raid0 = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->Raid1 = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->Raid10 = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->Raid5 = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->Irrt = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->OromUiBanner = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->HddUnlock = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->LedLocate = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->IrrtOnly = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->SalpSupport = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->SataConfig->TestMode = mSystemConfiguration.SataTestMode; + + // + // AzaliaConfig + // + DxePlatformPchPolicy->AzaliaConfig->Pme = mSystemConfiguration.AzaliaPme; + DxePlatformPchPolicy->AzaliaConfig->HdmiCodec = mSystemConfiguration.HdmiCodec; + DxePlatformPchPolicy->AzaliaConfig->DS = mSystemConfiguration.AzaliaDs; + DxePlatformPchPolicy->AzaliaConfig->AzaliaVCi = mSystemConfiguration.AzaliaVCiEnable; + + // + // Set LPSS configuration according to setup value. + // + DxePlatformPchPolicy->LpssConfig->LpssPciModeEnabled = mSystemConfiguration.LpssPciModeEnabled; + + DxePlatformPchPolicy->LpssConfig->Dma1Enabled = mSystemConfiguration.LpssDma1Enabled; + DxePlatformPchPolicy->LpssConfig->I2C0Enabled = mSystemConfiguration.LpssI2C0Enabled; + DxePlatformPchPolicy->LpssConfig->I2C1Enabled = mSystemConfiguration.LpssI2C1Enabled; + DxePlatformPchPolicy->LpssConfig->I2C2Enabled = mSystemConfiguration.LpssI2C2Enabled; + DxePlatformPchPolicy->LpssConfig->I2C3Enabled = mSystemConfiguration.LpssI2C3Enabled; + DxePlatformPchPolicy->LpssConfig->I2C4Enabled = mSystemConfiguration.LpssI2C4Enabled; + DxePlatformPchPolicy->LpssConfig->I2C5Enabled = mSystemConfiguration.LpssI2C5Enabled; + DxePlatformPchPolicy->LpssConfig->I2C6Enabled = mSystemConfiguration.LpssI2C6Enabled; + + DxePlatformPchPolicy->LpssConfig->Dma0Enabled = mSystemConfiguration.LpssDma0Enabled;; + DxePlatformPchPolicy->LpssConfig->Pwm0Enabled = mSystemConfiguration.LpssPwm0Enabled; + DxePlatformPchPolicy->LpssConfig->Pwm1Enabled = mSystemConfiguration.LpssPwm1Enabled; + DxePlatformPchPolicy->LpssConfig->Hsuart0Enabled = mSystemConfiguration.LpssHsuart0Enabled; + DxePlatformPchPolicy->LpssConfig->Hsuart1Enabled = mSystemConfiguration.LpssHsuart1Enabled; + DxePlatformPchPolicy->LpssConfig->SpiEnabled = mSystemConfiguration.LpssSpiEnabled; + + // + // Set SCC configuration according to setup value. + // + DxePlatformPchPolicy->SccConfig->SdioEnabled = mSystemConfiguration.LpssSdioEnabled; + DxePlatformPchPolicy->SccConfig->SdcardEnabled = TRUE; + DxePlatformPchPolicy->SccConfig->SdCardSDR25Enabled = mSystemConfiguration.LpssSdCardSDR25Enabled; + DxePlatformPchPolicy->SccConfig->SdCardDDR50Enabled = mSystemConfiguration.LpssSdCardDDR50Enabled; + DxePlatformPchPolicy->SccConfig->HsiEnabled = mSystemConfiguration.LpssMipiHsi; + + if (mSystemConfiguration.eMMCBootMode== 1) {// Auto detection mode + // + // Silicon Stepping + // + switch (PchStepping()) { + case PchA0: // A0 and A1 + case PchA1: + DEBUG ((EFI_D_ERROR, "Auto Detect: SOC A0/A1: SCC eMMC 4.41 Configuration\n")); + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 1; + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0; + break; + case PchB0: // B0 and later + default: + DEBUG ((EFI_D_ERROR, "Auto Detect: SOC B0 and later: SCC eMMC 4.5 Configuration\n")); + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = mSystemConfiguration.LpsseMMC45Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = mSystemConfiguration.LpsseMMC45DDR50Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = mSystemConfiguration.LpsseMMC45HS200Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = mSystemConfiguration.LpsseMMC45RetuneTimerValue; + break; + } + } else if (mSystemConfiguration.eMMCBootMode == 2) { // eMMC 4.41 + DEBUG ((EFI_D_ERROR, "Force to SCC eMMC 4.41 Configuration\n")); + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 1; + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0; + + } else if (mSystemConfiguration.eMMCBootMode == 3) { // eMMC 4.5 + DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 Configuration\n")); + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = mSystemConfiguration.LpsseMMC45Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = mSystemConfiguration.LpsseMMC45DDR50Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = mSystemConfiguration.LpsseMMC45HS200Enabled; + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = mSystemConfiguration.LpsseMMC45RetuneTimerValue; + + } else { // Disable eMMC controllers + DEBUG ((EFI_D_ERROR, "Disable eMMC controllers\n")); + DxePlatformPchPolicy->SccConfig->eMMCEnabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled = 0; + DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0; + } + + // + // Reserved SMBus Address + // + DxePlatformPchPolicy->SmbusConfig->NumRsvdSmbusAddresses = 4; + DxePlatformPchPolicy->SmbusConfig->RsvdSmbusAddressTable = mSmbusRsvdAddresses; + + // + // MiscPm Configuration + // + DxePlatformPchPolicy->MiscPmConfig->WakeConfig.WolEnableOverride = mSystemConfiguration.WakeOnLanS5; + DxePlatformPchPolicy->MiscPmConfig->SlpLanLowDc = mSystemConfiguration.SlpLanLowDc; + DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeWakeSts = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeHrstColdSts = PCH_DEVICE_ENABLE; + DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeHrstWarmSts = PCH_DEVICE_ENABLE; + + // + // Enable / disable serial IRQ according to setup value. + // + DxePlatformPchPolicy->SerialIrqConfig->SirqEnable = PCH_DEVICE_ENABLE; + + // + // Set Serial IRQ Mode Select according to setup value. + // + DxePlatformPchPolicy->SerialIrqConfig->SirqMode = PchQuietMode; + + // + // Program the default Sub System Vendor Device Id + // + DxePlatformPchPolicy->DefaultSvidSid->SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + DxePlatformPchPolicy->DefaultSvidSid->SubSystemId = V_PCH_DEFAULT_SID; + + mAzaliaVerbTable[9].VerbTableData = mAzaliaVerbTableData12; + + DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTableNum = sizeof (mAzaliaVerbTable) / sizeof (PCH_AZALIA_VERB_TABLE); + DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTable = mAzaliaVerbTable; + DxePlatformPchPolicy->AzaliaConfig->ResetWaitTimer = 300; + + DxePlatformPchPolicy->IdleReserve = mSystemConfiguration.IdleReserve; + DxePlatformPchPolicy->AcpiHWRed = PCH_DEVICE_DISABLE; + + // + // Install DxePchPolicyUpdateProtocol + // + Handle = NULL; + + mDxePchPolicyUpdate.Revision = DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePchPolicyUpdateProtocolGuid, + &mDxePchPolicyUpdate, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - End\n")); +} + + +DXE_VLV_PLATFORM_POLICY_PROTOCOL mDxePlatformVlvPolicy; + +VOID +InitVlvPlatformPolicy ( + ) +{ + DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformVlvPolicy; + EFI_STATUS Status; + EFI_HANDLE Handle; + + ZeroMem (&mDxePlatformVlvPolicy, sizeof(DXE_VLV_PLATFORM_POLICY_PROTOCOL)); + + DxePlatformVlvPolicy = &mDxePlatformVlvPolicy; + + + DxePlatformVlvPolicy->GraphicReserve00 = mSystemConfiguration.GraphicReserve00; + DxePlatformVlvPolicy->PavpMode = mSystemConfiguration.PavpMode; + DxePlatformVlvPolicy->GraphicReserve01 = 1; + DxePlatformVlvPolicy->GraphicReserve02 = mSystemConfiguration.GraphicReserve02; + DxePlatformVlvPolicy->GraphicReserve03 = 1; + DxePlatformVlvPolicy->GraphicReserve04 = 0; + DxePlatformVlvPolicy->GraphicReserve05 = mSystemConfiguration.GraphicReserve05; + DxePlatformVlvPolicy->IgdPanelFeatures.PFITStatus = mSystemConfiguration.PanelScaling; + + DxePlatformVlvPolicy->IgdPanelFeatures.LidStatus = 1; + DxePlatformVlvPolicy->IdleReserve = mSystemConfiguration.IdleReserve; + + DxePlatformVlvPolicy->GraphicReserve06 = 1; + + if ( (mSystemConfiguration.Lpe == 1) || mSystemConfiguration.Lpe == 2) { + DxePlatformVlvPolicy ->AudioTypeSupport = LPE_AUDIO ; + } else if ( mSystemConfiguration.PchAzalia == 1 ) { + DxePlatformVlvPolicy ->AudioTypeSupport = HD_AUDIO; + } else { + DxePlatformVlvPolicy ->AudioTypeSupport = NO_AUDIO; + } + + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gDxeVlvPlatformPolicyGuid, + EFI_NATIVE_INTERFACE, + DxePlatformVlvPolicy + ); + ASSERT_EFI_ERROR(Status); + +} diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c b/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c new file mode 100644 index 0000000000..06d325c39e --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c @@ -0,0 +1,141 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ IchRegTable.c
+
+Abstract:
+
+ Register initialization table for Ich.
+
+
+
+--*/
+
+#include <Library/EfiRegTableLib.h>
+#include "PlatformDxe.h"
+extern EFI_PLATFORM_INFO_HOB mPlatformInfo;
+
+#define R_EFI_PCI_SVID 0x2C
+
+EFI_REG_TABLE mSubsystemIdRegs [] = {
+
+ //
+ // Program SVID and SID for PCI devices.
+ // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance
+ //
+ PCI_WRITE (
+ MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+
+ PCI_WRITE (
+ IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+
+ PCI_WRITE(
+ DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ PCI_WRITE (
+ DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,
+ V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE
+ ),
+ TERMINATE_TABLE
+};
+
+/**
+ Updates the mSubsystemIdRegs table, and processes it. This should program
+ the Subsystem Vendor and Device IDs.
+
+ @retval Returns VOID
+
+**/
+VOID
+InitializeSubsystemIds (
+ )
+{
+
+ EFI_REG_TABLE *RegTablePtr;
+ UINT32 SubsystemVidDid;
+ UINT32 SubsystemAudioVidDid;
+
+ SubsystemVidDid = mPlatformInfo.SsidSvid;
+ SubsystemAudioVidDid = mPlatformInfo.SsidSvid;
+
+ RegTablePtr = mSubsystemIdRegs;
+
+ //
+ // While we are not at the end of the table
+ //
+ while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {
+ //
+ // If the data to write is the original SSID
+ //
+ if (RegTablePtr->PciWrite.Data ==
+ ((V_PCH_DEFAULT_SID << 16) |
+ V_PCH_INTEL_VENDOR_ID)
+ ) {
+
+ //
+ // Then overwrite it to use the alternate SSID
+ //
+ RegTablePtr->PciWrite.Data = SubsystemVidDid;
+ }
+
+ //
+ // Go to next table entry
+ //
+ RegTablePtr++;
+ }
+
+ RegTablePtr = mSubsystemIdRegs;
+
+
+ //
+ // Program the SSVID/SSDID
+ //
+ ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);
+
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c b/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c new file mode 100644 index 0000000000..7c21271a09 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c @@ -0,0 +1,216 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ IchTcoReset.c
+
+Abstract:
+ Implements the programming of events in TCO Reset
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include <Protocol/TcoReset.h>
+#include <Protocol/HwWatchdogTimer.h>
+
+
+EFI_STATUS
+EFIAPI
+EnableTcoReset (
+ IN UINT32 *RcrbGcsSaveValue
+ );
+
+EFI_STATUS
+EFIAPI
+DisableTcoReset (
+ OUT UINT32 RcrbGcsRestoreValue
+ );
+
+EFI_TCO_RESET_PROTOCOL mTcoResetProtocol = {
+ EnableTcoReset,
+ DisableTcoReset
+};
+
+/**
+
+ Enables the TCO timer to reset the system in case of a system hang. This is
+ used when writing the clock registers.
+
+ @param RcrbGcsSaveValue This is the value of the RCRB GCS register before it is
+ changed by this procedure. This will be used to restore
+ the settings of this register in PpiDisableTcoReset.
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+EnableTcoReset (
+ IN UINT32 *RcrbGcsSaveValue
+ )
+{
+ UINT16 TmpWord;
+ UINT16 AcpiBase;
+ EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
+ EFI_STATUS Status;
+ UINTN PbtnDisableInterval = 4; //Default value
+
+ //
+ // Get Watchdog Timer protocol.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiWatchdogTimerDriverProtocolGuid,
+ NULL,
+ (VOID **)&WatchdogTimerProtocol
+ );
+
+ //
+ // If the protocol is present, shut off the Timer as we enter BDS
+ //
+ if (!EFI_ERROR(Status)) {
+ WatchdogTimerProtocol->RestartWatchdogTimer();
+ WatchdogTimerProtocol->AllowKnownReset(TRUE);
+ }
+
+ if (*RcrbGcsSaveValue == 0) {
+ PbtnDisableInterval = PcdGet32(PcdPBTNDisableInterval);
+ } else {
+ PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;
+ }
+
+ //
+ // Read ACPI Base Address
+ //
+ AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
+
+ //
+ // Stop TCO if not already stopped
+ //
+ TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
+ TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
+ IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
+
+ //
+ // Clear second TCO status
+ //
+ IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
+
+ //
+ // Enable reboot on TCO timeout
+ //
+ *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG);
+ MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8) ~B_PCH_PMC_PM_CFG_NO_REBOOT);
+
+ //
+ // Set TCO reload value (interval *.6s)
+ //
+ IoWrite32(AcpiBase + R_PCH_TCO_TMR, (UINT32)(PbtnDisableInterval<<16));
+
+ //
+ // Force TCO to load new value
+ //
+ IoWrite8(AcpiBase + R_PCH_TCO_RLD, 4);
+
+ //
+ // Clear second TCO status
+ //
+ IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);
+
+ //
+ // Start TCO timer running
+ //
+ TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
+ TmpWord &= ~(B_PCH_TCO_CNT_TMR_HLT);
+ IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disables the TCO timer. This is used after writing the clock registers.
+
+ @param RcrbGcsRestoreValue Value saved in PpiEnableTcoReset so that it can
+ restored.
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+DisableTcoReset (
+ OUT UINT32 RcrbGcsRestoreValue
+ )
+{
+ UINT16 TmpWord;
+ UINT16 AcpiBase;
+ EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL *WatchdogTimerProtocol;
+ EFI_STATUS Status;
+
+ //
+ // Read ACPI Base Address
+ //
+ AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;
+
+ //
+ // Stop the TCO timer
+ //
+ TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);
+ TmpWord |= B_PCH_TCO_CNT_TMR_HLT;
+ IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);
+
+ //
+ // Get Watchdog Timer protocol.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiWatchdogTimerDriverProtocolGuid,
+ NULL,
+ (VOID **)&WatchdogTimerProtocol
+ );
+
+ //
+ // If the protocol is present, shut off the Timer as we enter BDS
+ //
+ if (!EFI_ERROR(Status)) {
+ WatchdogTimerProtocol->AllowKnownReset(FALSE);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Updates the feature policies according to the setup variable.
+
+ @retval Returns VOID
+
+**/
+VOID
+InitTcoReset (
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiTcoResetProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mTcoResetProtocol
+ );
+ ASSERT_EFI_ERROR(Status);
+
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c b/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c new file mode 100644 index 0000000000..69932223bd --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c @@ -0,0 +1,77 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ IdccInfo.c
+
+Abstract:
+
+ Platform information used by IDCC.
+
+Revision History
+
+--*/
+
+#include "PlatformDxe.h"
+
+#include <Guid/IdccData.h>
+
+extern EFI_GUID mPlatformDriverGuid;
+
+
+EFI_STATUS
+WriteIdccInfo (
+ )
+{
+ EFI_STATUS Status;
+ EFI_DATA_HUB_PROTOCOL *DataHub;
+ UINT8 Ratio;
+ EFI_IDCC_PROCESSOR_RATIO ProcRatio;
+
+ //
+ // Locate the data hub protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiDataHubProtocolGuid,
+ NULL,
+ (VOID **) &DataHub
+ );
+
+ //
+ // Find processor actual ratio
+ //
+ Ratio = 15; //Temporary - some dummy value.
+
+ //
+ // Fill in IDCC Type 5 structure
+ //
+ ProcRatio.IdccHeader.Type = EFI_IDCC_PROC_RATIO_TYPE;
+ ProcRatio.IdccHeader.RecordLength = sizeof(EFI_IDCC_PROCESSOR_RATIO);
+ ProcRatio.ProcessorRatio = Ratio;
+
+ //
+ // Write data to the data hub
+ //
+ Status = DataHub->LogData (
+ DataHub,
+ &gIdccDataHubGuid,
+ &mPlatformDriverGuid,
+ EFI_DATA_RECORD_CLASS_DATA,
+ &ProcRatio,
+ sizeof(EFI_IDCC_PROCESSOR_RATIO)
+ );
+
+ return Status;
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c new file mode 100644 index 0000000000..9ac816dd40 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c @@ -0,0 +1,166 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ LegacySpeaker.c
+
+Abstract:
+
+ This file implements DXE for Legacy Speaker.
+
+--*/
+
+#include "LegacySpeaker.h"
+
+/**
+
+ This function will enable the speaker to generate beep
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+TurnOnSpeaker (
+ )
+{
+ UINT8 Data;
+ Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
+ Data |= 0x03;
+ IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function will stop beep from speaker.
+
+ @retval Status
+
+**/
+EFI_STATUS
+TurnOffSpeaker (
+ )
+{
+ UINT8 Data;
+
+ Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);
+ Data &= 0xFC;
+ IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);
+ return EFI_SUCCESS;
+}
+
+/**
+ Generate beep sound based upon number of beeps and duration of the beep
+
+ @param NumberOfBeeps Number of beeps which user want to produce
+ @param BeepDuration Duration for speaker gate need to be enabled
+ @param TimeInterval Interval between each beep
+
+ @retval Does not return if the reset takes place.
+ EFI_INVALID_PARAMETER If ResetType is invalid.
+
+**/
+EFI_STATUS
+OutputBeep (
+ IN UINTN NumberOfBeep,
+ IN UINTN BeepDuration,
+ IN UINTN TimeInterval
+ )
+{
+ UINTN Num;
+
+ for (Num=0; Num < NumberOfBeep; Num++) {
+ TurnOnSpeaker ();
+ //
+ // wait some time,at least 120us
+ //
+ gBS->Stall (BeepDuration);
+ TurnOffSpeaker();
+ gBS->Stall (TimeInterval);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function will program the speaker tone frequency. The value should be with 64k
+ boundary since it takes only 16 bit value which gets programmed in two step IO opearattion
+
+ @param Frequency A value which should be 16 bit only.
+
+ @retval EFI_SUCESS
+
+**/
+EFI_STATUS
+EFIAPI
+ProgramToneFrequency (
+ IN EFI_SPEAKER_IF_PROTOCOL * This,
+ IN UINT16 Frequency
+ )
+{
+ UINT8 Data;
+
+ Data = 0xB6;
+ IoWrite8(EFI_TIMER_CONTROL_PORT, Data);
+
+ Data = (UINT8)(Frequency & 0x00FF);
+ IoWrite8(EFI_TIMER_2_PORT, Data);
+ Data = (UINT8)((Frequency & 0xFF00) >> 8);
+ IoWrite8(EFI_TIMER_2_PORT, Data);
+ return EFI_SUCCESS;
+}
+
+/**
+ This function will generate the beep for specified duration.
+
+ @param NumberOfBeeps Number of beeps which user want to produce
+ @param BeepDuration Duration for speaker gate need to be enabled
+ @param TimeInterval Interval between each beep
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+GenerateBeepTone (
+ IN EFI_SPEAKER_IF_PROTOCOL * This,
+ IN UINTN NumberOfBeeps,
+ IN UINTN BeepDuration,
+ IN UINTN TimeInterval
+ )
+{
+
+ if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0)) {
+ TurnOnSpeaker ();
+ return EFI_SUCCESS;
+ }
+
+ if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0)) {
+ TurnOffSpeaker ();
+ return EFI_SUCCESS;
+ }
+
+ if (BeepDuration == 0) {
+ BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;
+ }
+
+ if (TimeInterval == 0) {
+ TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL;
+ }
+
+ OutputBeep (NumberOfBeeps, BeepDuration, TimeInterval);
+ return EFI_SUCCESS;
+
+
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h new file mode 100644 index 0000000000..2075139195 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h @@ -0,0 +1,74 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ LegacySpeaker.h
+
+Abstract:
+
+ Speaker enabling related data
+
+--*/
+
+#ifndef _DXE_LEGACY_SPEAKER_H
+#define _DXE_LEGACY_SPEAKER_H
+
+#include "PlatformDxe.h"
+
+//
+// Speaker Related Port Information
+//
+#define EFI_TIMER_COUNTER_PORT 0x40
+#define EFI_TIMER_CONTROL_PORT 0x43
+#define EFI_TIMER_2_PORT 0x42
+#define EFI_SPEAKER_CONTROL_PORT 0x61
+
+#define EFI_SPEAKER_OFF_MASK 0xFC
+
+#define EFI_DEFAULT_BEEP_FREQUENCY 0x500
+
+//
+// Default Intervals/Beep Duration
+//
+#define EFI_DEFAULT_LONG_BEEP_DURATION 0x70000
+#define EFI_DEFAULT_SHORT_BEEP_DURATION 0x50000
+#define EFI_DEFAULT_BEEP_TIME_INTERVAL 0x20000
+
+
+EFI_STATUS
+EFIAPI
+ProgramToneFrequency (
+ IN EFI_SPEAKER_IF_PROTOCOL * This,
+ IN UINT16 Frequency
+ );
+
+
+EFI_STATUS
+EFIAPI
+GenerateBeepTone (
+ IN EFI_SPEAKER_IF_PROTOCOL * This,
+ IN UINTN NumberOfBeeps,
+ IN UINTN BeepDuration,
+ IN UINTN TimeInterval
+ );
+
+EFI_STATUS
+TurnOnSpeaker (
+ );
+
+EFI_STATUS
+TurnOffSpeaker (
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c new file mode 100644 index 0000000000..c67862c081 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c @@ -0,0 +1,587 @@ +/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ Observable.c
+
+Abstract:
+
+ The following contains all of the implementation for the Observable protocol. The
+ protocol uses the observer design pattern to provide a way to publish events and
+ to subscribe to those events so that a callback will be performed at the time of
+ the event. The observables and subscribers are maintained by the static tree,
+ mObservableDb. The difference between this protocol and the existing event protocol
+ that exists within the EFI framework is that this protocol allows for parameters
+ to be passed to the subscribed callbacks that can contain up to date context.
+
+--*/
+
+#include "Observable.h"
+
+static OBS_TREE* mObservableDb = NULL;
+static EFI_HANDLE mObservableHandle = NULL;
+static OBS_OBSERVABLE_PROTOCOL mObservable = {
+ AddObservable,
+ RemoveObservable,
+ Subscribe,
+ Unsubscribe,
+ Publish,
+ RemoveAllObservables
+};
+
+/** Install observable protocol.
+ *
+ * Install interface and initialize the observable protocol.
+ *
+ * @param VOID No parameters.
+ *
+ * @return EFI_SUCCESS Successfully installed and initialized the protocol.
+ **/
+EFI_STATUS
+InitializeObservableProtocol(
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Install protocol.
+ //
+ Status = gBS->InstallProtocolInterface (
+ &mObservableHandle,
+ &gObservableProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mObservable
+ );
+
+ return Status;
+}
+
+/** Deletes a subscriber
+ *
+ * This function removes the subscriber pointed to by Head.
+ *
+ * @param OBS_TREE* Head Points to the current subscriber.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing the subscriber.
+ **/
+OBS_LEAF*
+DeleteSubscriber(
+ OBS_LEAF* Head
+ )
+{
+ OBS_LEAF* Temp;
+
+ if (Head) {
+ Temp = Head;
+ Head = Head->Next;
+ gBS->FreePool(Temp);
+ }
+
+ return Head;
+}
+
+/** Finds and deletes all subscribers
+ *
+ * This function iterates recursively through the existing subscribers and delets them all.
+ *
+ * @param OBS_TREE* Head Points to the current subscriber.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing the subscribers.
+ **/
+OBS_LEAF*
+DeleteAllSubscribers(
+ OBS_LEAF* Head
+ )
+{
+ if (Head) {
+ if (Head->Next) {
+ //
+ // We aren't at the end of the list yet.
+ //
+ Head->Next = DeleteAllSubscribers(Head->Next);
+ }
+
+ //
+ // At the end, so delete the subscriber.
+ //
+ Head = DeleteSubscriber(Head);
+ }
+
+ return Head;
+}
+
+/** Deletes an observable
+ *
+ * This function removes the observable pointed to by Head.
+ *
+ * @param OBS_TREE* Head Points to the current observable.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing the observable.
+ **/
+OBS_TREE*
+DeleteObservable(
+ OBS_TREE* Head
+ )
+{
+ OBS_TREE* Temp;
+
+ if (Head) {
+ Temp = Head;
+ Head = Head->Next;
+ gBS->FreePool(Temp);
+ }
+
+ return Head;
+}
+
+/** Finds and deletes all observables
+ *
+ * This function iterates recursively through the existing observables database and, starting with
+ * the last most observable, deletes all of its subscribers, then deletes the observable itself.
+ *
+ * @param OBS_TREE* Head Points to the current observable.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing the observables.
+ **/
+OBS_TREE*
+DeleteAllObservables(
+ OBS_TREE* Head
+ )
+{
+ if (Head) {
+ if (Head->Next) {
+ //
+ // We aren't at the end of the list yet.
+ //
+ Head->Next = DeleteAllObservables(Head->Next);
+ }
+
+ //
+ // This is the end of the list of observables.
+ //
+ Head->Leaf = DeleteAllSubscribers(Head->Leaf);
+
+ //
+ // Subscribers are deleted, so now delete the observable.
+ //
+ Head = DeleteObservable(Head);
+ }
+
+ return Head;
+}
+
+/** Finds and deletes observable
+ *
+ * This function iterates recursively through the existing observable database in order to find the one
+ * specified by ReferenceGuid so that it can be deleted. If the requested observable is found, before it
+ * is deleted, all of the subscribers that are listening to this observable are deleted.
+ *
+ * @param OBS_TREE* Head Points to the current observable.
+ * EFI_GUID ReferenceGuid Corresponds to the observable that we're looking for.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing (or not finding) the observable.
+ **/
+OBS_TREE*
+FindAndDeleteObservable(
+ OBS_TREE* Head,
+ EFI_GUID ReferenceGuid
+ )
+{
+ if (Head) {
+ if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {
+ //
+ // We found the observable. Delete all of it's subscribers, first.
+ //
+ Head->Leaf = DeleteAllSubscribers(Head->Leaf);
+ //
+ // Now we can safely remove the observable.
+ //
+ Head = DeleteObservable(Head);
+ } else {
+ //
+ // Not found. Keep searching.
+ //
+ Head->Next = FindAndDeleteObservable(Head->Next, ReferenceGuid);
+ }
+ }
+
+ return Head;
+}
+
+/** Finds and deletes subscriber
+ *
+ * This function iterates recursively through the existing subscribers that are listening to the
+ * observable that was found when this function was called.
+ *
+ * @param OBS_TREE* Head Points to the current subscriber.
+ * OBS_CALLBACK CallbackInterface This is the subscriber that is requested be removed.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing (or not finding) the subscriber.
+ **/
+OBS_LEAF*
+_FindAndDeleteSubscriber(
+ OBS_LEAF* Head,
+ OBS_CALLBACK CallbackInterface
+ )
+{
+ if (Head) {
+ if (Head->Observer == CallbackInterface) {
+ //
+ // Found it. Now let's delete it.
+ //
+ Head = DeleteSubscriber(Head);
+ } else {
+ //
+ // Not found. Keep searching.
+ //
+ Head->Next = _FindAndDeleteSubscriber(Head->Next, CallbackInterface);
+ }
+ }
+
+ return Head;
+}
+
+/** Finds and deletes subscriber
+ *
+ * This function iterates recursively through the existing observables database until it either finds
+ * a matching guid or reaches the end of the list. After finding a match, it calls a helper function,
+ * _FindAndDeleteSubscriber. At this point, all responsibility for finding and deleting the subscriber
+ * lies on the helper function.
+ *
+ * @param OBS_TREE* Head Points to the current observable.
+ * EFI_GUID ReferenceGuid Corresponds to the observable that we're looking for.
+ * OBS_CALLBACK CallbackInterface This is the subscriber that is requested be removed.
+ *
+ * @return OBS_TREE* Returns the tree after successfully removing (or not finding) the subscriber.
+ **/
+OBS_TREE*
+FindAndDeleteSubscriber(
+ IN OUT OBS_TREE* Head,
+ IN EFI_GUID ReferenceGuid,
+ IN OBS_CALLBACK CallbackInterface
+ )
+{
+ if (Head) {
+ if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {
+ //
+ // We found the observer that matches ReferenceGuid. Find and delete the subscriber that is
+ // listening to it.
+ //
+ Head->Leaf = _FindAndDeleteSubscriber(Head->Leaf, CallbackInterface);
+ } else {
+ //
+ // Not found. Keep searching.
+ //
+ Head->Next = FindAndDeleteSubscriber(Head->Next, ReferenceGuid, CallbackInterface);
+ }
+ }
+
+ return Head;
+}
+
+/** Remove all observables.
+ *
+ * Remove all observable guids and all interfaces subscribed to them.
+ *
+ * @param VOID No parameters.
+ *
+ * @return EFI_SUCCESS Successfully removed all observables and subscribed interfaces.
+ **/
+EFI_STATUS
+EFIAPI
+RemoveAllObservables(
+ VOID
+ )
+{
+ mObservableDb = DeleteAllObservables(mObservableDb);
+
+ return EFI_SUCCESS;
+}
+
+/** Subscribe an interface with an observable guid.
+ *
+ * Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed
+ * whenever the appropriate observable instance specified by ReferenceGuid calls Publish.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid that the callback interface will subscribe to.
+ * OBS_CASLLBACK CallbackInterface A pointer to the function that is subscribing to the observable.
+ *
+ * @return EFI_SUCCESS Successfully subscribed the interface to the observable guid.
+ * EFI_NOT_FOUND No match could be found between the provided guid and existing observables.
+ * EFI_OUT_OF_RESOURCES Could not subscribe to this observer due to resource limitations.
+ * EFI_INVALID_PARAMETER Interface is already subscribed to this observer.
+ **/
+EFI_STATUS
+EFIAPI
+Subscribe (
+ IN EFI_GUID ReferenceGuid,
+ IN OBS_CALLBACK CallbackInterface
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ OBS_TREE* TempTree = NULL;
+ OBS_LEAF* Last = NULL;
+ OBS_LEAF* TempLeaf = NULL;
+ OBS_LEAF* NewLeaf = NULL;
+ BOOLEAN Found = FALSE;
+
+ if (mObservableDb != NULL) {
+ //
+ // Find the observable guid that we're looking for.
+ //
+ for (TempTree = mObservableDb; TempTree != NULL; TempTree = TempTree->Next) {
+ if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {
+ Found = TRUE;
+ break;
+ }
+ }
+ if (Found) {
+ //
+ // Prepare to add a new leaf.
+ //
+ NewLeaf = AllocateZeroPool(sizeof(OBS_LEAF));
+ if (!NewLeaf) {
+ Status = EFI_OUT_OF_RESOURCES;
+ } else {
+ NewLeaf->Next = NULL;
+ NewLeaf->Observer = CallbackInterface;
+ //
+ // Go to the end of the list of observers.
+ //
+ if (TempTree->Leaf != NULL) {
+ //
+ // First check to see if this is a duplicate observer.
+ //
+ Found = FALSE;
+ TempLeaf = TempTree->Leaf;
+ do {
+ Last = TempLeaf;
+ if (TempLeaf->Observer == CallbackInterface) {
+ //
+ // It is, so let's abort this process.
+ //
+ Found = TRUE;
+ break;
+ }
+ TempLeaf = TempLeaf->Next;
+ } while (TempLeaf != NULL);
+ TempLeaf = Last;
+
+ //
+ // Check for duplicates.
+ //
+ if (Found) {
+ gBS->FreePool(NewLeaf);
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ //
+ // At this point, TempLeaf->Next will be the end of the list.
+ //
+ TempLeaf->Next = NewLeaf;
+ }
+ } else {
+ //
+ // There are no observers listening to this guid. Start a new list.
+ //
+ TempTree->Leaf = NewLeaf;
+ }
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+
+ return Status;
+}
+
+/** Unsubscribe an interface with an observable guid.
+ *
+ * Use this to remove an interface from the callback list associated with an observable guid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to unsubscribe the interface from.
+ * OBS_NOTIFY_INTERFACE NotifyCallback A pointer to the interface that is being unsubscribed.
+ *
+ * @return EFI_SUCCESS Successfully unsubscribed the interface from the observable guid.
+ **/
+EFI_STATUS
+EFIAPI
+Unsubscribe (
+ IN EFI_GUID ReferenceGuid,
+ IN OBS_CALLBACK CallbackInterface
+ )
+{
+ mObservableDb = FindAndDeleteSubscriber(mObservableDb, ReferenceGuid, CallbackInterface);
+
+ return EFI_SUCCESS;
+}
+
+/** Notify observing functions.
+ *
+ * Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid that contains the the list of interfaces to be notified.
+ * VOID* Data Parameter context to be passed to the notification function.
+ *
+ * @return EFI_SUCCESS Successfully notified all observers listening to this guid.
+ * EFI_NOT_FOUND No match could be found between the provided guid and existing observables.
+ **/
+EFI_STATUS
+EFIAPI
+Publish (
+ IN EFI_GUID ReferenceGuid,
+ IN OUT VOID* Data
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ OBS_TREE* TempTree = NULL;
+ OBS_LEAF* TempLeaf = NULL;
+ BOOLEAN Found = FALSE;
+
+ if (mObservableDb != NULL) {
+ //
+ // Find the observable guid that we're looking for.
+ //
+ for (TempTree = mObservableDb; TempTree != NULL; TempTree = TempTree->Next) {
+ if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {
+ Found = TRUE;
+ break;
+ }
+ }
+ if (Found) {
+ //
+ // Notify every listener by performing each provided callback.
+ //
+ for (TempLeaf = TempTree->Leaf; TempLeaf != NULL; TempLeaf = TempLeaf->Next) {
+ if (TempLeaf->Observer != NULL) {
+ //
+ // Execute the callback.
+ //
+ TempLeaf->Observer(Data);
+ }
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+
+ return Status;
+}
+
+/** Creates a new observable.
+ *
+ * Create a new observable that can be observed with the use of Subscribe function.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to add.
+ *
+ * @return EFI_SUCCESS Successfully added observable.
+ * EFI_INVALID_PARAMETER Observable already exists.
+ **/
+EFI_STATUS
+EFIAPI
+AddObservable (
+ IN EFI_GUID ReferenceGuid
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ OBS_TREE* TempTree = NULL;
+ OBS_TREE* Last = NULL;
+ OBS_TREE* NewTree = NULL;
+ BOOLEAN Found = FALSE;
+
+ if (mObservableDb != NULL) {
+ if (mObservableDb->Next != NULL) {
+ //
+ // Iterate to the end of the observable list while checking to see if we aren't creating a duplicate.
+ //
+ TempTree = mObservableDb->Next;
+ do {
+ Last = TempTree;
+ if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {
+ Found = TRUE;
+ break;
+ }
+ TempTree = TempTree->Next;
+ } while (TempTree != NULL);
+ TempTree = Last;
+ } else {
+ TempTree = mObservableDb;
+ }
+ if (Found) {
+ //
+ // Duplicate, so reject the parameter.
+ //
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ //
+ // TempTree->Next is our target. Prepare to add a new tree link.
+ //
+ NewTree = AllocateZeroPool(sizeof(OBS_TREE));
+ if (NewTree) {
+ NewTree->Next = NULL;
+ NewTree->Leaf = NULL;
+ CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid));
+ TempTree->Next = NewTree;
+ } else {
+ Status = EFI_OUT_OF_RESOURCES;
+ }
+ }
+ } else {
+ //
+ // mObservableDb has not been created yet. Let's do that.
+ //
+ NewTree = AllocateZeroPool(sizeof(OBS_TREE));
+ if (NewTree) {
+ NewTree->Next = NULL;
+ NewTree->Leaf = NULL;
+ CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid));
+ mObservableDb = NewTree;
+ } else {
+ Status = EFI_OUT_OF_RESOURCES;
+ }
+ }
+
+ return Status;
+}
+
+/** Remove an observable.
+ *
+ * Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions
+ * that are subscribed to this guid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to remove.
+ *
+ * @return EFI_SUCCESS Successfully removed observable.
+ **/
+EFI_STATUS
+EFIAPI
+RemoveObservable (
+ IN EFI_GUID ReferenceGuid
+ )
+{
+ mObservableDb = FindAndDeleteObservable(mObservableDb, ReferenceGuid);
+
+ return EFI_SUCCESS;
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h new file mode 100644 index 0000000000..a6bc62bb0b --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h @@ -0,0 +1,142 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ Observable.h
+
+Abstract:
+
+ Prototypes for Observable protocol implementation
+--*/
+
+#ifndef _OBSERVABLE_H_
+#define _OBSERVABLE_H_
+#include "PlatformDxe.h"
+#include "Protocol/Observable.h"
+
+//
+// Prototypes
+//
+
+/** Install observable protocol.
+ *
+ * Install interface and initialize the observable protocol.
+ *
+ * @param VOID No parameters.
+ *
+ * @return EFI_SUCCESS Successfully installed and initialized the protocol.
+ **/
+EFI_STATUS
+InitializeObservableProtocol(
+ VOID
+ );
+
+/** Remove all observables.
+ *
+ * Remove all observable guids and all interfaces subscribed to them.
+ *
+ * @param VOID No parameters.
+ *
+ * @return EFI_SUCCESS Successfully removed all observables and subscribed interfaces.
+ **/
+EFI_STATUS
+EFIAPI
+RemoveAllObservables(
+ VOID
+ );
+
+/** Subscribe an interface with an observable guid.
+ *
+ * Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed
+ * whenever the appropriate observable instance specified by ReferenceGuid calls Publish.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid that the callback interface will subscribe to.
+ * OBS_CALLBACK CallbackInterface A pointer to the function that is subscribing to the observable.
+ *
+ * @return EFI_SUCCESS Successfully subscribed the interface to the observable guid.
+ * EFI_NOT_FOUND No match could be found between the provided guid and existing observables.
+ * EFI_OUT_OF_RESOURCES Could not subscribe to this observer due to resource limitations.
+ * EFI_INVALID_PARAMETER Interface is already subscribed to this observer.
+ **/
+EFI_STATUS
+EFIAPI
+Subscribe (
+ IN EFI_GUID ReferenceGuid,
+ IN OBS_CALLBACK CallbackInterface
+ );
+
+/** Unsubscribe an interface with an observable guid.
+ *
+ * Use this to remove an interface from the callback list associated with an observable guid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to unsubscribe the interface from.
+ * OBS_CALLBACK CallbackInterface A pointer to the interface that is being unsubscribed.
+ *
+ * @return EFI_SUCCESS Successfully unsubscribed the interface from the observable guid.
+ **/
+EFI_STATUS
+EFIAPI
+Unsubscribe (
+ IN EFI_GUID ReferenceGuid,
+ IN OBS_CALLBACK CallbackInterface
+ );
+
+/** Notify observing functions.
+ *
+ * Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid that contains the list of interfaces to be notified.
+ * VOID* Data Parameter context to be passed to the subscribed function.
+ *
+ * @return EFI_SUCCESS Successfully notified all observers listening to this guid.
+ * EFI_NOT_FOUND No match could be found between the provided guid and existing observables.
+ **/
+EFI_STATUS
+EFIAPI
+Publish (
+ IN EFI_GUID ReferenceGuid,
+ IN OUT VOID* Data
+ );
+
+/** Creates a new observable.
+ *
+ * Create a new observable that can be observed with the use of Subscribe function.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to add.
+ *
+ * @return EFI_SUCCESS Successfully added observable.
+ * EFI_INVALID_PARAMETER Observable already exists.
+ **/
+EFI_STATUS
+EFIAPI
+AddObservable (
+ IN EFI_GUID ReferenceGuid
+ );
+
+/** Remove an observable.
+ *
+ * Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions
+ * that are subscribed to this guid.
+ *
+ * @param EFI_GUID ReferenceGuid The observable guid to remove.
+ *
+ * @return EFI_SUCCESS Successfully removed observable.
+ **/
+EFI_STATUS
+EFIAPI
+RemoveObservable (
+ IN EFI_GUID ReferenceGuid
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h b/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h new file mode 100644 index 0000000000..89e31d265a --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h @@ -0,0 +1,384 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+
+#ifndef _EFI_PCI_BUS_H_
+#define _EFI_PCI_BUS_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/LoadedImage.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/LoadFile2.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHotPlugRequest.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciPlatform.h>
+#include <Protocol/PciHotPlugInit.h>
+#include <Protocol/Decompress.h>
+#include <Protocol/BusSpecificDriverOverride.h>
+#include <Protocol/IncompatiblePciDeviceSupport.h>
+#include <Protocol/PciOverride.h>
+#include <Protocol/PciEnumerationComplete.h>
+
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/PeImage.h>
+#include <IndustryStandard/Acpi.h>
+
+typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;
+typedef struct _PCI_BAR PCI_BAR;
+
+#define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
+#define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
+
+#define EFI_PCI_IOV_POLICY_ARI 0x0001
+#define EFI_PCI_IOV_POLICY_SRIOV 0x0002
+#define EFI_PCI_IOV_POLICY_MRIOV 0x0004
+
+typedef enum {
+ PciBarTypeUnknown = 0,
+ PciBarTypeIo16,
+ PciBarTypeIo32,
+ PciBarTypeMem32,
+ PciBarTypePMem32,
+ PciBarTypeMem64,
+ PciBarTypePMem64,
+ PciBarTypeIo,
+ PciBarTypeMem,
+ PciBarTypeMaxType
+} PCI_BAR_TYPE;
+
+
+#define VGABASE1 0x3B0
+#define VGALIMIT1 0x3BB
+
+#define VGABASE2 0x3C0
+#define VGALIMIT2 0x3DF
+
+#define ISABASE 0x100
+#define ISALIMIT 0x3FF
+
+//
+// PCI BAR parameters
+//
+struct _PCI_BAR {
+ UINT64 BaseAddress;
+ UINT64 Length;
+ UINT64 Alignment;
+ PCI_BAR_TYPE BarType;
+ BOOLEAN Prefetchable;
+ UINT8 MemType;
+ UINT16 Offset;
+};
+
+//
+// defined in PCI Card Specification, 8.0
+//
+#define PCI_CARD_MEMORY_BASE_0 0x1C
+#define PCI_CARD_MEMORY_LIMIT_0 0x20
+#define PCI_CARD_MEMORY_BASE_1 0x24
+#define PCI_CARD_MEMORY_LIMIT_1 0x28
+#define PCI_CARD_IO_BASE_0_LOWER 0x2C
+#define PCI_CARD_IO_BASE_0_UPPER 0x2E
+#define PCI_CARD_IO_LIMIT_0_LOWER 0x30
+#define PCI_CARD_IO_LIMIT_0_UPPER 0x32
+#define PCI_CARD_IO_BASE_1_LOWER 0x34
+#define PCI_CARD_IO_BASE_1_UPPER 0x36
+#define PCI_CARD_IO_LIMIT_1_LOWER 0x38
+#define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
+#define PCI_CARD_BRIDGE_CONTROL 0x3E
+
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
+
+#define PPB_BAR_0 0
+#define PPB_BAR_1 1
+#define PPB_IO_RANGE 2
+#define PPB_MEM32_RANGE 3
+#define PPB_PMEM32_RANGE 4
+#define PPB_PMEM64_RANGE 5
+#define PPB_MEM64_RANGE 0xFF
+
+#define P2C_BAR_0 0
+#define P2C_MEM_1 1
+#define P2C_MEM_2 2
+#define P2C_IO_1 3
+#define P2C_IO_2 4
+
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
+
+#define PCI_MAX_HOST_BRIDGE_NUM 0x0010
+
+//
+// Define option for attribute
+//
+#define EFI_SET_SUPPORTS 0
+#define EFI_SET_ATTRIBUTES 1
+
+#define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
+
+struct _PCI_IO_DEVICE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PROTOCOL PciIo;
+ LIST_ENTRY Link;
+
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_LOAD_FILE2_PROTOCOL LoadFile2;
+
+ //
+ // PCI configuration space header type
+ //
+ PCI_TYPE00 Pci;
+
+ //
+ // Bus number, Device number, Function number
+ //
+ UINT8 BusNumber;
+ UINT8 DeviceNumber;
+ UINT8 FunctionNumber;
+
+ //
+ // BAR for this PCI Device
+ //
+ PCI_BAR PciBar[PCI_MAX_BAR];
+
+ //
+ // The bridge device this pci device is subject to
+ //
+ PCI_IO_DEVICE *Parent;
+
+ //
+ // A linked list for children Pci Device if it is bridge device
+ //
+ LIST_ENTRY ChildList;
+
+ //
+ // TURE if the PCI bus driver creates the handle for this PCI device
+ //
+ BOOLEAN Registered;
+
+ //
+ // TRUE if the PCI bus driver successfully allocates the resource required by
+ // this PCI device
+ //
+ BOOLEAN Allocated;
+
+ //
+ // The attribute this PCI device currently set
+ //
+ UINT64 Attributes;
+
+ //
+ // The attributes this PCI device actually supports
+ //
+ UINT64 Supports;
+
+ //
+ // The resource decode the bridge supports
+ //
+ UINT32 Decodes;
+
+ //
+ // TRUE if the ROM image is from the PCI Option ROM BAR
+ //
+ BOOLEAN EmbeddedRom;
+
+ //
+ // The OptionRom Size
+ //
+ UINT64 RomSize;
+
+ //
+ // The OptionRom Size
+ //
+ UINT64 RomBase;
+
+ //
+ // TRUE if all OpROM (in device or in platform specific position) have been processed
+ //
+ BOOLEAN AllOpRomProcessed;
+
+ //
+ // TRUE if there is any EFI driver in the OptionRom
+ //
+ BOOLEAN BusOverride;
+
+ //
+ // A list tracking reserved resource on a bridge device
+ //
+ LIST_ENTRY ReservedResourceList;
+
+ //
+ // A list tracking image handle of platform specific overriding driver
+ //
+ LIST_ENTRY OptionRomDriverList;
+
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;
+ EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;
+
+ BOOLEAN IsPciExp;
+
+ //
+ // For SR-IOV
+ //
+ UINT8 PciExpressCapabilityOffset;
+ UINT32 AriCapabilityOffset;
+ UINT32 SrIovCapabilityOffset;
+ UINT32 MrIovCapabilityOffset;
+ PCI_BAR VfPciBar[PCI_MAX_BAR];
+ UINT32 SystemPageSize;
+ UINT16 InitialVFs;
+ UINT16 ReservedBusNum;
+
+ //
+ // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
+ // but some chipsets support non-stardard I/O window aligments less than 4K.
+ // This field is used to support this case.
+ //
+ UINT16 BridgeIoAlignment;
+};
+
+#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
+ CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
+ CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_LINK(a) \
+ CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
+
+#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
+ CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
+
+
+
+//
+// Global Variables
+//
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
+extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;
+extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;
+extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;
+extern BOOLEAN gFullEnumeration;
+extern UINTN gPciHostBridgeNumber;
+extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
+extern UINT64 gAllOne;
+extern UINT64 gAllZero;
+extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;
+extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;
+extern BOOLEAN mReserveIsaAliases;
+extern BOOLEAN mReserveVgaAliases;
+
+/**
+ Macro that checks whether device is a GFX device.
+
+ @param _p Specified device.
+
+ @retval TRUE Device is a a GFX device.
+ @retval FALSE Device is not a a GFX device.
+
+**/
+#define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
+
+/**
+ Test to see if this driver supports ControllerHandle. Any ControllerHandle
+ than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to test.
+ @param RemainingDevicePath Optional parameter use to pick a specific child.
+ device to start.
+
+ @retval EFI_SUCCESS This driver supports this device.
+ @retval EFI_ALREADY_STARTED This driver is already running on this device.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Start this driver on ControllerHandle and enumerate Pci bus and start
+ all device under PCI bus.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to bind driver to.
+ @param RemainingDevicePath Optional parameter use to pick a specific child.
+ device to start.
+
+ @retval EFI_SUCCESS This driver is added to ControllerHandle.
+ @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
+ @retval other This driver does not support this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ );
+
+/**
+ Stop this driver on ControllerHandle. Support stoping any child handles
+ created by this driver.
+
+ @param This Protocol instance pointer.
+ @param Controller Handle of device to stop driver on.
+ @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
+ children is zero stop the entire bus driver.
+ @param ChildHandleBuffer List of Child Handles to Stop.
+
+ @retval EFI_SUCCESS This driver is removed ControllerHandle.
+ @retval other This driver was not removed from this device.
+
+**/
+EFI_STATUS
+EFIAPI
+PciBusDriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE Controller,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c new file mode 100644 index 0000000000..16aaa18563 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c @@ -0,0 +1,517 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ PciDevice.c
+
+Abstract:
+
+ Platform Initialization Driver.
+
+Revision History
+
+--*/
+
+#include "PlatformDxe.h"
+#include "Library/DxeServicesTableLib.h"
+#include "PciBus.h"
+#include "Guid/PciLanInfo.h"
+
+extern VOID *mPciLanInfo;
+extern UINTN mPciLanCount;
+
+extern EFI_HANDLE mImageHandle;
+extern SYSTEM_CONFIGURATION mSystemConfiguration;
+
+
+VOID *mPciRegistration;
+#define NCR_VENDOR_ID 0x1000
+#define ATI_VENDOR_ID 0x1002
+#define INTEL_VENDOR_ID 0x8086
+#define ATI_RV423_ID 0x5548
+#define ATI_RV423_ID2 0x5d57
+#define ATI_RV380_ID 0x3e50
+#define ATI_RV370_ID 0x5b60
+#define SI_VENDOR_ID 0x1095
+#define SI_SISATA_ID 0x3114
+#define SI_SIRAID_PCIUNL 0x40
+#define INTEL_82573E_IDER 0x108D
+
+typedef struct {
+ UINT8 ClassCode;
+ UINT8 SubClassCode;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+} BAD_DEVICE_TABLE;
+
+BAD_DEVICE_TABLE BadDeviceTable[] = {
+ {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_SCSI,(UINT16)NCR_VENDOR_ID, (UINT16)0xffff}, // Any NCR cards
+ {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_IDE,(UINT16)INTEL_VENDOR_ID, (UINT16)INTEL_82573E_IDER}, // Intel i82573E Tekoa GBit Lan IDE-R
+ {(UINT8)0xff,(UINT8)0xff,(UINT16)0xffff,(UINT16)0xffff}
+ };
+
+EFI_STATUS
+PciBusDriverHook (
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT FilterEvent;
+
+ //
+ // Register for callback to PCI I/O protocol
+ //
+ Status = gBS->CreateEvent (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ PciBusEvent,
+ NULL,
+ &FilterEvent
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Register for protocol notifications on this event
+ //
+ Status = gBS->RegisterProtocolNotify (
+ &gEfiPciIoProtocolGuid,
+ FilterEvent,
+ &mPciRegistration
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+VOID
+InitBadBars(
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT16 VendorId,
+ IN UINT16 DeviceId
+ )
+{
+
+ EFI_STATUS Status;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 BaseAddress = 0;
+ UINT64 TempBaseAddress = 0;
+ UINT8 RevId = 0;
+ UINT32 Bar;
+ UINT64 IoSize;
+ UINT64 MemSize;
+ UINTN MemSizeBits;
+
+
+ PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
+ switch ( VendorId) {
+ case ATI_VENDOR_ID:
+ //
+ // ATI fix-ups. At this time all ATI cards in BadDeviceTable
+ // have same problem in that OPROM BAR needs to be increased.
+ //
+ Bar = 0x30 ;
+ //
+ // Get original BAR address
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+ //
+ // Find BAR size
+ //
+ TempBaseAddress = 0xffffffff;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ TempBaseAddress &= 0xfffffffe;
+ MemSize = 1;
+ while ((TempBaseAddress & 0x01) == 0) {
+ TempBaseAddress = TempBaseAddress >> 1;
+ MemSize = MemSize << 1;
+ }
+
+ //
+ // Free up allocated memory memory and re-allocate with increased size.
+ //
+ Status = gDS->FreeMemorySpace (
+ BaseAddress,
+ MemSize
+ );
+ //
+ // Force new alignment
+ //
+ MemSize = 0x8000000;
+ MemSizeBits = 28;
+
+ Status = gDS->AllocateMemorySpace (
+ EfiGcdAllocateAnySearchBottomUp,
+ EfiGcdMemoryTypeMemoryMappedIo,
+ MemSizeBits, // Alignment
+ MemSize,
+ &BaseAddress,
+ mImageHandle,
+ NULL
+ );
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+
+ break;
+ case NCR_VENDOR_ID:
+#define MIN_NCR_IO_SIZE 0x800
+#define NCR_GRAN 11 // 2**11 = 0x800
+ //
+ // NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.
+ //
+ for (Bar = 0x10; Bar < 0x28; Bar+= 4) {
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &BaseAddress
+ );
+ if (BaseAddress && 0x01) {
+ TempBaseAddress = 0xffffffff;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ TempBaseAddress &= 0xfffffffc;
+ IoSize = 1;
+ while ((TempBaseAddress & 0x01) == 0) {
+ TempBaseAddress = TempBaseAddress >> 1;
+ IoSize = IoSize << 1;
+ }
+ if (IoSize < MIN_NCR_IO_SIZE) {
+ Status = gDS->FreeIoSpace (
+ BaseAddress,
+ IoSize
+ );
+
+ Status = gDS->AllocateIoSpace (
+ EfiGcdAllocateAnySearchTopDown,
+ EfiGcdIoTypeIo,
+ NCR_GRAN, // Alignment
+ MIN_NCR_IO_SIZE,
+ &BaseAddress,
+ mImageHandle,
+ NULL
+ );
+ TempBaseAddress = BaseAddress + 1;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ }
+ }
+ }
+
+ break;
+
+ case INTEL_VENDOR_ID:
+ if (DeviceId == INTEL_82573E_IDER) {
+ //
+ // Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not
+ // support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable
+ // them all for Control Blocks and Bus mastering ops as well as Secondary IDE
+ // Controller.
+ // All Tekoa A2 or earlier step chips for now.
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_REVISION_ID_OFFSET,
+ 1,
+ &RevId
+ );
+ if (RevId <= 0x02) {
+ for (Bar = 0x14; Bar < 0x24; Bar+= 4) {
+ //
+ // Maybe want to clean this up a bit later but for now just clear out the secondary
+ // Bars don't worry aboyut freeing up thge allocs.
+ //
+ TempBaseAddress = 0x0;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Bar,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ } // end for
+ }
+ else
+ {
+ //
+ //Tekoa A3 or above:
+ //Clear bus master base address (PCI register 0x20)
+ //since Tekoa does not fully support IDE Bus Mastering
+ //
+ TempBaseAddress = 0x0;
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0x20,
+ 1,
+ (VOID *) &TempBaseAddress
+ );
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+ return;
+}
+
+VOID
+ProgramPciLatency(
+ IN EFI_PCI_IO_PROTOCOL *PciIo
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Program Master Latency Timer
+ //
+ if (mSystemConfiguration.PciLatency != 0) {
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_LATENCY_TIMER_OFFSET,
+ 1,
+ &mSystemConfiguration.PciLatency
+ );
+ }
+ return;
+}
+
+/**
+During S5 shutdown, we need to program PME in all LAN devices.
+Here we identify LAN devices and save their bus/dev/func.
+
+**/
+VOID
+SavePciLanAddress(
+ IN EFI_PCI_IO_PROTOCOL *PciIo
+ )
+{
+ EFI_STATUS Status;
+ UINTN PciSegment,
+ PciBus,
+ PciDevice,
+ PciFunction;
+ VOID *NewBuffer;
+ PCI_LAN_INFO *x;
+
+ Status = PciIo->GetLocation (
+ PciIo,
+ &PciSegment,
+ &PciBus,
+ &PciDevice,
+ &PciFunction
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ mPciLanCount ++;
+ Status = gBS->AllocatePool (
+ EfiBootServicesData,
+ mPciLanCount * sizeof(PCI_LAN_INFO),
+ &NewBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ if (mPciLanCount > 1) {
+ //
+ // copy old data into new, larger buffer
+ //
+ gBS->CopyMem (
+ NewBuffer,
+ mPciLanInfo,
+ (mPciLanCount - 1) * sizeof(PCI_LAN_INFO)
+ );
+
+ //
+ // free the old memory buffer
+ //
+ gBS->FreePool (mPciLanInfo);
+
+ }
+
+ //
+ // init the new entry
+ //
+ x = (PCI_LAN_INFO *)NewBuffer + (mPciLanCount - 1);
+ x->PciBus = (UINT8)PciBus;
+ x->PciDevice = (UINT8)PciDevice;
+ x->PciFunction = (UINT8)PciFunction;
+
+ mPciLanInfo = NewBuffer;
+
+ return;
+}
+
+/**
+ @param Event the event that is signaled.
+ @param Context not used here.
+
+
+**/
+VOID
+EFIAPI
+PciBusEvent (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ )
+{
+
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_IO_DEVICE *PciIoDevice;
+ UINT64 Supports;
+ UINTN Index;
+ UINT8 mCacheLineSize = 0x10;
+
+ while (TRUE) {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByRegisterNotify,
+ NULL,
+ mPciRegistration,
+ &BufferSize,
+ &Handle
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // If no more notification events exist
+ //
+ return;
+ }
+
+ Status = gBS->HandleProtocol (
+ Handle,
+ &gEfiPciIoProtocolGuid,
+ (void **)&PciIo
+ );
+
+ PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
+
+ //
+ // Enable I/O for bridge so port 0x80 codes will come out
+ //
+ if (PciIoDevice->Pci.Hdr.VendorId == V_PCH_INTEL_VENDOR_ID)
+ {
+ Status = PciIo->Attributes(
+ PciIo,
+ EfiPciIoAttributeOperationSupported,
+ 0,
+ &Supports
+ );
+ Supports &= EFI_PCI_DEVICE_ENABLE;
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ Supports,
+ NULL
+ );
+ break;
+ }
+
+ //
+ // Program PCI Latency Timer
+ //
+ ProgramPciLatency(PciIo);
+
+ //
+ // Program Cache Line Size to 64 bytes (0x10 DWORDs)
+ //
+ Status = PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_CACHELINE_SIZE_OFFSET,
+ 1,
+ &mCacheLineSize
+ );
+
+ //
+ // If PCI LAN device, save bus/dev/func info
+ // so we can program PME during S5 shutdown
+ //
+ if (PciIoDevice->Pci.Hdr.ClassCode[2] == PCI_CLASS_NETWORK) {
+ SavePciLanAddress(PciIo);
+ break;
+ }
+
+ //
+ // Workaround for cards with bad BARs
+ //
+ Index = 0;
+ while (BadDeviceTable[Index].ClassCode != 0xff) {
+ if (BadDeviceTable[Index].DeviceId == 0xffff) {
+ if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
+ (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
+ (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId)) {
+ InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);
+ }
+ } else {
+ if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&
+ (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&
+ (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId) &&
+ (PciIoDevice->Pci.Hdr.DeviceId == BadDeviceTable[Index].DeviceId)) {
+
+ InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);
+ }
+ }
+ ++Index;
+ }
+ break;
+ }
+
+ return;
+}
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c new file mode 100644 index 0000000000..0f3a414c5b --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c @@ -0,0 +1,1661 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ Platform.c
+
+Abstract:
+
+ Platform Initialization Driver.
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include "Platform.h"
+#include "PchCommonDefinitions.h"
+#include <Protocol/UsbPolicy.h>
+#include <Protocol/PchPlatformPolicy.h>
+#include <Protocol/TpmMp.h>
+#include <Protocol/CpuIo2.h>
+#include <Library/S3BootScriptLib.h>
+#include <Guid/PciLanInfo.h>
+#include <Guid/ItkData.h>
+#include <Library/PciLib.h>
+#include <PlatformBootMode.h>
+#include <Guid/EventGroup.h>
+#include <Guid/Vlv2Variable.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/IgdOpRegion.h>
+#include <Library/PcdLib.h>
+
+//
+// VLV2 GPIO GROUP OFFSET
+//
+#define GPIO_SCORE_OFFSET 0x0000
+#define GPIO_NCORE_OFFSET 0x1000
+#define GPIO_SSUS_OFFSET 0x2000
+
+typedef struct {
+ UINT32 offset;
+ UINT32 val;
+} CFIO_PNP_INIT;
+
+GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
+{
+// Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
+ GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
+ GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
+};
+
+
+EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
+EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
+SYSTEM_CONFIGURATION mSystemConfiguration;
+SYSTEM_PASSWORDS mSystemPassword;
+EFI_HANDLE mImageHandle;
+BOOLEAN mMfgMode = FALSE;
+VOID *mDxePlatformStringPack;
+UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
+extern CHAR16 gItkDataVarName[];
+
+
+EFI_PLATFORM_INFO_HOB mPlatformInfo;
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
+EFI_EVENT mReadyToBootEvent;
+
+UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
+UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
+UINT32 mSubsystemVidDid;
+UINT32 mSubsystemAudioVidDid;
+
+UINTN mPciLanCount = 0;
+VOID *mPciLanInfo = NULL;
+UINTN SpiBase;
+
+static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
+ ProgramToneFrequency,
+ GenerateBeepTone
+};
+
+EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
+
+
+CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
+{
+ {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
+ {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
+ {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
+ {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
+ {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
+ {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
+ {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
+ {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
+ {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
+ {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
+ {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
+ {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
+ {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
+ {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
+ {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
+ {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
+ {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
+ {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
+};
+
+VOID
+EfiOrMem (
+ IN VOID *Destination,
+ IN VOID *Source,
+ IN UINTN Length
+ );
+
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
+STATIC
+VOID
+InitFirmwareId();
+#endif
+
+
+VOID
+InitializeClockRouting(
+ );
+
+VOID
+InitializeSlotInfo (
+ );
+
+#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
+VOID
+InitializeSensorInfoVariable (
+ );
+#endif
+
+VOID
+InitTcoReset (
+ );
+
+VOID
+InitExI ();
+
+VOID
+InitItk();
+
+VOID
+InitPlatformBootMode();
+
+VOID
+InitMfgAndConfigModeStateVar();
+
+VOID
+InitPchPlatformPolicy (
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfo
+ );
+
+VOID
+InitVlvPlatformPolicy (
+ );
+
+VOID
+InitSioPlatformPolicy(
+ );
+
+VOID
+PchInitBeforeBoot(
+ );
+
+VOID
+UpdateDVMTSetup(
+ );
+
+VOID
+InitPlatformUsbPolicy (
+ VOID
+ );
+
+VOID
+InitRC6Policy(
+ VOID
+ );
+
+
+VOID
+TristateLpcGpioConfig (
+ IN UINT32 Gpio_Mmio_Offset,
+ IN UINT32 Gpio_Pin_Num,
+ GPIO_CONF_PAD_INIT* Gpio_Conf_Data
+ )
+
+{
+ UINT32 index;
+ UINT32 mmio_conf0;
+ UINT32 mmio_padval;
+ PAD_CONF0 conf0_val;
+ PAD_VAL pad_val;
+
+ //
+ // GPIO WELL -- Memory base registers
+ //
+
+ //
+ // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
+ // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
+ //
+
+ for(index=0; index < Gpio_Pin_Num; index++)
+ {
+ //
+ // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
+ //
+ mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
+ mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
+
+#ifdef EFI_DEBUG
+ DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
+
+#endif
+ DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
+ Gpio_Conf_Data[index].usage,
+ Gpio_Conf_Data[index].func,
+ Gpio_Conf_Data[index].int_type,
+ Gpio_Conf_Data[index].pull,
+ mmio_conf0));
+
+ //
+ // Step 1: PadVal Programming
+ //
+ pad_val.dw = MmioRead32(mmio_padval);
+
+ //
+ // Config PAD_VAL only for GPIO (Non-Native) Pin
+ //
+ if(Native != Gpio_Conf_Data[index].usage)
+ {
+ pad_val.dw &= ~0x6; // Clear bits 1:2
+ pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
+
+ //
+ // set GPO default value
+ //
+ if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
+ {
+ pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
+ }
+ }
+
+
+ DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
+
+ MmioWrite32(mmio_padval, pad_val.dw);
+
+ //
+ // Step 2: CONF0 Programming
+ // Read GPIO default CONF0 value, which is assumed to be default value after reset.
+ //
+ conf0_val.dw = MmioRead32(mmio_conf0);
+
+ //
+ // Set Function #
+ //
+ conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
+
+ if(GPO == Gpio_Conf_Data[index].usage)
+ {
+ //
+ // If used as GPO, then internal pull need to be disabled
+ //
+ conf0_val.r.Pull_assign = 0; // Non-pull
+ }
+ else
+ {
+ //
+ // Set PullUp / PullDown
+ //
+ if(P_20K_H == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x1; // PullUp
+ conf0_val.r.Pull_strength = 0x2;// 20K
+ }
+ else if(P_20K_L == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0x2; // PullDown
+ conf0_val.r.Pull_strength = 0x2;// 20K
+ }
+ else if(P_NONE == Gpio_Conf_Data[index].pull)
+ {
+ conf0_val.r.Pull_assign = 0; // Non-pull
+ }
+ else
+ {
+ ASSERT(FALSE); // Invalid value
+ }
+ }
+
+ //
+ // Set INT Trigger Type
+ //
+ conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
+
+ //
+ // Set INT Trigger Type
+ //
+ if(TRIG_ == Gpio_Conf_Data[index].int_type)
+ {
+ //
+ // Interrupt not capable, clear bits 27:24
+ //
+ }
+ else
+ {
+ conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
+ }
+
+ DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
+
+ //
+ // Write back the targeted GPIO config value according to platform (board) GPIO setting
+ //
+ MmioWrite32 (mmio_conf0, conf0_val.dw);
+ }
+
+ // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
+ // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
+ //
+}
+
+VOID
+EFIAPI
+SpiBiosProtectionFunction(
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+
+ UINTN mPciD31F0RegBase;
+ UINTN BiosFlaLower = 0;
+ UINTN BiosFlaLimit = 0x7fffff;
+
+ BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
+
+
+ mPciD31F0RegBase = MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
+
+ //
+ //Set SMM_BWP, WPD and LE bit
+ //
+ MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
+ MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
+ MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
+
+ //
+ //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
+ //
+ if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
+ (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
+ //
+ //Already locked. we could take no action here
+ //
+ DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
+ return;
+ }
+
+ //
+ //Set PR0
+ //
+ MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
+ B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
+ (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));
+
+ //
+ //Lock down PR0
+ //
+ MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
+
+ //
+ // Verify if it's really locked.
+ //
+ if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
+ DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
+ }
+
+ return;
+
+}
+
+VOID
+EFIAPI
+InitPciDevPME (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ UINTN VarSize;
+ EFI_STATUS Status;
+
+ VarSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = gRT->GetVariable(
+ NORMAL_SETUP_NAME,
+ &gEfiNormalSetupGuid,
+ NULL,
+ &VarSize,
+ &mSystemConfiguration
+ );
+
+ //
+ //Program HDA PME_EN
+ //
+ PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
+
+ //
+ //Program SATA PME_EN
+ //
+ PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
+
+ DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
+ if (mSystemConfiguration.EhciPllCfgEnable != 1) {
+ //
+ //Program EHCI PME_EN
+ //
+ PchMmPci32Or (
+ 0,
+ 0,
+ PCI_DEVICE_NUMBER_PCH_USB,
+ PCI_FUNCTION_NUMBER_PCH_EHCI,
+ R_PCH_EHCI_PWR_CNTL_STS,
+ B_PCH_EHCI_PWR_CNTL_STS_PME_EN
+ );
+ }
+ {
+ UINTN EhciPciMmBase;
+ UINT32 Buffer32 = 0;
+
+ EhciPciMmBase = MmPciAddress (0,
+ 0,
+ PCI_DEVICE_NUMBER_PCH_USB,
+ PCI_FUNCTION_NUMBER_PCH_EHCI,
+ 0
+ );
+ DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
+ Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
+ DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
+ }
+}
+
+#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
+
+#endif
+
+
+EFI_STATUS
+EFIAPI
+TristateLpcGpioS0i3Config (
+ UINT32 Gpio_Mmio_Offset,
+ UINT32 Gpio_Pin_Num,
+ CFIO_PNP_INIT* Gpio_Conf_Data
+ )
+{
+
+ UINT32 index;
+ UINT32 mmio_reg;
+ UINT32 mmio_val;
+
+ DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
+
+ for(index=0; index < Gpio_Pin_Num; index++)
+ {
+ mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
+
+ MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
+ mmio_val = 0;
+ mmio_val = MmioRead32(mmio_reg);
+
+ DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
+
+/**
+ Event Notification during exit boot service to enabel ACPI mode
+
+ Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
+
+ Clear all ACPI event status and disable all ACPI events
+ Disable PM sources except power button
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
+
+ Update EC to disable SMI and enable SCI
+
+ Enable SCI
+
+ Enable PME_B0_EN in GPE0a_EN
+
+ @param Event - EFI Event Handle
+ @param Context - Pointer to Notify Context
+
+ @retval Nothing
+
+**/
+VOID
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINT32 RegData32;
+ UINT16 Pm1Cnt;
+ UINT16 AcpiBase;
+ UINT32 Gpe0aEn;
+
+ AcpiBase = MmioRead16 (
+ PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
+ ) & B_PCH_LPC_ACPI_BASE_BAR;
+
+ DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
+
+ //
+ // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
+ //
+ RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
+ RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
+ IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
+
+ RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
+ RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
+ IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
+
+ //
+ // Disable PM sources except power button
+ // power button is enabled only for PCAT. Disabled it on Tablet platform
+ //
+
+ IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
+ IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
+ // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
+ //
+ IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
+ IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
+
+ RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
+ RegData32 &= ~(BIT7);
+ IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
+
+ //
+ // Enable SCI
+ //
+ Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
+ Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
+ IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+
+ IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
+
+ //
+ // Enable PME_B0_EN in GPE0a_EN
+ // Caution: Enable PME_B0_EN must be placed after enabling SCI.
+ // Otherwise, USB PME could not be handled as SMI event since no handler is there.
+ //
+ Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
+ Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
+ IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
+
+}
+
+/**
+
+ Routine Description:
+
+ This is the standard EFI driver point for the Driver. This
+ driver is responsible for setting up any platform specific policy or
+ initialization information.
+
+ @param ImageHandle Handle for the image of this driver.
+ @param SystemTable Pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS Policy decisions set.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN VarSize;
+ EFI_HANDLE Handle = NULL;
+
+ EFI_EVENT mEfiExitBootServicesEvent;
+
+ //
+mImageHandle = ImageHandle;
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiSpeakerInterfaceProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mSpeakerInterface
+ );
+
+ Status = gBS->LocateProtocol (
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ (VOID **) &mPciRootBridgeIo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
+ Status = gRT->GetVariable(
+ L"PlatformInfo",
+ &gEfiVlv2VariableGuid,
+ NULL,
+ &VarSize,
+ &mPlatformInfo
+ );
+
+ //
+ // Initialize Product Board ID variable
+ //
+ InitMfgAndConfigModeStateVar();
+ InitPlatformBootMode();
+
+ //
+ // Install Observable protocol
+ //
+ InitializeObservableProtocol();
+
+
+ VarSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = gRT->GetVariable(
+ NORMAL_SETUP_NAME,
+ &gEfiNormalSetupGuid,
+ NULL,
+ &VarSize,
+ &mSystemConfiguration
+ );
+
+
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ ReadyToBootFunction,
+ NULL,
+ &mReadyToBootEvent
+ );
+
+ //
+ // Create a ReadyToBoot Event to run the PME init process
+ //
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ InitPciDevPME,
+ NULL,
+ &mReadyToBootEvent
+ );
+ //
+ // Create a ReadyToBoot Event to run enable PR0 and lock down
+ //
+ if(mSystemConfiguration.SpiRwProtect==1) {
+ Status = EfiCreateEventReadyToBootEx (
+ TPL_CALLBACK,
+ SpiBiosProtectionFunction,
+ NULL,
+ &mReadyToBootEvent
+ );
+ }
+
+ ReportStatusCodeEx (
+ EFI_PROGRESS_CODE,
+ EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
+ 0,
+ &gEfiCallerIdGuid,
+ NULL,
+ NULL,
+ 0
+ );
+
+#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
+ //
+ // Initialize Sensor Info variable
+ //
+ InitializeSensorInfoVariable();
+#endif
+ InitPchPlatformPolicy(&mPlatformInfo);
+ InitVlvPlatformPolicy();
+
+ //
+ // Add usb policy
+ //
+ InitPlatformUsbPolicy();
+ InitSioPlatformPolicy();
+ InitializeClockRouting();
+ InitializeSlotInfo();
+ InitTcoReset();
+
+ //
+ //Init ExI
+ //
+ InitExI();
+
+ ReportStatusCodeEx (
+ EFI_PROGRESS_CODE,
+ EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
+ 0,
+ &gEfiCallerIdGuid,
+ NULL,
+ NULL,
+ 0
+ );
+
+ //
+ // Install PCI Bus Driver Hook
+ //
+ PciBusDriverHook();
+
+ InitItk();
+
+ ReportStatusCodeEx (
+ EFI_PROGRESS_CODE,
+ EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
+ 0,
+ &gEfiCallerIdGuid,
+ NULL,
+ NULL,
+ 0
+ );
+
+
+ //
+ // Initialize Password States and Callbacks
+ //
+ PchInitBeforeBoot();
+
+#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
+
+#endif
+
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
+ //
+ // Re-write Firmware ID if it is changed
+ //
+ InitFirmwareId();
+#endif
+
+ ReportStatusCodeEx (
+ EFI_PROGRESS_CODE,
+ EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
+ 0,
+ &gEfiCallerIdGuid,
+ NULL,
+ NULL,
+ 0
+ );
+
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ EnableAcpiCallback,
+ NULL,
+ &gEfiEventExitBootServicesGuid,
+ &mEfiExitBootServicesEvent
+ );
+
+
+//
+// Tristae Lpc pins at last moment
+//
+if (mSystemConfiguration.TristateLpc == 1)
+{
+}
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Source Or Destination with Length bytes.
+
+ @param[in] Destination Target memory
+ @param[in] Source Source memory
+ @param[in] Length Number of bytes
+
+ @retval None
+
+**/
+VOID
+EfiOrMem (
+ IN VOID *Destination,
+ IN VOID *Source,
+ IN UINTN Length
+ )
+{
+ CHAR8 *Destination8;
+ CHAR8 *Source8;
+
+ if (Source < Destination) {
+ Destination8 = (CHAR8 *) Destination + Length - 1;
+ Source8 = (CHAR8 *) Source + Length - 1;
+ while (Length--) {
+ *(Destination8--) |= *(Source8--);
+ }
+ } else {
+ Destination8 = (CHAR8 *) Destination;
+ Source8 = (CHAR8 *) Source;
+ while (Length--) {
+ *(Destination8++) |= *(Source8++);
+ }
+ }
+}
+
+VOID
+PchInitBeforeBoot()
+{
+ //
+ // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
+ //
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
+ 1,
+ (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
+ 1,
+ (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint16,
+ (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
+ 1,
+ (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
+
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint16,
+ (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
+ 1,
+ (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
+
+ //
+ // Saved MTPMC_1 for S3 resume.
+ //
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint32,
+ (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
+ 1,
+ (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
+ return;
+}
+
+VOID
+EFIAPI
+ReadyToBootFunction (
+ EFI_EVENT Event,
+ VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
+ EFI_ISA_ACPI_DEVICE_ID IsaDevice;
+ UINTN Size;
+ UINT16 State;
+ EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
+ EFI_CPU_IO_PROTOCOL *CpuIo;
+ UINT8 Data;
+ UINT8 ReceiveBuffer [64];
+ UINT32 ReceiveBufferSize;
+
+ UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0A,
+ 0x00, 0x00, 0x00, 0x5D};
+ UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0C,
+ 0x40, 0x00, 0x00, 0x0A,
+ 0x00, 0x00};
+ UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0A,
+ 0x00, 0x00, 0x00, 0x70};
+ UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0A,
+ 0x00, 0x00, 0x00, 0x6F};
+ UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0B,
+ 0x00, 0x00, 0x00, 0x72,
+ 0x00};
+ UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
+ 0x00, 0x00, 0x00, 0x0B,
+ 0x00, 0x00, 0x00, 0x71,
+ 0x00};
+
+ Size = sizeof(UINT16);
+ Status = gRT->GetVariable (
+ VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
+ &gEfiNormalSetupGuid,
+ NULL,
+ &Size,
+ &State
+ );
+
+ //
+ // Disable Floppy Controller if needed
+ //
+ Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
+ if (!EFI_ERROR(Status) && (State == 0x00)) {
+ IsaDevice.HID = EISA_PNP_ID(0x604);
+ IsaDevice.UID = 0;
+ Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
+ }
+
+ //
+ // save LAN info to a variable
+ //
+ if (NULL != mPciLanInfo) {
+ gRT->SetVariable (
+ L"PciLanInfo",
+ &gEfiPciLanInfoGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ mPciLanCount * sizeof(PCI_LAN_INFO),
+ mPciLanInfo
+ );
+ }
+
+ if (NULL != mPciLanInfo) {
+ gBS->FreePool (mPciLanInfo);
+ mPciLanInfo = NULL;
+ }
+
+
+ //
+ // Handle ACPI OS TPM requests here
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiCpuIoProtocolGuid,
+ NULL,
+ (VOID **)&CpuIo
+ );
+ Status = gBS->LocateProtocol (
+ &gEfiTpmMpDriverProtocolGuid,
+ NULL,
+ (VOID **)&TpmMpDriver
+ );
+ if (!EFI_ERROR (Status))
+ {
+ Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
+
+ //
+ // Clear pending ACPI TPM request indicator
+ //
+ WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
+ if (Data != 0)
+ {
+ WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
+
+ //
+ // Assert Physical Presence for these commands
+ //
+ TpmPhysicalPresenceCommand [11] = 0x20;
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver, TpmPhysicalPresenceCommand,
+ sizeof (TpmPhysicalPresenceCommand),
+ ReceiveBuffer, &ReceiveBufferSize
+ );
+ //
+ // PF PhysicalPresence = TRUE
+ //
+ TpmPhysicalPresenceCommand [11] = 0x08;
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver, TpmPhysicalPresenceCommand,
+ sizeof (TpmPhysicalPresenceCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ if (Data == 0x01)
+ {
+ //
+ // TPM_PhysicalEnable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver, TpmPhysicalEnableCommand,
+ sizeof (TpmPhysicalEnableCommand),
+ ReceiveBuffer, &ReceiveBufferSize
+ );
+ }
+ if (Data == 0x02)
+ {
+ //
+ // TPM_PhysicalDisable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver, TpmPhysicalDisableCommand,
+ sizeof (TpmPhysicalDisableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ }
+ if (Data == 0x03)
+ {
+ //
+ // TPM_PhysicalSetDeactivated=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer, &ReceiveBufferSize
+ );
+ gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
+ }
+ if (Data == 0x04)
+ {
+ //
+ // TPM_PhysicalSetDeactivated=TRUE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x01;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x05)
+ {
+ //
+ // TPM_ForceClear
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmForceClearCommand,
+ sizeof (TpmForceClearCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x06)
+ {
+ //
+ // TPM_PhysicalEnable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalEnableCommand,
+ sizeof (TpmPhysicalEnableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalSetDeactivated=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x07)
+ {
+ //
+ // TPM_PhysicalSetDeactivated=TRUE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x01;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalDisable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalDisableCommand,
+ sizeof (TpmPhysicalDisableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x08)
+ {
+ //
+ // TPM_SetOwnerInstall=TRUE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmSetOwnerInstallCommand [10] = 0x01;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmSetOwnerInstallCommand,
+ sizeof (TpmSetOwnerInstallCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ }
+ if (Data == 0x09)
+ {
+ //
+ // TPM_SetOwnerInstall=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmSetOwnerInstallCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmSetOwnerInstallCommand,
+ sizeof (TpmSetOwnerInstallCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ }
+ if (Data == 0x0A)
+ {
+ //
+ // TPM_PhysicalEnable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalEnableCommand,
+ sizeof (TpmPhysicalEnableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalSetDeactivated=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // Do TPM_SetOwnerInstall=TRUE on next reboot
+ //
+
+ WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
+
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x0B)
+ {
+ //
+ // TPM_SetOwnerInstall=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmSetOwnerInstallCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmSetOwnerInstallCommand,
+ sizeof (TpmSetOwnerInstallCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalSetDeactivated=TRUE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x01;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalDisable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalDisableCommand,
+ sizeof (TpmPhysicalDisableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0x0E)
+ {
+ //
+ // TPM_ForceClear
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmForceClearCommand,
+ sizeof (TpmForceClearCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalEnable
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalEnableCommand,
+ sizeof (TpmPhysicalEnableCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ //
+ // TPM_PhysicalSetDeactivated=FALSE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmPhysicalSetDeactivatedCommand [10] = 0x00;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalSetDeactivatedCommand,
+ sizeof (TpmPhysicalSetDeactivatedCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ gRT->ResetSystem (
+ EfiResetWarm,
+ EFI_SUCCESS,
+ 0,
+ NULL
+ );
+ }
+ if (Data == 0xF0)
+ {
+ //
+ // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
+ //
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ TpmSetOwnerInstallCommand [10] = 0x01;
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmSetOwnerInstallCommand,
+ sizeof (TpmSetOwnerInstallCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
+ }
+ //
+ // Deassert Physical Presence
+ //
+ TpmPhysicalPresenceCommand [11] = 0x10;
+ ReceiveBufferSize = sizeof(ReceiveBuffer);
+ Status = TpmMpDriver->Transmit (
+ TpmMpDriver,
+ TpmPhysicalPresenceCommand,
+ sizeof (TpmPhysicalPresenceCommand),
+ ReceiveBuffer,
+ &ReceiveBufferSize
+ );
+ }
+ }
+
+ return;
+}
+
+/**
+
+ Initializes manufacturing and config mode setting.
+
+**/
+VOID
+InitMfgAndConfigModeStateVar()
+{
+ EFI_PLATFORM_SETUP_ID *BootModeBuffer;
+ VOID *HobList;
+ UINT16 State;
+
+ //
+ // Variable initialization
+ //
+ State = FALSE;
+
+ HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
+ if (HobList != NULL) {
+ BootModeBuffer = GET_GUID_HOB_DATA (HobList);
+
+ //
+ // Check if in Manufacturing mode
+ //
+ if ( !CompareMem (
+ &BootModeBuffer->SetupName,
+ MANUFACTURE_SETUP_NAME,
+ StrSize (MANUFACTURE_SETUP_NAME)
+ ) ) {
+ mMfgMode = TRUE;
+ }
+
+ //
+ // Check if in safe mode
+ //
+ if ( !CompareMem (
+ &BootModeBuffer->SetupName,
+ SAFE_SETUP_NAME,
+ StrSize (SAFE_SETUP_NAME)
+ ) ) {
+ State = TRUE;
+ }
+ }
+
+}
+
+/**
+
+ Initializes manufacturing and config mode setting.
+
+**/
+VOID
+InitPlatformBootMode()
+{
+ EFI_PLATFORM_SETUP_ID *BootModeBuffer;
+ VOID *HobList;
+
+ HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
+ if (HobList != NULL) {
+ BootModeBuffer = GET_GUID_HOB_DATA (HobList);
+ mPlatformBootMode = BootModeBuffer->PlatformBootMode;
+ }
+}
+
+/**
+
+ Initializes ITK.
+
+**/
+VOID
+InitItk(
+ )
+{
+ EFI_STATUS Status;
+ UINT16 ItkModBiosState;
+ UINT8 Value;
+ UINTN DataSize;
+ UINT32 Attributes;
+
+ //
+ // Setup local variable according to ITK variable
+ //
+ //
+ // Read ItkBiosModVar to determine if BIOS has been modified by ITK
+ // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
+ // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
+ //
+ DataSize = sizeof (Value);
+ Status = gRT->GetVariable (
+ ITK_BIOS_MOD_VAR_NAME,
+ &gItkDataVarGuid,
+ &Attributes,
+ &DataSize,
+ &Value
+ );
+ if (Status == EFI_NOT_FOUND) {
+ //
+ // Variable not found, hasn't been initialized, intialize to 0
+ //
+ Value=0x00;
+ //
+ // Write variable to flash.
+ //
+ gRT->SetVariable (
+ ITK_BIOS_MOD_VAR_NAME,
+ &gItkDataVarGuid,
+ EFI_VARIABLE_RUNTIME_ACCESS |
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (Value),
+ &Value
+ );
+
+}
+ if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
+ if (Value == 0x00) {
+ ItkModBiosState = 0x00;
+ } else {
+ ItkModBiosState = 0x01;
+ }
+ gRT->SetVariable (
+ VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
+ &gEfiNormalSetupGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ 2,
+ (void *)&ItkModBiosState
+ );
+ }
+}
+
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
+
+/**
+
+ Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
+
+**/
+STATIC
+VOID
+InitFirmwareId(
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
+
+ //
+ // First try writing the variable without a password in case we are
+ // upgrading from a BIOS without password protection on the FirmwareId
+ //
+ Status = gRT->SetVariable(
+ (CHAR16 *)&gFirmwareIdName,
+ &gFirmwareIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof( FIRMWARE_ID ) - 1,
+ FIRMWARE_ID
+ );
+
+ if (Status == EFI_INVALID_PARAMETER) {
+
+ //
+ // Since setting the firmware id without the password failed,
+ // a password must be required.
+ //
+ Status = gRT->SetVariable(
+ (CHAR16 *)&FirmwareIdNameWithPassword,
+ &gFirmwareIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof( FIRMWARE_ID ) - 1,
+ FIRMWARE_ID
+ );
+ }
+}
+#endif
+
+VOID
+UpdateDVMTSetup(
+ )
+{
+ //
+ // Workaround to support IIA bug.
+ // IIA request to change option value to 4, 5 and 7 relatively
+ // instead of 1, 2, and 3 which follow Lakeport Specs.
+ // Check option value, temporary hardcode GraphicsDriverMemorySize
+ // Option value to fulfill IIA requirment. So that user no need to
+ // load default and update setupvariable after update BIOS.
+ // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
+ // *This is for broadwater and above product only.
+ //
+
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ UINTN VarSize;
+ EFI_STATUS Status;
+
+ VarSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = gRT->GetVariable(
+ NORMAL_SETUP_NAME,
+ &gEfiNormalSetupGuid,
+ NULL,
+ &VarSize,
+ &SystemConfiguration
+ );
+
+ if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
+ switch (SystemConfiguration.GraphicsDriverMemorySize){
+ case 1:
+ SystemConfiguration.GraphicsDriverMemorySize = 4;
+ break;
+ case 2:
+ SystemConfiguration.GraphicsDriverMemorySize = 5;
+ break;
+ case 3:
+ SystemConfiguration.GraphicsDriverMemorySize = 7;
+ break;
+ default:
+ break;
+ }
+
+ Status = gRT->SetVariable (
+ NORMAL_SETUP_NAME,
+ &gEfiNormalSetupGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof(SYSTEM_CONFIGURATION),
+ &SystemConfiguration
+ );
+ }
+}
+
+VOID
+InitPlatformUsbPolicy (
+ VOID
+ )
+
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+
+ mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
+ mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
+ if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
+ mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
+ } else {
+ mUsbPolicyData.UsbEmulationSize = 0;
+ }
+ mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
+ mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
+
+ //
+ // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
+ //
+ mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
+
+ //
+ // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
+ //
+ mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
+
+ //
+ // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
+ //
+ mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
+
+ //
+ // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
+ // default is Ich acpibase =0x040. acpitimerreg=0x08.
+ mUsbPolicyData.LpcAcpiBase = 0x40;
+ mUsbPolicyData.AcpiTimerReg = 0x08;
+
+ //
+ // Set for reduce usb post time
+ //
+ mUsbPolicyData.UsbTimeTue = 0x00;
+ mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
+ mUsbPolicyData.EnumWaitPortStableStall = 100;
+
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gUsbPolicyGuid,
+ EFI_NATIVE_INTERFACE,
+ &mUsbPolicyData
+ );
+ ASSERT_EFI_ERROR(Status);
+
+}
+
+UINT8
+ReadCmosBank1Byte (
+ IN EFI_CPU_IO_PROTOCOL *CpuIo,
+ IN UINT8 Index
+ )
+{
+ UINT8 Data;
+
+ CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
+ CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
+ return Data;
+}
+
+VOID
+WriteCmosBank1Byte (
+ IN EFI_CPU_IO_PROTOCOL *CpuIo,
+ IN UINT8 Index,
+ IN UINT8 Data
+ )
+{
+ CpuIo->Io.Write (
+ CpuIo,
+ EfiCpuIoWidthUint8,
+ 0x72,
+ 1,
+ &Index
+ );
+ CpuIo->Io.Write (
+ CpuIo,
+ EfiCpuIoWidthUint8,
+ 0x73,
+ 1,
+ &Data
+ );
+}
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h new file mode 100644 index 0000000000..42197cab18 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h @@ -0,0 +1,719 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ PlatformDxe.h
+
+Abstract:
+
+ Header file for Platform Initialization Driver.
+
+
+
+++*/
+
+#ifndef _PLATFORM_DRIVER_H
+#define _PLATFORM_DRIVER_H
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/HobLib.h>
+#include <Library/EfiRegTableLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <Library/Tpm2DeviceLib.h>
+#include <Library/BaseCryptLib.h>
+#include <Protocol/GlobalNvsArea.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/IsaAcpi.h>
+#include <Framework/FrameworkInternalFormRepresentation.h>
+#include <Protocol/FrameworkHii.h>
+#include <Protocol/FrameworkFormCallback.h>
+#include <Protocol/CpuIo.h>
+#include <Protocol/BootScriptSave.h>
+#include <Framework/BootScript.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/BoardFeatures.h>
+#include <Guid/DataHubRecords.h>
+#include <Protocol/DataHub.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/Speaker.h>
+#include <IndustryStandard/Pci22.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PlatformInfo.h>
+#include "Configuration.h"
+#define _EFI_H_ //skip efi.h
+#include "PchAccess.h"
+#include "VlvAccess.h"
+#include "BoardIdDecode.h"
+#include "PlatformBaseAddresses.h"
+#include "SetupMode.h"
+#include "PlatformBootMode.h"
+#include "CpuType.h"
+
+#define PCAT_RTC_ADDRESS_REGISTER 0x74
+#define PCAT_RTC_DATA_REGISTER 0x75
+
+#define RTC_ADDRESS_SECOND_ALARM 0x01
+#define RTC_ADDRESS_MINUTE_ALARM 0x03
+#define RTC_ADDRESS_HOUR_ALARM 0x05
+
+#define RTC_ADDRESS_REGISTER_A 0x0A
+#define RTC_ADDRESS_REGISTER_B 0x0B
+#define RTC_ADDRESS_REGISTER_C 0x0C
+#define RTC_ADDRESS_REGISTER_D 0x0D
+
+#define B_RTC_ALARM_INT_ENABLE 0x20
+#define B_RTC_ALARM_INT_STATUS 0x20
+
+#define B_RTC_DATE_ALARM_MASK 0x3F
+
+//
+// Default CPU Alternate Duty Cycle (255=100%, 0=0%)
+//
+#define DEF_CPU_ALT_DUTY_CYCLE 0xFF
+
+#define MAX_ONBOARD_SATA_DEVICE 2
+
+#define DXE_DEVICE_ENABLED 1
+#define DXE_DEVICE_DISABLED 0
+
+#define AZALIA_MAX_LOOP_TIME 0x10000
+
+//
+// Platform driver GUID
+//
+#define EFI_PLATFORM_DRIVER_GUID \
+ { 0x056E7324, 0xA718, 0x465b, 0x9A, 0x84, 0x22, 0x8F, 0x06, 0x64, 0x2B, 0x4F }
+
+#define PASSWORD_MAX_SIZE 20
+#define PLATFORM_NORMAL_MODE 0x01
+#define PLATFORM_SAFE_MODE 0x02
+#define PLATFORM_RECOVERY_MODE 0x04
+#define PLATFORM_MANUFACTURING_MODE 0x08
+#define PLATFORM_BACK_TO_BIOS_MODE 0x10
+
+#define EFI_OEM_SPECIFIC 0x8000
+#define EFI_CU_PLATFORM_DXE_INIT (EFI_OEM_SPECIFIC | 0x00000011)
+#define EFI_CU_PLATFORM_DXE_STEP1 (EFI_OEM_SPECIFIC | 0x00000012)
+#define EFI_CU_PLATFORM_DXE_STEP2 (EFI_OEM_SPECIFIC | 0x00000013)
+#define EFI_CU_PLATFORM_DXE_STEP3 (EFI_OEM_SPECIFIC | 0x00000014)
+#define EFI_CU_PLATFORM_DXE_STEP4 (EFI_OEM_SPECIFIC | 0x00000015)
+#define EFI_CU_PLATFORM_DXE_INIT_DONE (EFI_OEM_SPECIFIC | 0x00000016)
+
+
+#define EFI_SECTION_STRING 0x1C
+#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+#define PREFIX_BLANK 0x04
+
+#pragma pack(1)
+
+typedef UINT64 EFI_BOARD_FEATURES;
+
+//
+//BUGBUG: should remove these EDK hii definition once Hii transtion is done
+//
+typedef UINT16 STRING_REF;
+typedef UINT16 EFI_FORM_LABEL;
+
+typedef enum {
+ EfiUserPassword,
+ EfiAdminPassword
+} EFI_PASSWORD_TYPE;
+
+typedef struct {
+ CHAR16 TempPassword[PASSWORD_MAX_SIZE];
+ CHAR16 EncodedPassword[PASSWORD_MAX_SIZE];
+ VOID *PasswordLocation;
+ EFI_PASSWORD_TYPE PasswordType;
+} EFI_PASSWORD_DATA;
+
+typedef struct {
+ CHAR8 AaNumber[7];
+ UINT8 BoardId;
+ EFI_BOARD_FEATURES Features;
+ UINT16 SubsystemDeviceId;
+ UINT16 AudioSubsystemDeviceId;
+ UINT64 AcpiOemTableId;
+} BOARD_ID_DECODE;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_FORM_ROUTINE) (
+ SYSTEM_CONFIGURATION *SetupBuffer
+ );
+
+typedef struct{
+ UINT16 DeviceNumber;
+ UINT16 FunctionNumber;
+}PCI_DEVICE_FUNC_INFO;
+
+typedef struct{
+ CHAR16 PortNumber[4];
+ STRING_REF SataDeviceInfoStringId;
+}SATA_DEVICE_STRING_INFO;
+
+typedef struct {
+ UINT16 Signature;
+ UINT8 Size;
+ UINT32 EntryPoint;
+ UINT8 Reserve[17];
+ UINT16 PciDataOff;
+ UINT16 ExpansionOff;
+} PNP_OPTION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature;
+ UINT8 Revision;
+ UINT8 Length;
+ UINT16 NextHeader;
+ UINT8 Reserve;
+ UINT8 CheckSum;
+ UINT32 DeviceId;
+ UINT16 ManufactureStrOff;
+ UINT16 ProductStrOff;
+} PNP_EXPANSION_HEADER;
+
+typedef struct {
+ BOOLEAN Enable;
+ UINT8 VerbTableNum;
+ UINT16 CodecSSID;
+ EFI_PHYSICAL_ADDRESS HDABar;
+ EFI_PHYSICAL_ADDRESS UpperHDABar;
+ UINT8 SDIPresent;
+ BOOLEAN Pme;
+ BOOLEAN LegacyFrontPanelAudio;
+ BOOLEAN HighDefinitionFrontPanelAudio;
+} EFI_AZALIA_S3;
+
+//
+//following structs are from R8. Remove them once R8->R9 transition is done
+//
+typedef struct {
+ CHAR16 *OptionString; // Passed in string to generate a token for in a truly dynamic form creation
+ STRING_REF StringToken; // This is used when creating a single op-code without generating a StringToken (have one already)
+ UINT16 Value;
+ UINT8 Flags;
+ UINT16 Key;
+} IFR_OPTION;
+
+
+
+typedef struct {
+ UINT8 Number;
+ UINT32 HorizontalResolution;
+ UINT32 VerticalResolution;
+} PANEL_RESOLUTION;
+
+#pragma pack()
+
+//
+// Prototypes
+//
+EFI_STATUS
+EFIAPI
+EfiMain (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+EFI_STATUS
+ProcessEventLog (
+ );
+
+EFI_STATUS
+FindDataRecords (
+ );
+
+EFI_STATUS
+ProcessPasswords(
+ );
+
+VOID
+MemorySetup(
+ );
+
+
+UINTN
+EfiValueToString (
+ IN OUT CHAR16 *Buffer,
+ IN INT64 Value,
+ IN UINTN Flags,
+ IN UINTN Width
+ );
+
+VOID
+EFIAPI
+ReadyToBootFunction (
+ EFI_EVENT Event,
+ VOID *Context
+ );
+
+VOID
+InstallHiiDataAndGetSettings(
+ IN EFI_HII_STRING_PACK *StringPack,
+ //
+ ... // 0 or more of => IN EFI_HII_IFR_PACK *IfrPack,
+ // Terminate list with NULL
+ //
+ );
+
+EFI_STATUS
+ReadOrInitSetupVariable(
+ IN UINTN RequiredVariableSize,
+ IN UINTN RequiredPasswordSize,
+ IN VOID *DefaultData,
+ IN VOID *MfgDefaultData,
+ OUT VOID *SetupVariableData,
+ OUT VOID *SystemPassword
+ );
+
+VOID
+EfiLogicalOrMem(
+ IN VOID *Destination,
+ IN VOID *Source,
+ IN UINTN Length
+ );
+
+EFI_STATUS
+GetStringFromToken (
+ IN EFI_GUID *ProducerGuid,
+ IN STRING_REF Token,
+ OUT CHAR16 **String
+ );
+
+UINT32
+ConvertBase2ToRaw (
+ IN EFI_EXP_BASE2_DATA *Data);
+
+UINT32
+ConvertBase10ToRaw (
+ IN EFI_EXP_BASE10_DATA *Data);
+
+CHAR16 *
+GetStringById (
+ IN STRING_REF Id,
+ EFI_HII_HANDLE StringPackHandle
+ );
+
+VOID
+EFIAPI
+SetupDataFilter (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+
+VOID
+EFIAPI
+IdeDataFilter (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+
+VOID
+EFIAPI
+UpdateAhciRaidDiskInfo (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+
+VOID
+EFIAPI
+EventLogFilter (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+
+VOID
+SwapEntries (
+ IN CHAR8 *Data
+ );
+
+VOID
+AsciiToUnicode (
+ IN CHAR8 *AsciiString,
+ IN CHAR16 *UnicodeString
+ );
+
+UINT16
+ConfigModeStateGet();
+
+VOID
+SetSkus();
+
+VOID
+CPUSetupItems();
+
+EFI_STATUS
+SecurityDriverCallback (
+ IN EFI_FORM_CALLBACK_PROTOCOL *This,
+ IN UINT16 KeyValue,
+ IN EFI_IFR_DATA_ARRAY *Data,
+ OUT EFI_HII_CALLBACK_PACKET **Packet
+ );
+
+VOID
+SetPasswordState (
+ );
+
+VOID
+EncodePassword (
+ IN CHAR16 *Password
+ );
+
+VOID
+EFIAPI
+PciBusEvent (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ );
+VOID
+AsfInitialize(
+ );
+
+VOID
+InitializeAsf (
+ );
+
+UINT8
+ReadCmosBank1Byte (
+ IN EFI_CPU_IO_PROTOCOL *CpuIo,
+ IN UINT8 Index
+ );
+
+VOID
+WriteCmosBank1Byte (
+ IN EFI_CPU_IO_PROTOCOL *CpuIo,
+ IN UINT8 Index,
+ IN UINT8 Data
+ );
+
+VOID
+InitializeBoardId (
+ );
+
+EFI_STATUS
+InstallBootCallbackRoutine(
+ );
+
+EFI_STATUS
+InstallConfigurationCallbackRoutine(
+ );
+
+EFI_STATUS
+InstallPerformanceCallbackRoutine(
+ );
+
+EFI_STATUS
+InstallSecurityCallbackRoutine (
+ );
+
+EFI_STATUS
+InstallMainCallbackRoutine (
+ );
+
+EFI_STATUS
+MemoryConfigurationUpdate (
+ UINT16 *Key,
+ EFI_FORM_LABEL *Label,
+ UINT16 *OpcodeCount,
+ UINT8 **OpcodeData,
+ EFI_FORM_ROUTINE *Routine
+ );
+
+EFI_STATUS
+MemoryConfigurationCallbackRoutine (
+ SYSTEM_CONFIGURATION *SetupBuffer
+ );
+
+EFI_STATUS
+MemoryConfigurationCalculateSpeed(
+ SYSTEM_CONFIGURATION *SetupBuffer
+ );
+
+VOID
+UpdateMemoryString(
+ IN STRING_REF TokenToUpdate,
+ IN CHAR16 *NewString
+ );
+
+VOID
+InitFeaturePolicy (
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfo
+ );
+
+VOID
+InitializeSetupVarHide (
+ );
+
+VOID
+PreparePCIePCISlotInformation(
+ VOID
+ );
+
+
+EFI_STATUS
+BootConfigurationUpdate (
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+InitializeBootConfiguration(
+ VOID
+ );
+
+UINT16
+GetStringSize(
+ IN CHAR16 *ThisString
+ );
+
+UINT16
+GetDriveCount (
+ IN STRING_REF *BootMap
+ );
+
+CHAR16 *
+GetBootString (
+ IN STRING_REF Id,
+ OUT UINTN *Length
+ );
+
+EFI_STATUS
+BootCfgCreateTwoOptionOneOf(
+ IN UINT16 QuestionId,
+ IN EFI_FORM_LABEL Label,
+ IN STRING_REF OptionPrompt,
+ IN STRING_REF OptionHelp,
+ IN STRING_REF OptionOneString,
+ IN STRING_REF OptionTwoString,
+ IN UINT8 OptionOneFlags,
+ IN UINT8 OptionTwoFlags,
+ IN UINT16 KeyValueOne,
+ IN UINT16 KeyValueTwo
+ );
+
+EFI_STATUS
+ReplaceOpcodeWithText(
+ IN STRING_REF OptionPrompt,
+ IN STRING_REF OptionHelp,
+ IN STRING_REF OptionOneString,
+ IN EFI_FORM_LABEL Label
+ );
+
+EFI_STATUS
+CreateDriveBootOrderOpcode(
+ IN VOID *Data,
+ IN STRING_REF *BootMap,
+ IN EFI_FORM_LABEL Label,
+ IN UINT16 QuestionId,
+ IN STRING_REF OptionOneString,
+ IN STRING_REF OptionTwoString
+ );
+
+VOID
+SetHyperBootCfgFlags(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+VOID
+GetHyperBootCfgFlags(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+VOID
+PrepareBootCfgForHyperBoot(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+BOOLEAN
+BootCfgChanged(
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+InsertOpcodeAtIndex(
+ IN SYSTEM_CONFIGURATION *SystemConfiguration,
+ IN OUT IFR_OPTION *OptionList,
+ IN IFR_OPTION IfrOption,
+ IN UINT16 OptionCount
+ );
+
+VOID
+ConfigureBootOrderStrings(
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+VOID
+InitializeAllBootStrings(
+ VOID
+ );
+
+VOID
+SaveUsbCfgSettings(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+VOID
+RestoreUsbCfgSettings(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+UpdateBootDevicePriority(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+DisableHyperBoot(
+ IN OUT SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+BOOLEAN
+CheckForUserPassword(
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+HyperBootPasswordCallback(
+ IN OUT VOID* Data
+ );
+
+EFI_STATUS
+EFIAPI
+HyperBootF9Callback (
+ IN VOID* Data
+ );
+
+EFI_STATUS
+InstallHiiEvents(
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+ProgramToneFrequency (
+ IN EFI_SPEAKER_IF_PROTOCOL *This,
+ IN UINT16 Frequency
+ );
+
+EFI_STATUS
+EFIAPI
+GenerateBeepTone (
+ IN EFI_SPEAKER_IF_PROTOCOL *This,
+ IN UINTN NumberOfBeeps,
+ IN UINTN BeepDuration,
+ IN UINTN TimeInterval
+ );
+
+EFI_STATUS
+InitializeObservableProtocol();
+
+EFI_STATUS
+PciBusDriverHook();
+
+typedef struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL GOP_DISPLAY_BRIGHTNESS_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_MAXIMUM_BRIGHTNESS_LEVEL) (
+ IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
+ OUT UINT32 *MaxBrightnessLevel
+ );
+
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_CURRENT_BRIGHTNESS_LEVEL) (
+ IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
+ OUT UINT32 *MaxBrightnessLevel
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *SET_BRIGHTNESS_LEVEL) (
+ IN GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,
+ IN UINT32 BrightnessLevel
+ );
+
+struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL {
+ UINT32 Revision;
+ GET_MAXIMUM_BRIGHTNESS_LEVEL GetMaxBrightnessLevel;
+ GET_CURRENT_BRIGHTNESS_LEVEL GetCurrentBrightnessLevel;
+ SET_BRIGHTNESS_LEVEL SetBrightnessLevel;
+};
+
+//
+// Global externs
+//
+extern UINT8 MaintenanceBin[];
+extern UINT8 MainBin[];
+extern UINT8 ConfigurationBin[];
+extern UINT8 MemoryConfigurationBin[];
+extern UINT8 PerformanceBin[];
+extern UINT8 SecurityBin[];
+extern UINT8 BootBin[];
+extern UINT8 PowerBin[];
+extern UINT8 SystemSetupBin[];
+
+extern VOID *mDxePlatformStringPack;
+extern EFI_HII_PROTOCOL *mHii;
+extern SYSTEM_CONFIGURATION mSystemConfiguration;
+extern FRAMEWORK_EFI_HII_HANDLE mMaintenanceHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mMainHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mConfigurationHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mPerformanceHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mPowerHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mBootHiiHandle;
+extern FRAMEWORK_EFI_HII_HANDLE mSecurityHiiHandle;
+
+extern SYSTEM_PASSWORDS mSystemPassword;
+extern EFI_PASSWORD_DATA mAdminPassword;
+extern EFI_PASSWORD_DATA mUserPassword;
+
+extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
+
+//
+//extern EFI_REG_TABLE mSubsystemIdRegs[];
+//
+extern UINT32 mSubsystemVidDid;
+extern UINT32 mSubsystemAudioVidDid;
+
+extern UINT8 mBoardIdIndex;
+extern BOOLEAN mFoundAANum;
+extern EFI_BOARD_FEATURES mBoardFeatures;
+extern UINT16 mSubsystemDeviceId;
+extern UINT16 mSubsystemAudioDeviceId;
+extern BOARD_ID_DECODE mBoardIdDecodeTable[];
+extern UINTN mBoardIdDecodeTableSize;
+
+extern UINT8 mSmbusRsvdAddresses[];
+extern UINT8 mNumberSmbusAddress;
+extern BOOLEAN mMfgMode;
+extern UINT32 mPlatformBootMode;
+extern CHAR8 BoardAaNumber[];
+
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+#endif
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf new file mode 100644 index 0000000000..6fa0700415 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf @@ -0,0 +1,145 @@ +#/*++
+#
+# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+# Module Name:
+#
+# PlatformBB.inf
+#
+# Abstract:
+#
+# Component description file for platform DXE driver
+# ------------------------------------------------------------------------------
+# Rev Date<MM/DD/YYYY> Name Description
+# ------------------------------------------------------------------------------
+# R01 <04/22/2011> LB Update code for SIO83627UHG support.
+# ------------------------------------------------------------------------------
+#
+#--*/
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 056E7324-A718-465b-9A84-228F06642B4F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ PI_SPECIFICATION_VERSION = 0x0001000A
+ ENTRY_POINT = InitializePlatform
+
+[sources.common]
+ BoardId.c
+ BoardIdDecode.c
+ ClockControl.c
+ Platform.c
+ IchRegTable.c
+ IdccInfo.c
+ SioPlatformPolicy.c
+ IchPlatformPolicy.c
+ PciDevice.c
+ SlotConfig.c
+ IchTcoReset.c
+ SensorVar.c
+ LegacySpeaker.c
+ Observable/Observable.c
+ ExI.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ Vlv2TbltDevicePkg/PlatformPkg.dec
+ Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ DxeServicesTableLib
+ PchPlatformLib
+
+ DebugLib
+ HiiLib
+ PrintLib
+ UefiLib
+ S3BootScriptLib
+ ReportStatusCodeLib
+ EfiRegTableLib
+ BiosIdLib
+ BaseCryptLib
+
+[Guids]
+ gEfiBiosIdGuid
+ gEfiPlatformBootModeGuid
+ gEfiBoardFeaturesGuid
+ gItkDataVarGuid
+ gDmiDataGuid
+ gIdccDataHubGuid
+ gEfiPciLanInfoGuid
+ gEfiNormalSetupGuid
+ gEfiGlobalVariableGuid
+ gEfiEventExitBootServicesGuid
+ gEfiVlv2VariableGuid
+ gEfiSecureBootEnableDisableGuid
+
+[Protocols]
+ gEfiPciRootBridgeIoProtocolGuid # CONSUMES ## GUID
+ gEfiVariableArchProtocolGuid
+ gEfiVariableWriteArchProtocolGuid
+ gEfiHiiConfigAccessProtocolGuid
+ gEfiBootScriptSaveProtocolGuid
+ gEfiCpuIoProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiDiskInfoProtocolGuid
+ gEfiPs2PolicyProtocolGuid
+ gEfiIsaAcpiProtocolGuid
+ gEfiDataHubProtocolGuid
+ gEfiPciIoProtocolGuid
+ gDxePchPlatformPolicyProtocolGuid
+ gEfiTpmMpDriverProtocolGuid
+ gEfiLpcWpce791PolicyProtocolGuid
+ gUsbPolicyGuid
+ gEfiSpeakerInterfaceProtocolGuid
+ gDxeVlvPlatformPolicyGuid
+ gEfiSmbiosSlotPopulationGuid
+ gObservableProtocolGuid
+ gEfiCk505ClockPlatformInfoGuid
+ gEfiLpcWpc83627PolicyProtocolGuid
+ gEfiTcoResetProtocolGuid
+ gEfiWatchdogTimerDriverProtocolGuid
+ gEfiPlatformIdeInitProtocolGuid
+ gEfiGlobalNvsAreaProtocolGuid
+ gEfiCpuIo2ProtocolGuid
+ gIgdOpRegionProtocolGuid
+
+[Pcd.common]
+ gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
+ gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection
+
+[Depex]
+ gEfiPciRootBridgeIoProtocolGuid AND
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid AND
+ gEfiBootScriptSaveProtocolGuid AND
+ gEfiCpuIoProtocolGuid AND
+ gDxePchPlatformPolicyProtocolGuid AND
+ gEfiGlobalNvsAreaProtocolGuid
+
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c b/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c new file mode 100644 index 0000000000..27f742b807 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c @@ -0,0 +1,117 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ SensorVar.c
+
+Abstract:
+
+ Initialization for the Sensor Info variable.
+
+Revision History
+
+--*/
+
+#include "PlatformDxe.h"
+#include "Guid/SensorInfoVariable.h"
+
+//
+// Sensor Information (board specific)
+//
+
+#define TEMPERATURE_SENSORS_COUNT 4
+#define VOLTAGE_SENSORS_COUNT 6
+#define FAN_SENSORS_COUNT 4
+#define FAN_CONTROLLERS_COUNT 3
+
+TYPEDEF_TEMP_SENSOR_SECTION(TEMPERATURE_SENSORS_COUNT);
+TYPEDEF_VOLT_SENSOR_SECTION(VOLTAGE_SENSORS_COUNT);
+TYPEDEF_FAN_SENSOR_SECTION(FAN_SENSORS_COUNT);
+TYPEDEF_FAN_CONTROLLER_SECTION(FAN_CONTROLLERS_COUNT);
+TYPEDEF_SENSOR_INFO_VAR;
+
+SENSOR_INFO_VAR mSensorInfoData =
+{
+ //
+ // Temperature Sensors
+ //
+ TEMPERATURE_SENSORS_COUNT,
+ {
+ { 0, 3, CPU_CORE_TEMPERATURE, TRUE },
+ { 0, 1, MOTHERBOARD_AMBIENT_TEMPERATURE, FALSE },
+ { 0, 2, VR_TEMPERATURE, FALSE },
+ { 0, 0, IOH_TEMPERATURE, FALSE }
+ },
+
+ //
+ // Voltage Sensors
+ //
+ VOLTAGE_SENSORS_COUNT,
+ {
+ { 0, 0, PLUS_12_VOLTS },
+ { 0, 1, PLUS_5_VOLTS },
+ { 0, 2, PLUS_3P3_VOLTS },
+ { 0, 3, MCH_VCC_VOLTAGE },
+ { 0, 4, CPU_1_VCCP_VOLTAGE },
+ { 0, 5, CPU_VTT_VOLTAGE }
+ },
+
+ //
+ // Fan Speed Sensors
+ //
+ FAN_SENSORS_COUNT,
+ {
+ { 0, 0, CPU_COOLING_FAN, FAN_4WIRE, 0 },
+ { 0, 1, AUX_COOLING_FAN, FAN_4WIRE, 1 },
+ { 0, 2, CHASSIS_INLET_FAN, FAN_3WIRE_VOLTAGE, 1 },
+ { 0, 3, CHASSIS_OUTLET_FAN, FAN_3WIRE_VOLTAGE, 2 }
+ },
+
+ //
+ // Fan Speed Controllers
+ //
+ FAN_CONTROLLERS_COUNT,
+ {
+ { 0, 0, CPU_COOLING_FAN, { 0, 0xff, 0xff, 0xff } },
+ { 0, 1, CHASSIS_COOLING_FAN, { 1, 2, 0xff, 0xff } },
+ { 0, 2, CHASSIS_COOLING_FAN, { 3, 0xff, 0xff, 0xff } }
+ }
+};
+
+/**
+
+ Write the Sensor Info variable if it does not already exist.
+
+**/
+VOID
+InitializeSensorInfoVariable (
+ )
+{
+ //
+ // Set the Sensor Info variable. If it already exists and the data matches,
+ // the variable driver will simply return without writing; otherwise, the
+ // driver will write the variable.
+ //
+ gRT->SetVariable (
+ gEfiSensorInfoVarNameWithPassword,
+ &gEfiSensorInfoVarGuid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (SENSOR_INFO_VAR),
+ &mSensorInfoData
+ );
+}
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c b/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c new file mode 100644 index 0000000000..da006279ce --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c @@ -0,0 +1,87 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+
+ SioPlatformPolicy.c
+
+Abstract:
+
+ Sio Platform Policy Setting.
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include <Protocol/LpcWpc83627Policy.h>
+
+
+EFI_WPC83627_POLICY_PROTOCOL mSio83627PolicyData = {
+ { EFI_WPC83627_COM1_ENABLE, // Com1
+ EFI_WPC83627_LPT1_ENABLE, // Lpt1
+ EFI_WPC83627_FDD_DISABLE, // Floppy
+ EFI_WPC83627_FDD_WRITE_ENABLE, // FloppyWriteProtect
+ EFI_WPC83627_RESERVED_DEFAULT, // Port80
+ EFI_WPC83627_ECIR_DISABLE, // CIR
+ EFI_WPC83627_PS2_KBC_ENABLE, // Ps2Keyboard
+ EFI_WPC83627_RESERVED_DEFAULT, // Ps2Mouse
+ EFI_WPC83627_COM2_ENABLE, // Com2
+ EFI_WPC83627_COM3_ENABLE, // Com3
+ EFI_WPC83627_COM4_ENABLE, // Com4
+ EFI_WPC83627_RESERVED_DEFAULT, // Dac
+ 0x00 // Rsvd
+ },
+ LptModeEcp, // LptMode
+};
+
+/**
+
+ Publish the platform SIO policy setting.
+
+ @retval EFI_SUCCESS
+
+**/
+VOID
+InitSioPlatformPolicy(
+ )
+{
+
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+
+ Handle = NULL;
+
+ if((mSystemConfiguration.Serial) || (mBoardFeatures & B_BOARD_FEATURES_SIO_NO_COM1)) {
+ mSio83627PolicyData.DeviceEnables.Com1 = EFI_WPC83627_COM1_DISABLE;
+ }
+
+ if((mSystemConfiguration.Serial2) || ((mBoardFeatures & B_BOARD_FEATURES_SIO_COM2)==0)) {
+ mSio83627PolicyData.DeviceEnables.Com2 = EFI_WPC83627_COM2_DISABLE;
+ }
+
+ mSio83627PolicyData.LptMode = mSystemConfiguration.ParallelMode;
+ if((!mSystemConfiguration.Parallel) || (mBoardFeatures & B_BOARD_FEATURES_SIO_NO_PARALLEL)) {
+ mSio83627PolicyData.DeviceEnables.Lpt1 = EFI_WPC83627_LPT1_DISABLE;
+ }
+
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiLpcWpc83627PolicyProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mSio83627PolicyData
+ );
+ ASSERT_EFI_ERROR(Status);
+
+}
+
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c new file mode 100644 index 0000000000..c0c752601f --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c @@ -0,0 +1,153 @@ +/** @file
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ SlotConfig.c
+
+Abstract:
+
+ Sets platform/SKU specific expansion slot information.
+
+
+
+--*/
+#include "SlotConfig.h"
+
+//
+// Implementation
+//
+VOID
+InitializeSlotInfo (
+ )
+{
+ UINT16 BusSaveState;
+ UINT16 Vendor;
+ UINT8 CurrentBus;
+ UINTN i;
+ UINTN j;
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+ BOOLEAN RunNext;
+
+ //
+ // Loop through the slot table and see if any slots have cards in them
+ //
+ for (i = 0; i < mSlotBridgeTableSize; i++) {
+ //
+ // Initialize variable
+ //
+ RunNext = FALSE;
+
+ //
+ // Hide mini PCIe slots per SKU
+ //
+ for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
+ if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {
+ if ((mSlotInformation.SlotEntries[j].SmbiosSlotId == 0x02) &&
+ (mBoardFeatures & B_BOARD_FEATURES_NO_MINIPCIE)
+ ) {
+ mSlotInformation.SlotEntries[j].Disabled = TRUE;
+ RunNext = TRUE;
+ }
+ break;
+ }
+ }
+
+ if (RunNext) {
+ //
+ // Skip slot device detection since the slot is disabled.
+ //
+ continue;
+ }
+
+ //
+ // Check to see if the bridge has a bus number and assign one if not
+ //
+ BusSaveState = MmPci16 (
+ 0,
+ mSlotBridgeTable[i].Bus,
+ mSlotBridgeTable[i].Dev,
+ mSlotBridgeTable[i].Function,
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
+ );
+ if (BusSaveState == 0) {
+ //
+ // Assign temp bus number
+ //
+ MmPci16 (
+ 0,
+ mSlotBridgeTable[i].Bus,
+ mSlotBridgeTable[i].Dev,
+ mSlotBridgeTable[i].Function,
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
+ ) = DEF_BUS_CONFIG;
+ CurrentBus = DEF_BUS;
+ } else if (BusSaveState == 0xFFFF) {
+ //
+ // Bridge is disabled so continue with next entry in the table
+ //
+ continue;
+ } else {
+ //
+ // Use existing bus number
+ //
+ CurrentBus = (UINT8) BusSaveState & 0xFF;
+ }
+
+ //
+ // Check to see if a device is behind the bridge
+ //
+ Vendor = MmPci16 (
+ 0,
+ CurrentBus,
+ mSlotBridgeTable[i].TargetDevice,
+ 0,
+ 0
+ );
+ if (Vendor != 0xFFFF) {
+ //
+ // Device found so make sure the slot is marked that way
+ //
+ for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {
+ if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {
+ mSlotInformation.SlotEntries[j].InUse = TRUE;
+ break;
+ }
+ }
+ }
+
+ //
+ // Restore previous bus information
+ //
+ if (BusSaveState == 0) {
+ MmPci16 (
+ 0,
+ mSlotBridgeTable[i].Bus,
+ mSlotBridgeTable[i].Dev,
+ mSlotBridgeTable[i].Function,
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
+ ) = 0;
+ }
+ }
+
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gEfiSmbiosSlotPopulationGuid,
+ EFI_NATIVE_INTERFACE,
+ &mSlotInformation
+ );
+ ASSERT_EFI_ERROR(Status);
+
+}
diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h new file mode 100644 index 0000000000..97380dbaa8 --- /dev/null +++ b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h @@ -0,0 +1,85 @@ +/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ SlotConfig.c
+
+Abstract:
+
+ Sets platform/SKU specific expansion slot information.
+
+
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include <Protocol/SmbiosSlotPopulation.h>
+#include <IndustryStandard/Pci22.h>
+
+
+//
+// Default bus number for the bridge
+//
+#define DEF_BUS_CONFIG 0x0101
+#define DEF_BUS 0x01
+
+//
+// Data structures for slot information
+//
+typedef struct {
+ UINT16 SmbiosSlotId;
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Function;
+ UINT8 TargetDevice;
+} EFI_PCI_SLOT_BRIDGE_INFO;
+
+//
+// Product specific bridge to slot routing information
+//
+EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {
+ {
+ 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
+ PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,
+ 0
+ }
+};
+
+UINTN mSlotBridgeTableSize =
+ sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);
+
+//
+// Slot entry table for IBX RVP
+//
+EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {
+ {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)
+ {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)
+ {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)
+ {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot
+ {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)
+ {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)
+ {0x07, FALSE, FALSE}, // PCI Slot 1
+ {0x18, FALSE, TRUE}, // PCI Slot 2 (NOT USED)
+ {0x17, FALSE, TRUE}, // PCI Slot 3 (NOT USED)
+};
+
+EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {
+ sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),
+ mSlotEntries
+};
+
+
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