diff options
Diffstat (limited to 'ArmPlatformPkg/Library')
16 files changed, 664 insertions, 634 deletions
diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c index 23e01f43b3..d01c910f6e 100644 --- a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c @@ -17,7 +17,7 @@ #include "ArmMaliDp.h"
// CORE_ID of the MALI DP
-STATIC UINT32 mDpDeviceId;
+STATIC UINT32 mDpDeviceId;
/** Disable the graphics layer
@@ -25,7 +25,9 @@ STATIC UINT32 mDpDeviceId; **/
STATIC
VOID
-LayerGraphicsDisable (VOID)
+LayerGraphicsDisable (
+ VOID
+ )
{
MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);
}
@@ -36,7 +38,9 @@ LayerGraphicsDisable (VOID) **/
STATIC
VOID
-LayerGraphicsEnable (VOID)
+LayerGraphicsEnable (
+ VOID
+ )
{
MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);
}
@@ -49,7 +53,7 @@ LayerGraphicsEnable (VOID) STATIC
VOID
LayerGraphicsSetFrame (
- IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
+ IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
)
{
// Disable the graphics layer.
@@ -84,12 +88,12 @@ LayerGraphicsSetFrame ( STATIC
VOID
LayerGraphicsConfig (
- IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,
- IN CONST UINT32 HRes,
- IN CONST UINT32 VRes
+ IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,
+ IN CONST UINT32 HRes,
+ IN CONST UINT32 VRes
)
{
- UINT32 PixelFormat;
+ UINT32 PixelFormat;
// Disable the graphics layer before configuring any settings.
LayerGraphicsDisable ();
@@ -134,26 +138,26 @@ LayerGraphicsConfig ( STATIC
VOID
SetDisplayEngineTiming (
- IN CONST SCAN_TIMINGS * CONST Horizontal,
- IN CONST SCAN_TIMINGS * CONST Vertical
+ IN CONST SCAN_TIMINGS *CONST Horizontal,
+ IN CONST SCAN_TIMINGS *CONST Vertical
)
{
- UINTN RegHIntervals;
- UINTN RegVIntervals;
- UINTN RegSyncControl;
- UINTN RegHVActiveSize;
+ UINTN RegHIntervals;
+ UINTN RegVIntervals;
+ UINTN RegSyncControl;
+ UINTN RegHVActiveSize;
if (mDpDeviceId == MALIDP_500) {
// MALI DP500 timing registers.
- RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;
- RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;
- RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;
+ RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;
+ RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;
+ RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;
} else {
// MALI DP550/DP650 timing registers.
- RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;
- RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;
- RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;
+ RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;
+ RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;
+ RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;
RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;
}
@@ -194,11 +198,11 @@ UINT32 ArmMaliDpGetCoreId (
)
{
- UINT32 DpCoreId;
+ UINT32 DpCoreId;
// First check for DP500 as register offset for DP550/DP650 CORE_ID
// is beyond 3K/4K register space of the DP500.
- DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);
+ DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);
DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;
if (DpCoreId == MALIDP_500) {
@@ -206,7 +210,7 @@ ArmMaliDpGetCoreId ( }
// Check for DP550 or DP650.
- DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);
+ DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);
DpCoreId >>= DP_DC_CORE_ID_SHIFT;
if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) {
@@ -227,9 +231,12 @@ ArmMaliDpGetCoreId ( on the platform.
**/
EFI_STATUS
-LcdIdentify (VOID)
+LcdIdentify (
+ VOID
+ )
{
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",
DP_BASE
));
@@ -239,8 +246,8 @@ LcdIdentify (VOID) }
if (mDpDeviceId == MALIDP_NOT_PRESENT) {
- DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));
- return EFI_NOT_FOUND;
+ DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));
+ return EFI_NOT_FOUND;
}
DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));
@@ -256,7 +263,7 @@ LcdIdentify (VOID) **/
EFI_STATUS
LcdInitialize (
- IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
+ IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress
)
{
DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));
@@ -266,8 +273,11 @@ LcdInitialize ( }
if (mDpDeviceId == MALIDP_NOT_PRESENT) {
- DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed,"
- "no ARM Mali DP present\n"));
+ DEBUG ((
+ DEBUG_ERROR,
+ "ARM Mali DP initialization failed,"
+ "no ARM Mali DP present\n"
+ ));
return EFI_NOT_FOUND;
}
@@ -285,7 +295,9 @@ LcdInitialize ( **/
STATIC
VOID
-SetConfigurationMode (VOID)
+SetConfigurationMode (
+ VOID
+ )
{
// Request configuration Mode.
if (mDpDeviceId == MALIDP_500) {
@@ -303,7 +315,9 @@ SetConfigurationMode (VOID) **/
STATIC
VOID
-SetNormalMode (VOID)
+SetNormalMode (
+ VOID
+ )
{
// Disable configuration Mode.
if (mDpDeviceId == MALIDP_500) {
@@ -321,7 +335,9 @@ SetNormalMode (VOID) **/
STATIC
VOID
-SetConfigValid (VOID)
+SetConfigValid (
+ VOID
+ )
{
if (mDpDeviceId == MALIDP_500) {
MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);
@@ -396,7 +412,9 @@ LcdSetMode ( **/
VOID
-LcdShutdown (VOID)
+LcdShutdown (
+ VOID
+ )
{
// Disable graphics layer.
LayerGraphicsDisable ();
diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h index 7939b0ff5f..76a628c07a 100644 --- a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h @@ -6,232 +6,233 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef ARMMALIDP_H_
#define ARMMALIDP_H_
-#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
+#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))
// MALI DP Ids
-#define MALIDP_NOT_PRESENT 0xFFF
-#define MALIDP_500 0x500
-#define MALIDP_550 0x550
-#define MALIDP_650 0x650
+#define MALIDP_NOT_PRESENT 0xFFF
+#define MALIDP_500 0x500
+#define MALIDP_550 0x550
+#define MALIDP_650 0x650
// DP500 Peripheral Ids
-#define DP500_ID_PART_0 0x00
-#define DP500_ID_DES_0 0xB
-#define DP500_ID_PART_1 0x5
+#define DP500_ID_PART_0 0x00
+#define DP500_ID_DES_0 0xB
+#define DP500_ID_PART_1 0x5
-#define DP500_ID_REVISION 0x1
-#define DP500_ID_JEDEC 0x1
-#define DP500_ID_DES_1 0x3
+#define DP500_ID_REVISION 0x1
+#define DP500_ID_JEDEC 0x1
+#define DP500_ID_DES_1 0x3
-#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
-#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
+#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)
+#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \
| DP500_ID_PART_1)
-#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
+#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \
| (DP500_ID_JEDEC << 3) \
| (DP500_ID_DES_1))
// DP550 Peripheral Ids
-#define DP550_ID_PART_0 0x50
-#define DP550_ID_DES_0 0xB
-#define DP550_ID_PART_1 0x5
+#define DP550_ID_PART_0 0x50
+#define DP550_ID_DES_0 0xB
+#define DP550_ID_PART_1 0x5
-#define DP550_ID_REVISION 0x0
-#define DP550_ID_JEDEC 0x1
-#define DP550_ID_DES_1 0x3
+#define DP550_ID_REVISION 0x0
+#define DP550_ID_JEDEC 0x1
+#define DP550_ID_DES_1 0x3
-#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
-#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
+#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)
+#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \
| DP550_ID_PART_1)
-#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
+#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \
| (DP550_ID_JEDEC << 3) \
| (DP550_ID_DES_1))
// DP650 Peripheral Ids
-#define DP650_ID_PART_0 0x50
-#define DP650_ID_DES_0 0xB
-#define DP650_ID_PART_1 0x6
+#define DP650_ID_PART_0 0x50
+#define DP650_ID_DES_0 0xB
+#define DP650_ID_PART_1 0x6
-#define DP650_ID_REVISION 0x0
-#define DP650_ID_JEDEC 0x1
-#define DP650_ID_DES_1 0x3
+#define DP650_ID_REVISION 0x0
+#define DP650_ID_JEDEC 0x1
+#define DP650_ID_DES_1 0x3
-#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
-#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
+#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)
+#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \
| DP650_ID_PART_1)
-#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
+#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \
| (DP650_ID_JEDEC << 3) \
| (DP650_ID_DES_1))
// Display Engine (DE) control register offsets for DP550/DP650
-#define DP_DE_STATUS 0x00000
-#define DP_DE_IRQ_SET 0x00004
-#define DP_DE_IRQ_MASK 0x00008
-#define DP_DE_IRQ_CLEAR 0x0000C
-#define DP_DE_CONTROL 0x00010
-#define DP_DE_PROG_LINE 0x00014
-#define DP_DE_AXI_CONTROL 0x00018
-#define DP_DE_AXI_QOS 0x0001C
-#define DP_DE_DISPLAY_FUNCTION 0x00020
-
-#define DP_DE_H_INTERVALS 0x00030
-#define DP_DE_V_INTERVALS 0x00034
-#define DP_DE_SYNC_CONTROL 0x00038
-#define DP_DE_HV_ACTIVESIZE 0x0003C
-#define DP_DE_DISPLAY_SIDEBAND 0x00040
-#define DP_DE_BACKGROUND_COLOR 0x00044
-#define DP_DE_DISPLAY_SPLIT 0x00048
-#define DP_DE_OUTPUT_DEPTH 0x0004C
+#define DP_DE_STATUS 0x00000
+#define DP_DE_IRQ_SET 0x00004
+#define DP_DE_IRQ_MASK 0x00008
+#define DP_DE_IRQ_CLEAR 0x0000C
+#define DP_DE_CONTROL 0x00010
+#define DP_DE_PROG_LINE 0x00014
+#define DP_DE_AXI_CONTROL 0x00018
+#define DP_DE_AXI_QOS 0x0001C
+#define DP_DE_DISPLAY_FUNCTION 0x00020
+
+#define DP_DE_H_INTERVALS 0x00030
+#define DP_DE_V_INTERVALS 0x00034
+#define DP_DE_SYNC_CONTROL 0x00038
+#define DP_DE_HV_ACTIVESIZE 0x0003C
+#define DP_DE_DISPLAY_SIDEBAND 0x00040
+#define DP_DE_BACKGROUND_COLOR 0x00044
+#define DP_DE_DISPLAY_SPLIT 0x00048
+#define DP_DE_OUTPUT_DEPTH 0x0004C
// Display Engine (DE) control register offsets for DP500
-#define DP_DE_DP500_CORE_ID 0x00018
-#define DP_DE_DP500_CONTROL 0x0000C
-#define DP_DE_DP500_PROG_LINE 0x00010
-#define DP_DE_DP500_H_INTERVALS 0x00028
-#define DP_DE_DP500_V_INTERVALS 0x0002C
-#define DP_DE_DP500_SYNC_CONTROL 0x00030
-#define DP_DE_DP500_HV_ACTIVESIZE 0x00034
-#define DP_DE_DP500_BG_COLOR_RG 0x0003C
-#define DP_DE_DP500_BG_COLOR_B 0x00040
+#define DP_DE_DP500_CORE_ID 0x00018
+#define DP_DE_DP500_CONTROL 0x0000C
+#define DP_DE_DP500_PROG_LINE 0x00010
+#define DP_DE_DP500_H_INTERVALS 0x00028
+#define DP_DE_DP500_V_INTERVALS 0x0002C
+#define DP_DE_DP500_SYNC_CONTROL 0x00030
+#define DP_DE_DP500_HV_ACTIVESIZE 0x00034
+#define DP_DE_DP500_BG_COLOR_RG 0x0003C
+#define DP_DE_DP500_BG_COLOR_B 0x00040
/* Display Engine (DE) graphics layer (LG) register offsets
* NOTE: For DP500 it will be LG2.
*/
-#define DE_LG_OFFSET 0x00300
-#define DP_DE_LG_FORMAT (DE_LG_OFFSET)
-#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
-#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
-#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
-#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
-#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
-#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
-#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
-#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
-#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
-#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
-#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
+#define DE_LG_OFFSET 0x00300
+#define DP_DE_LG_FORMAT (DE_LG_OFFSET)
+#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)
+#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)
+#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)
+#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)
+#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)
+#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)
+#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)
+#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)
+#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)
+#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)
+#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)
// Display core (DC) control register offsets.
-#define DP_DC_OFFSET 0x0C000
-#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
-#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
-#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
-#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
-#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
-#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
-#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
+#define DP_DC_OFFSET 0x0C000
+#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)
+#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)
+#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)
+#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)
+#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)
+#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)
+#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)
// DP500 has a global configuration register.
-#define DP_DP500_CONFIG_VALID (0xF00)
+#define DP_DP500_CONFIG_VALID (0xF00)
// Display core ID register offsets.
-#define DP_DC_ID_OFFSET 0x0FF00
-#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
-#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
-#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
-#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
-#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
-#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
-#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
-#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
-#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
-
-#define DP_DP500_ID_OFFSET 0x0F00
-#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
-#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
-#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
-#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
-#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
-#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
-#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
-#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
-#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
+#define DP_DC_ID_OFFSET 0x0FF00
+#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)
+#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)
+#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)
+#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)
+#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)
+#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)
+#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)
+#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)
+#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)
+
+#define DP_DP500_ID_OFFSET 0x0F00
+#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)
+#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)
+#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)
+#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)
+#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)
+#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)
+#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)
+#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)
+#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)
// Display status configuration mode activation flag
-#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
+#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)
// Display core control configuration mode
-#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
-#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
-#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
+#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)
+#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)
+#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)
#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)
#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)
// Display core configuration valid register
-#define DP_DC_CONFIG_VALID_CVAL (0x1U)
+#define DP_DC_CONFIG_VALID_CVAL (0x1U)
// DC_CORE_ID
// Display core version register PRODUCT_ID
-#define DP_DC_CORE_ID_SHIFT 16
-#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
+#define DP_DC_CORE_ID_SHIFT 16
+#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT
// Timing settings
-#define DP_DE_HBACKPORCH_SHIFT 16
-#define DP_DE_VBACKPORCH_SHIFT 16
-#define DP_DE_VSP_SHIFT 28
-#define DP_DE_VSYNCWIDTH_SHIFT 16
-#define DP_DE_HSP_SHIFT 13
-#define DP_DE_V_ACTIVE_SHIFT 16
+#define DP_DE_HBACKPORCH_SHIFT 16
+#define DP_DE_VBACKPORCH_SHIFT 16
+#define DP_DE_VSP_SHIFT 28
+#define DP_DE_VSYNCWIDTH_SHIFT 16
+#define DP_DE_HSP_SHIFT 13
+#define DP_DE_V_ACTIVE_SHIFT 16
// BACKGROUND_COLOR
-#define DP_DE_BG_R_PIXEL_SHIFT 16
-#define DP_DE_BG_G_PIXEL_SHIFT 8
-
-//Graphics layer LG_FORMAT Pixel Format
-#define DP_PIXEL_FORMAT_ARGB_8888 0x8
-#define DP_PIXEL_FORMAT_ABGR_8888 0x9
-#define DP_PIXEL_FORMAT_RGBA_8888 0xA
-#define DP_PIXEL_FORMAT_BGRA_8888 0xB
-#define DP_PIXEL_FORMAT_XRGB_8888 0x10
-#define DP_PIXEL_FORMAT_XBGR_8888 0x11
-#define DP_PIXEL_FORMAT_RGBX_8888 0x12
-#define DP_PIXEL_FORMAT_BGRX_8888 0x13
-#define DP_PIXEL_FORMAT_RGB_888 0x18
-#define DP_PIXEL_FORMAT_BGR_888 0x19
+#define DP_DE_BG_R_PIXEL_SHIFT 16
+#define DP_DE_BG_G_PIXEL_SHIFT 8
+
+// Graphics layer LG_FORMAT Pixel Format
+#define DP_PIXEL_FORMAT_ARGB_8888 0x8
+#define DP_PIXEL_FORMAT_ABGR_8888 0x9
+#define DP_PIXEL_FORMAT_RGBA_8888 0xA
+#define DP_PIXEL_FORMAT_BGRA_8888 0xB
+#define DP_PIXEL_FORMAT_XRGB_8888 0x10
+#define DP_PIXEL_FORMAT_XBGR_8888 0x11
+#define DP_PIXEL_FORMAT_RGBX_8888 0x12
+#define DP_PIXEL_FORMAT_BGRX_8888 0x13
+#define DP_PIXEL_FORMAT_RGB_888 0x18
+#define DP_PIXEL_FORMAT_BGR_888 0x19
// DP500 format code are different than DP550/DP650
-#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
-#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
-#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
-#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
+#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2
+#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3
+#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4
+#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5
// Graphics layer LG_PTR_LOW and LG_PTR_HIGH
-#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
-#define DP_DE_LG_PTR_HIGH_SHIFT 32
+#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU
+#define DP_DE_LG_PTR_HIGH_SHIFT 32
// Graphics layer LG_CONTROL register characteristics
-#define DP_DE_LG_L_ALPHA_SHIFT 16
-#define DP_DE_LG_CHK_SHIFT 15
-#define DP_DE_LG_PMUL_SHIFT 14
-#define DP_DE_LG_COM_SHIFT 12
-#define DP_DE_LG_VFP_SHIFT 11
-#define DP_DE_LG_HFP_SHIFT 10
-#define DP_DE_LG_ROTATION_SHIFT 8
-
-#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
-#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
-#define DP_DE_LG_LAYER_BLEND_BG 0x2U
-#define DP_DE_LG_PIXEL_BLEND_BG 0x3U
-#define DP_DE_LG_ENABLE 0x1U
+#define DP_DE_LG_L_ALPHA_SHIFT 16
+#define DP_DE_LG_CHK_SHIFT 15
+#define DP_DE_LG_PMUL_SHIFT 14
+#define DP_DE_LG_COM_SHIFT 12
+#define DP_DE_LG_VFP_SHIFT 11
+#define DP_DE_LG_HFP_SHIFT 10
+#define DP_DE_LG_ROTATION_SHIFT 8
+
+#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U
+#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U
+#define DP_DE_LG_LAYER_BLEND_BG 0x2U
+#define DP_DE_LG_PIXEL_BLEND_BG 0x3U
+#define DP_DE_LG_ENABLE 0x1U
// Graphics layer LG_IN_SIZE register characteristics
-#define DP_DE_LG_V_IN_SIZE_SHIFT 16
+#define DP_DE_LG_V_IN_SIZE_SHIFT 16
// Graphics layer LG_CMP_SIZE register characteristics
-#define DP_DE_LG_V_CMP_SIZE_SHIFT 16
-#define DP_DE_LG_V_OFFSET_SHIFT 16
+#define DP_DE_LG_V_CMP_SIZE_SHIFT 16
+#define DP_DE_LG_V_OFFSET_SHIFT 16
// Helper display timing macro functions.
-#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
-#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
-#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
-#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
+#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)
+#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)
+#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)
+#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)
// Helper layer graphics macros.
-#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
-#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
+#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)
+#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)
#endif /* ARMMALIDP_H_ */
diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c index 1cd9ec30a9..eeab58805e 100644 --- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c +++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.c @@ -11,8 +11,7 @@ #include <Ppi/ArmMpCoreInfo.h>
-
-ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
+ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
@@ -88,26 +87,26 @@ ArmPlatformGetBootMode ( **/
RETURN_STATUS
ArmPlatformInitialize (
- IN UINTN MpId
+ IN UINTN MpId
)
{
if (!ArmPlatformIsPrimaryCore (MpId)) {
return RETURN_SUCCESS;
}
- //TODO: Implement me
+ // TODO: Implement me
return RETURN_SUCCESS;
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
)
{
- if (ArmIsMpCore()) {
- *CoreCount = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+ if (ArmIsMpCore ()) {
+ *CoreCount = sizeof (mArmPlatformNullMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
*ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
return EFI_SUCCESS;
} else {
@@ -115,9 +114,9 @@ PrePeiCoreGetMpCoreInfo ( }
}
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gArmMpCoreInfoPpiGuid,
@@ -131,12 +130,11 @@ ArmPlatformGetPlatformPpiList ( OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
- if (ArmIsMpCore()) {
- *PpiListSize = sizeof(gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
+ if (ArmIsMpCore ()) {
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
} else {
*PpiListSize = 0;
- *PpiList = NULL;
+ *PpiList = NULL;
}
}
-
diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c index 686e083e2e..7151c96625 100644 --- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c +++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullMem.c @@ -21,8 +21,8 @@ **/
VOID
ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
)
{
- ASSERT(0);
+ ASSERT (0);
}
diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/HdLcd/HdLcd.c index 0247057e68..6bab6bd45d 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -16,7 +16,7 @@ #include "HdLcd.h"
-#define BYTES_PER_PIXEL 4
+#define BYTES_PER_PIXEL 4
/** Initialize display.
@@ -26,7 +26,7 @@ **/
EFI_STATUS
LcdInitialize (
- IN EFI_PHYSICAL_ADDRESS VramBaseAddress
+ IN EFI_PHYSICAL_ADDRESS VramBaseAddress
)
{
// Disable the controller
@@ -39,7 +39,7 @@ LcdInitialize ( MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
// Setup various registers that never change
- MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
+ MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
@@ -63,9 +63,9 @@ LcdSetMode ( IN UINT32 ModeNumber
)
{
- EFI_STATUS Status;
- SCAN_TIMINGS *Horizontal;
- SCAN_TIMINGS *Vertical;
+ EFI_STATUS Status;
+ SCAN_TIMINGS *Horizontal;
+ SCAN_TIMINGS *Vertical;
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
@@ -100,11 +100,11 @@ LcdSetMode ( : PixelBlueGreenRedReserved8BitPerColor;
if (ModeInfo.PixelFormat == PixelFormat) {
- MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
+ MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 16);
MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 0);
} else {
MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8) | 16);
- MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
+ MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8) | 0);
}
MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8) | 8);
@@ -126,15 +126,15 @@ LcdSetMode ( MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1);
// Set the vertical timing information
- MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
- MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
- MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
+ MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync);
+ MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch);
+ MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1);
MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch);
// Set the horizontal timing information
- MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
- MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
- MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
+ MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync);
+ MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch);
+ MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1);
MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch);
// Enable the controller
diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/HdLcd/HdLcd.h index ca5c6676cf..ea0a0fcc6f 100644 --- a/ArmPlatformPkg/Library/HdLcd/HdLcd.h +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -10,75 +10,75 @@ #define HDLCD_H_
// HDLCD Controller Register Offsets
-#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
-#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
-#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
-#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
-#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
-#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
-#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
-#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
-#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
-#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
-#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
-#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
-#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
-#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
-#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
-#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
-#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
-#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
-#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
-#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
-#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
-#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
-#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
-#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
+#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
+#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
+#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
+#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
+#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
+#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
+#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
+#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
+#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
+#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
+#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
+#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
+#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
+#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
+#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
+#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
+#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
+#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
+#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
+#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
+#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
+#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
+#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
+#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
// HDLCD Values of registers
// HDLCD Interrupt mask, clear and status register
-#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
-#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
-#define HDLCD_SYNC BIT2 /* Vertical sync */
-#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
+#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
+#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
+#define HDLCD_SYNC BIT2 /* Vertical sync */
+#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
// CLCD_CONTROL Control register
-#define HDLCD_DISABLE 0
-#define HDLCD_ENABLE BIT0
+#define HDLCD_DISABLE 0
+#define HDLCD_ENABLE BIT0
// Bus Options
-#define HDLCD_BURST_1 BIT0
-#define HDLCD_BURST_2 BIT1
-#define HDLCD_BURST_4 BIT2
-#define HDLCD_BURST_8 BIT3
-#define HDLCD_BURST_16 BIT4
+#define HDLCD_BURST_1 BIT0
+#define HDLCD_BURST_2 BIT1
+#define HDLCD_BURST_4 BIT2
+#define HDLCD_BURST_8 BIT3
+#define HDLCD_BURST_16 BIT4
// Polarities - HIGH
-#define HDLCD_VSYNC_HIGH BIT0
-#define HDLCD_HSYNC_HIGH BIT1
-#define HDLCD_DATEN_HIGH BIT2
-#define HDLCD_DATA_HIGH BIT3
-#define HDLCD_PXCLK_HIGH BIT4
+#define HDLCD_VSYNC_HIGH BIT0
+#define HDLCD_HSYNC_HIGH BIT1
+#define HDLCD_DATEN_HIGH BIT2
+#define HDLCD_DATA_HIGH BIT3
+#define HDLCD_PXCLK_HIGH BIT4
// Polarities - LOW (for completion and for ease of understanding the hardware settings)
-#define HDLCD_VSYNC_LOW 0
-#define HDLCD_HSYNC_LOW 0
-#define HDLCD_DATEN_LOW 0
-#define HDLCD_DATA_LOW 0
-#define HDLCD_PXCLK_LOW 0
+#define HDLCD_VSYNC_LOW 0
+#define HDLCD_HSYNC_LOW 0
+#define HDLCD_DATEN_LOW 0
+#define HDLCD_DATA_LOW 0
+#define HDLCD_PXCLK_LOW 0
// Default polarities
-#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
+#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
HDLCD_VSYNC_HIGH)
// Pixel Format
-#define HDLCD_LITTLE_ENDIAN (0 << 31)
-#define HDLCD_BIG_ENDIAN (1 << 31)
+#define HDLCD_LITTLE_ENDIAN (0 << 31)
+#define HDLCD_BIG_ENDIAN (1 << 31)
// Number of bytes per pixel
-#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
+#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
-#define HDLCD_PRODUCT_ID 0x1CDC
+#define HDLCD_PRODUCT_ID 0x1CDC
#endif /* HDLCD_H_ */
diff --git a/ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.c b/ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.c index dca3cf706e..32c2eb3f76 100644 --- a/ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.c +++ b/ArmPlatformPkg/Library/LcdPlatformNullLib/LcdPlatformNullLib.c @@ -20,7 +20,7 @@ **/
EFI_STATUS
LcdPlatformInitializeDisplay (
- IN EFI_HANDLE Handle
+ IN EFI_HANDLE Handle
)
{
ASSERT (FALSE);
@@ -40,8 +40,8 @@ LcdPlatformInitializeDisplay ( **/
EFI_STATUS
LcdPlatformGetVram (
- OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
- OUT UINTN* VramSize
+ OUT EFI_PHYSICAL_ADDRESS *VramBaseAddress,
+ OUT UINTN *VramSize
)
{
ASSERT (FALSE);
@@ -73,7 +73,7 @@ LcdPlatformGetMaxMode ( **/
EFI_STATUS
LcdPlatformSetMode (
- IN UINT32 ModeNumber
+ IN UINT32 ModeNumber
)
{
ASSERT (FALSE);
@@ -116,9 +116,9 @@ LcdPlatformQueryMode ( **/
EFI_STATUS
LcdPlatformGetTimings (
- IN UINT32 ModeNumber,
- OUT SCAN_TIMINGS **Horizontal,
- OUT SCAN_TIMINGS **Vertical
+ IN UINT32 ModeNumber,
+ OUT SCAN_TIMINGS **Horizontal,
+ OUT SCAN_TIMINGS **Vertical
)
{
ASSERT (FALSE);
@@ -136,8 +136,8 @@ LcdPlatformGetTimings ( **/
EFI_STATUS
LcdPlatformGetBpp (
- IN UINT32 ModeNumber,
- OUT LCD_BPP* Bpp
+ IN UINT32 ModeNumber,
+ OUT LCD_BPP *Bpp
)
{
ASSERT (FALSE);
diff --git a/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.c b/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.c index 1237f93827..6e11b23fdb 100644 --- a/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.c +++ b/ArmPlatformPkg/Library/NorFlashPlatformNullLib/NorFlashPlatformNullLib.c @@ -18,11 +18,11 @@ NorFlashPlatformInitialization ( EFI_STATUS
NorFlashPlatformGetDevices (
- OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
- OUT UINT32 *Count
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
+ OUT UINT32 *Count
)
{
*NorFlashDescriptions = NULL;
- *Count = 0;
+ *Count = 0;
return EFI_SUCCESS;
}
diff --git a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c index a552e6ab9b..ae329c3f83 100644 --- a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c +++ b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c @@ -35,15 +35,15 @@ SerialPortInitialize ( UINT8 DataBits;
EFI_STOP_BITS_TYPE StopBits;
- BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
ReceiveFifoDepth = 0; // Use default FIFO depth
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
- StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
return PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase),
- PL011UartClockGetFreq(),
+ PL011UartClockGetFreq (),
&BaudRate,
&ReceiveFifoDepth,
&Parity,
@@ -65,8 +65,8 @@ SerialPortInitialize ( UINTN
EFIAPI
SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
)
{
return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
@@ -85,9 +85,9 @@ SerialPortWrite ( UINTN
EFIAPI
SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
}
@@ -107,6 +107,7 @@ SerialPortPoll ( {
return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase));
}
+
/**
Set new attributes to PL011.
@@ -151,7 +152,7 @@ SerialPortSetAttributes ( {
return PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase),
- PL011UartClockGetFreq(),
+ PL011UartClockGetFreq (),
BaudRate,
ReceiveFifoDepth,
Parity,
diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h b/ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h index 000fd6578f..8433a81aea 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011Uart.h @@ -9,106 +9,106 @@ #ifndef __PL011_UART_H__
#define __PL011_UART_H__
-#define PL011_VARIANT_ZTE 1
+#define PL011_VARIANT_ZTE 1
// PL011 Registers
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
-#define UARTDR 0x004
-#define UARTRSR 0x010
-#define UARTECR 0x010
-#define UARTFR 0x014
-#define UARTIBRD 0x024
-#define UARTFBRD 0x028
-#define UARTLCR_H 0x030
-#define UARTCR 0x034
-#define UARTIFLS 0x038
-#define UARTIMSC 0x040
-#define UARTRIS 0x044
-#define UARTMIS 0x048
-#define UARTICR 0x04c
-#define UARTDMACR 0x050
+#define UARTDR 0x004
+#define UARTRSR 0x010
+#define UARTECR 0x010
+#define UARTFR 0x014
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR_H 0x030
+#define UARTCR 0x034
+#define UARTIFLS 0x038
+#define UARTIMSC 0x040
+#define UARTRIS 0x044
+#define UARTMIS 0x048
+#define UARTICR 0x04c
+#define UARTDMACR 0x050
#else
-#define UARTDR 0x000
-#define UARTRSR 0x004
-#define UARTECR 0x004
-#define UARTFR 0x018
-#define UARTILPR 0x020
-#define UARTIBRD 0x024
-#define UARTFBRD 0x028
-#define UARTLCR_H 0x02C
-#define UARTCR 0x030
-#define UARTIFLS 0x034
-#define UARTIMSC 0x038
-#define UARTRIS 0x03C
-#define UARTMIS 0x040
-#define UARTICR 0x044
-#define UARTDMACR 0x048
+#define UARTDR 0x000
+#define UARTRSR 0x004
+#define UARTECR 0x004
+#define UARTFR 0x018
+#define UARTILPR 0x020
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR_H 0x02C
+#define UARTCR 0x030
+#define UARTIFLS 0x034
+#define UARTIMSC 0x038
+#define UARTRIS 0x03C
+#define UARTMIS 0x040
+#define UARTICR 0x044
+#define UARTDMACR 0x048
#endif
-#define UARTPID0 0xFE0
-#define UARTPID1 0xFE4
-#define UARTPID2 0xFE8
-#define UARTPID3 0xFEC
+#define UARTPID0 0xFE0
+#define UARTPID1 0xFE4
+#define UARTPID2 0xFE8
+#define UARTPID3 0xFEC
// Data status bits
-#define UART_DATA_ERROR_MASK 0x0F00
+#define UART_DATA_ERROR_MASK 0x0F00
// Status reg bits
-#define UART_STATUS_ERROR_MASK 0x0F
+#define UART_STATUS_ERROR_MASK 0x0F
// Flag reg bits
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE
-#define PL011_UARTFR_RI (1 << 0) // Ring indicator
-#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
-#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
-#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
-#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
-#define PL011_UARTFR_BUSY (1 << 8) // UART busy
-#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
-#define PL011_UARTFR_DSR (1 << 3) // Data set ready
-#define PL011_UARTFR_CTS (1 << 1) // Clear to send
+#define PL011_UARTFR_RI (1 << 0) // Ring indicator
+#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
+#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
+#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
+#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
+#define PL011_UARTFR_BUSY (1 << 8) // UART busy
+#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
+#define PL011_UARTFR_DSR (1 << 3) // Data set ready
+#define PL011_UARTFR_CTS (1 << 1) // Clear to send
#else
-#define PL011_UARTFR_RI (1 << 8) // Ring indicator
-#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
-#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
-#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
-#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
-#define PL011_UARTFR_BUSY (1 << 3) // UART busy
-#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
-#define PL011_UARTFR_DSR (1 << 1) // Data set ready
-#define PL011_UARTFR_CTS (1 << 0) // Clear to send
+#define PL011_UARTFR_RI (1 << 8) // Ring indicator
+#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty
+#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full
+#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full
+#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty
+#define PL011_UARTFR_BUSY (1 << 3) // UART busy
+#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect
+#define PL011_UARTFR_DSR (1 << 1) // Data set ready
+#define PL011_UARTFR_CTS (1 << 0) // Clear to send
#endif
// Flag reg bits - alternative names
-#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
-#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
-#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
-#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
-#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
+#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE
+#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF
+#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF
+#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE
+#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY
// Control reg bits
-#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
-#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
-#define PL011_UARTCR_RTS (1 << 11) // Request to send
-#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
-#define PL011_UARTCR_RXE (1 << 9) // Receive enable
-#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
-#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
-#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
+#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
+#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
+#define PL011_UARTCR_RTS (1 << 11) // Request to send
+#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
+#define PL011_UARTCR_RXE (1 << 9) // Receive enable
+#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
+#define PL011_UARTCR_LBE (1 << 7) // Loopback enable
+#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
// Line Control Register Bits
-#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
-#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
-#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
-#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
-#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
-#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
-#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
-#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
-#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
-#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
+#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
+#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
+#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
+#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
+#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
+#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
+#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
+#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
+#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
+#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
-#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
-#define PL011_VER_R1P4 0x2
+#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
+#define PL011_VER_R1P4 0x2
#endif
diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c index 3c58a0f39a..60f9bc5fb0 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -25,7 +25,7 @@ // EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE is the only
// control bit that is not supported.
//
-STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
+STATIC CONST UINT32 mInvalidControlBits = EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;
/**
@@ -73,16 +73,16 @@ PL011UartInitializePort ( IN OUT EFI_STOP_BITS_TYPE *StopBits
)
{
- UINT32 LineControl;
- UINT32 Divisor;
- UINT32 Integer;
- UINT32 Fractional;
- UINT32 HardwareFifoDepth;
- UINT32 UartPid2;
+ UINT32 LineControl;
+ UINT32 Divisor;
+ UINT32 Integer;
+ UINT32 Fractional;
+ UINT32 HardwareFifoDepth;
+ UINT32 UartPid2;
HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
if (HardwareFifoDepth == 0) {
- UartPid2 = MmioRead32 (UartBase + UARTPID2);
+ UartPid2 = MmioRead32 (UartBase + UARTPID2);
HardwareFifoDepth = (PL011_UARTPID2_VER (UartPid2) > PL011_VER_R1P4) ? 32 : 16;
}
@@ -91,7 +91,7 @@ PL011UartInitializePort ( // down, there is no maximum FIFO size.
if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
// Enable FIFO
- LineControl = PL011_UARTLCR_H_FEN;
+ LineControl = PL011_UARTLCR_H_FEN;
*ReceiveFifoDepth = HardwareFifoDepth;
} else {
// Disable FIFO
@@ -104,67 +104,67 @@ PL011UartInitializePort ( // Parity
//
switch (*Parity) {
- case DefaultParity:
- *Parity = NoParity;
- case NoParity:
- // Nothing to do. Parity is disabled by default.
- break;
- case EvenParity:
- LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
- break;
- case OddParity:
- LineControl |= PL011_UARTLCR_H_PEN;
- break;
- case MarkParity:
- LineControl |= ( PL011_UARTLCR_H_PEN \
- | PL011_UARTLCR_H_SPS \
- | PL011_UARTLCR_H_EPS);
- break;
- case SpaceParity:
- LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
- break;
- default:
- return RETURN_INVALID_PARAMETER;
+ case DefaultParity:
+ *Parity = NoParity;
+ case NoParity:
+ // Nothing to do. Parity is disabled by default.
+ break;
+ case EvenParity:
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);
+ break;
+ case OddParity:
+ LineControl |= PL011_UARTLCR_H_PEN;
+ break;
+ case MarkParity:
+ LineControl |= (PL011_UARTLCR_H_PEN \
+ | PL011_UARTLCR_H_SPS \
+ | PL011_UARTLCR_H_EPS);
+ break;
+ case SpaceParity:
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);
+ break;
+ default:
+ return RETURN_INVALID_PARAMETER;
}
//
// Data Bits
//
switch (*DataBits) {
- case 0:
- *DataBits = 8;
- case 8:
- LineControl |= PL011_UARTLCR_H_WLEN_8;
- break;
- case 7:
- LineControl |= PL011_UARTLCR_H_WLEN_7;
- break;
- case 6:
- LineControl |= PL011_UARTLCR_H_WLEN_6;
- break;
- case 5:
- LineControl |= PL011_UARTLCR_H_WLEN_5;
- break;
- default:
- return RETURN_INVALID_PARAMETER;
+ case 0:
+ *DataBits = 8;
+ case 8:
+ LineControl |= PL011_UARTLCR_H_WLEN_8;
+ break;
+ case 7:
+ LineControl |= PL011_UARTLCR_H_WLEN_7;
+ break;
+ case 6:
+ LineControl |= PL011_UARTLCR_H_WLEN_6;
+ break;
+ case 5:
+ LineControl |= PL011_UARTLCR_H_WLEN_5;
+ break;
+ default:
+ return RETURN_INVALID_PARAMETER;
}
//
// Stop Bits
//
switch (*StopBits) {
- case DefaultStopBits:
- *StopBits = OneStopBit;
- case OneStopBit:
- // Nothing to do. One stop bit is enabled by default.
- break;
- case TwoStopBits:
- LineControl |= PL011_UARTLCR_H_STP2;
- break;
- case OneFiveStopBits:
+ case DefaultStopBits:
+ *StopBits = OneStopBit;
+ case OneStopBit:
+ // Nothing to do. One stop bit is enabled by default.
+ break;
+ case TwoStopBits:
+ LineControl |= PL011_UARTLCR_H_STP2;
+ break;
+ case OneFiveStopBits:
// Only 1 or 2 stop bits are supported
- default:
- return RETURN_INVALID_PARAMETER;
+ default:
+ return RETURN_INVALID_PARAMETER;
}
// Don't send the LineControl value to the PL011 yet,
@@ -178,7 +178,7 @@ PL011UartInitializePort ( // If PL011 Integer value has been defined then always ignore the BAUD rate
if (FixedPcdGet32 (PL011UartInteger) != 0) {
- Integer = FixedPcdGet32 (PL011UartInteger);
+ Integer = FixedPcdGet32 (PL011UartInteger);
Fractional = FixedPcdGet32 (PL011UartFractional);
} else {
// If BAUD rate is zero then replace it with the system default value
@@ -188,12 +188,13 @@ PL011UartInitializePort ( return RETURN_INVALID_PARAMETER;
}
}
+
if (0 == UartClkInHz) {
return RETURN_INVALID_PARAMETER;
}
- Divisor = (UartClkInHz * 4) / *BaudRate;
- Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
+ Divisor = (UartClkInHz * 4) / *BaudRate;
+ Integer = Divisor >> FRACTION_PART_SIZE_IN_BITS;
Fractional = Divisor & FRACTION_PART_MASK;
}
@@ -202,15 +203,17 @@ PL011UartInitializePort ( // and re-initialize only if the settings are different.
//
if (((MmioRead32 (UartBase + UARTCR) & PL011_UARTCR_UARTEN) != 0) &&
- (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
- (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
- (MmioRead32 (UartBase + UARTFBRD) == Fractional)) {
+ (MmioRead32 (UartBase + UARTLCR_H) == LineControl) &&
+ (MmioRead32 (UartBase + UARTIBRD) == Integer) &&
+ (MmioRead32 (UartBase + UARTFBRD) == Fractional))
+ {
// Nothing to do - already initialized with correct attributes
return RETURN_SUCCESS;
}
// Wait for the end of transmission
- while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0);
+ while ((MmioRead32 (UartBase + UARTFR) & PL011_UARTFR_TXFE) == 0) {
+ }
// Disable UART: "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must not be changed
// when the UART is enabled"
@@ -227,8 +230,10 @@ PL011UartInitializePort ( MmioWrite32 (UartBase + UARTECR, 0);
// Enable Tx, Rx, and UART overall
- MmioWrite32 (UartBase + UARTCR,
- PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
+ MmioWrite32 (
+ UartBase + UARTCR,
+ PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN
+ );
return RETURN_SUCCESS;
}
@@ -263,8 +268,8 @@ PL011UartInitializePort ( RETURN_STATUS
EFIAPI
PL011UartSetControl (
- IN UINTN UartBase,
- IN UINT32 Control
+ IN UINTN UartBase,
+ IN UINT32 Control
)
{
UINT32 Bits;
@@ -340,15 +345,14 @@ PL011UartSetControl ( RETURN_STATUS
EFIAPI
PL011UartGetControl (
- IN UINTN UartBase,
- OUT UINT32 *Control
+ IN UINTN UartBase,
+ OUT UINT32 *Control
)
{
- UINT32 FlagRegister;
- UINT32 ControlRegister;
+ UINT32 FlagRegister;
+ UINT32 ControlRegister;
-
- FlagRegister = MmioRead32 (UartBase + UARTFR);
+ FlagRegister = MmioRead32 (UartBase + UARTFR);
ControlRegister = MmioRead32 (UartBase + UARTCR);
*Control = 0;
@@ -386,7 +390,8 @@ PL011UartGetControl ( }
if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
- == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {
+ == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN))
+ {
*Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
@@ -410,16 +415,17 @@ PL011UartGetControl ( UINTN
EFIAPI
PL011UartWrite (
- IN UINTN UartBase,
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
+ IN UINTN UartBase,
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
)
{
- UINT8* CONST Final = &Buffer[NumberOfBytes];
+ UINT8 *CONST Final = &Buffer[NumberOfBytes];
while (Buffer < Final) {
// Wait until UART able to accept another char
- while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK));
+ while ((MmioRead32 (UartBase + UARTFR) & UART_TX_FULL_FLAG_MASK)) {
+ }
MmioWrite8 (UartBase + UARTDR, *Buffer++);
}
@@ -440,15 +446,17 @@ PL011UartWrite ( UINTN
EFIAPI
PL011UartRead (
- IN UINTN UartBase,
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
+ IN UINTN UartBase,
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
)
{
- UINTN Count;
+ UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
- while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
+ while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0) {
+ }
+
*Buffer = MmioRead8 (UartBase + UARTDR);
}
@@ -465,7 +473,7 @@ PL011UartRead ( BOOLEAN
EFIAPI
PL011UartPoll (
- IN UINTN UartBase
+ IN UINTN UartBase
)
{
return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h index 6112a42638..00b3fc99ac 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClock.h @@ -6,34 +6,33 @@ **/
-
#ifndef __PL031_REAL_TIME_CLOCK_H__
#define __PL031_REAL_TIME_CLOCK_H__
// PL031 Registers
-#define PL031_RTC_DR_DATA_REGISTER 0x000
-#define PL031_RTC_MR_MATCH_REGISTER 0x004
-#define PL031_RTC_LR_LOAD_REGISTER 0x008
-#define PL031_RTC_CR_CONTROL_REGISTER 0x00C
-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
-#define PL031_RTC_PERIPH_ID0 0xFE0
-#define PL031_RTC_PERIPH_ID1 0xFE4
-#define PL031_RTC_PERIPH_ID2 0xFE8
-#define PL031_RTC_PERIPH_ID3 0xFEC
-#define PL031_RTC_PCELL_ID0 0xFF0
-#define PL031_RTC_PCELL_ID1 0xFF4
-#define PL031_RTC_PCELL_ID2 0xFF8
-#define PL031_RTC_PCELL_ID3 0xFFC
+#define PL031_RTC_DR_DATA_REGISTER 0x000
+#define PL031_RTC_MR_MATCH_REGISTER 0x004
+#define PL031_RTC_LR_LOAD_REGISTER 0x008
+#define PL031_RTC_CR_CONTROL_REGISTER 0x00C
+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010
+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014
+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018
+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C
+#define PL031_RTC_PERIPH_ID0 0xFE0
+#define PL031_RTC_PERIPH_ID1 0xFE4
+#define PL031_RTC_PERIPH_ID2 0xFE8
+#define PL031_RTC_PERIPH_ID3 0xFEC
+#define PL031_RTC_PCELL_ID0 0xFF0
+#define PL031_RTC_PCELL_ID1 0xFF4
+#define PL031_RTC_PCELL_ID2 0xFF8
+#define PL031_RTC_PCELL_ID3 0xFFC
// PL031 Values
-#define PL031_RTC_ENABLED 0x00000001
-#define PL031_SET_IRQ_MASK 0x00000001
-#define PL031_IRQ_TRIGGERED 0x00000001
-#define PL031_CLEAR_IRQ 0x00000001
+#define PL031_RTC_ENABLED 0x00000001
+#define PL031_SET_IRQ_MASK 0x00000001
+#define PL031_IRQ_TRIGGERED 0x00000001
+#define PL031_CLEAR_IRQ 0x00000001
-#define PL031_COUNTS_PER_SECOND 1
+#define PL031_COUNTS_PER_SECOND 1
#endif
diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index 3afef4bf9a..a203299c06 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -31,38 +31,40 @@ #include "PL031RealTimeClock.h"
-STATIC BOOLEAN mPL031Initialized = FALSE;
-STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
-STATIC UINTN mPL031RtcBase;
+STATIC BOOLEAN mPL031Initialized = FALSE;
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+STATIC UINTN mPL031RtcBase;
EFI_STATUS
IdentifyPL031 (
VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
// Check if this is a PrimeCell Peripheral
if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID0) != 0x0D)
- || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID1) != 0xF0)
- || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID2) != 0x05)
- || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID3) != 0xB1)) {
+ || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID1) != 0xF0)
+ || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID2) != 0x05)
+ || (MmioRead8 (mPL031RtcBase + PL031_RTC_PCELL_ID3) != 0xB1))
+ {
Status = EFI_NOT_FOUND;
goto EXIT;
}
// Check if this PrimeCell Peripheral is the PL031 Real Time Clock
if ( (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID0) != 0x31)
- || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID1) != 0x10)
- || ((MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
- || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID3) != 0x00)) {
+ || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID1) != 0x10)
+ || ((MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
+ || (MmioRead8 (mPL031RtcBase + PL031_RTC_PERIPH_ID3) != 0x00))
+ {
Status = EFI_NOT_FOUND;
goto EXIT;
}
Status = EFI_SUCCESS;
- EXIT:
+EXIT:
return Status;
}
@@ -71,10 +73,10 @@ InitializePL031 ( VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
// Prepare the hardware
- Status = IdentifyPL031();
+ Status = IdentifyPL031 ();
if (EFI_ERROR (Status)) {
goto EXIT;
}
@@ -96,7 +98,7 @@ InitializePL031 ( mPL031Initialized = TRUE;
- EXIT:
+EXIT:
return Status;
}
@@ -117,8 +119,8 @@ InitializePL031 ( EFI_STATUS
EFIAPI
LibGetTime (
- OUT EFI_TIME *Time,
- OUT EFI_TIME_CAPABILITIES *Capabilities
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
)
{
EFI_STATUS Status;
@@ -154,17 +156,16 @@ LibGetTime ( // Update the Capabilities info
if (Capabilities != NULL) {
// PL031 runs at frequency 1Hz
- Capabilities->Resolution = PL031_COUNTS_PER_SECOND;
+ Capabilities->Resolution = PL031_COUNTS_PER_SECOND;
// Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
- Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);
+ Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);
// FALSE: Setting the time does not clear the values below the resolution level
- Capabilities->SetsToZero = FALSE;
+ Capabilities->SetsToZero = FALSE;
}
return EFI_SUCCESS;
}
-
/**
Sets the current local time and date information.
@@ -178,7 +179,7 @@ LibGetTime ( EFI_STATUS
EFIAPI
LibSetTime (
- IN EFI_TIME *Time
+ IN EFI_TIME *Time
)
{
EFI_STATUS Status;
@@ -217,7 +218,6 @@ LibSetTime ( return EFI_SUCCESS;
}
-
/**
Returns the current wakeup alarm clock setting.
@@ -233,16 +233,15 @@ LibSetTime ( EFI_STATUS
EFIAPI
LibGetWakeupTime (
- OUT BOOLEAN *Enabled,
- OUT BOOLEAN *Pending,
- OUT EFI_TIME *Time
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
)
{
// Not a required feature
return EFI_UNSUPPORTED;
}
-
/**
Sets the system wakeup alarm clock time.
@@ -259,8 +258,8 @@ LibGetWakeupTime ( EFI_STATUS
EFIAPI
LibSetWakeupTime (
- IN BOOLEAN Enabled,
- OUT EFI_TIME *Time
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
)
{
// Not a required feature
@@ -278,8 +277,8 @@ LibSetWakeupTime ( VOID
EFIAPI
LibRtcVirtualNotifyEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
//
@@ -288,7 +287,7 @@ LibRtcVirtualNotifyEvent ( // to virtual address. After the OS transitions to calling in virtual mode, all future
// runtime calls will be made in virtual mode.
//
- EfiConvertPointer (0x0, (VOID**)&mPL031RtcBase);
+ EfiConvertPointer (0x0, (VOID **)&mPL031RtcBase);
return;
}
@@ -305,12 +304,12 @@ LibRtcVirtualNotifyEvent ( EFI_STATUS
EFIAPI
LibRtcInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HANDLE Handle;
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
// Initialize RTC Base Address
mPL031RtcBase = PcdGet32 (PcdPL031RtcBase);
@@ -318,7 +317,8 @@ LibRtcInitialize ( // Declare the controller as EFI_MEMORY_RUNTIME
Status = gDS->AddMemorySpace (
EfiGcdMemoryTypeMemoryMappedIo,
- mPL031RtcBase, SIZE_4KB,
+ mPL031RtcBase,
+ SIZE_4KB,
EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
);
if (EFI_ERROR (Status)) {
@@ -334,9 +334,10 @@ LibRtcInitialize ( Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
- &gEfiRealTimeClockArchProtocolGuid, NULL,
+ &gEfiRealTimeClockArchProtocolGuid,
+ NULL,
NULL
- );
+ );
ASSERT_EFI_ERROR (Status);
//
diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c index b519202573..07f9b0f6be 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -26,20 +26,25 @@ LcdIdentify ( VOID
)
{
- DEBUG ((DEBUG_WARN, "Probing ID registers at 0x%lx for a PL111\n",
- PL111_REG_CLCD_PERIPH_ID_0));
+ DEBUG ((
+ DEBUG_WARN,
+ "Probing ID registers at 0x%lx for a PL111\n",
+ PL111_REG_CLCD_PERIPH_ID_0
+ ));
// Check if this is a PL111
- if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&
- MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&
- (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&
- MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&
- MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {
+ if ((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0) &&
+ (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1) &&
+ ((MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2) &&
+ (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3) &&
+ (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0) &&
+ (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1) &&
+ (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2) &&
+ (MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3))
+ {
return EFI_SUCCESS;
}
+
return EFI_NOT_FOUND;
}
@@ -51,7 +56,7 @@ LcdIdentify ( **/
EFI_STATUS
LcdInitialize (
- IN EFI_PHYSICAL_ADDRESS VramBaseAddress
+ IN EFI_PHYSICAL_ADDRESS VramBaseAddress
)
{
// Define start of the VRAM. This never changes for any graphics mode
@@ -76,11 +81,11 @@ LcdSetMode ( IN UINT32 ModeNumber
)
{
- EFI_STATUS Status;
- SCAN_TIMINGS *Horizontal;
- SCAN_TIMINGS *Vertical;
- UINT32 LcdControl;
- LCD_BPP LcdBpp;
+ EFI_STATUS Status;
+ SCAN_TIMINGS *Horizontal;
+ SCAN_TIMINGS *Vertical;
+ UINT32 LcdControl;
+ LCD_BPP LcdBpp;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;
@@ -148,6 +153,7 @@ LcdSetMode ( if (ModeInfo.PixelFormat == PixelBlueGreenRedReserved8BitPerColor) {
LcdControl |= PL111_CTRL_BGR;
}
+
MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
return EFI_SUCCESS;
diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h index fabf778c19..0d4fe387c5 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h @@ -16,39 +16,39 @@ **********************************************************************/
// Controller Register Offsets
-#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
-#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
-#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
-#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
-#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
-#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
-#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
-#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
-#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
-#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
-#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
-#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
-#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
-#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
+#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
+#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
+#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
+#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
+#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
+#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
+#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
+#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
+#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
+#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
+#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
+#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
+#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
+#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
// Identification Register Offsets
-#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
-#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
-#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
-#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
-#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
-#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
-#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
-#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
-
-#define PL111_CLCD_PERIPH_ID_0 0x11
-#define PL111_CLCD_PERIPH_ID_1 0x11
-#define PL111_CLCD_PERIPH_ID_2 0x04
-#define PL111_CLCD_PERIPH_ID_3 0x00
-#define PL111_CLCD_P_CELL_ID_0 0x0D
-#define PL111_CLCD_P_CELL_ID_1 0xF0
-#define PL111_CLCD_P_CELL_ID_2 0x05
-#define PL111_CLCD_P_CELL_ID_3 0xB1
+#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
+#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
+#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
+#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
+#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
+#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
+#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
+#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
+
+#define PL111_CLCD_PERIPH_ID_0 0x11
+#define PL111_CLCD_PERIPH_ID_1 0x11
+#define PL111_CLCD_PERIPH_ID_2 0x04
+#define PL111_CLCD_PERIPH_ID_3 0x00
+#define PL111_CLCD_P_CELL_ID_0 0x0D
+#define PL111_CLCD_P_CELL_ID_1 0xF0
+#define PL111_CLCD_P_CELL_ID_2 0x05
+#define PL111_CLCD_P_CELL_ID_3 0xB1
/**********************************************************************/
@@ -61,83 +61,83 @@ /**********************************************************************/
// Register: PL111_REG_LCD_TIMING_0
-#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
+#define HOR_AXIS_PANEL(hbp, hfp, hsw, hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
// Register: PL111_REG_LCD_TIMING_1
-#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
+#define VER_AXIS_PANEL(vbp, vfp, vsw, ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
// Register: PL111_REG_LCD_TIMING_2
-#define PL111_BIT_SHIFT_PCD_HI 27
-#define PL111_BIT_SHIFT_BCD 26
-#define PL111_BIT_SHIFT_CPL 16
-#define PL111_BIT_SHIFT_IOE 14
-#define PL111_BIT_SHIFT_IPC 13
-#define PL111_BIT_SHIFT_IHS 12
-#define PL111_BIT_SHIFT_IVS 11
-#define PL111_BIT_SHIFT_ACB 6
-#define PL111_BIT_SHIFT_CLKSEL 5
-#define PL111_BIT_SHIFT_PCD_LO 0
-
-#define PL111_BCD (1 << 26)
-#define PL111_IPC (1 << 13)
-#define PL111_IHS (1 << 12)
-#define PL111_IVS (1 << 11)
-
-#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
+#define PL111_BIT_SHIFT_PCD_HI 27
+#define PL111_BIT_SHIFT_BCD 26
+#define PL111_BIT_SHIFT_CPL 16
+#define PL111_BIT_SHIFT_IOE 14
+#define PL111_BIT_SHIFT_IPC 13
+#define PL111_BIT_SHIFT_IHS 12
+#define PL111_BIT_SHIFT_IVS 11
+#define PL111_BIT_SHIFT_ACB 6
+#define PL111_BIT_SHIFT_CLKSEL 5
+#define PL111_BIT_SHIFT_PCD_LO 0
+
+#define PL111_BCD (1 << 26)
+#define PL111_IPC (1 << 13)
+#define PL111_IHS (1 << 12)
+#define PL111_IVS (1 << 11)
+
+#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
// Register: PL111_REG_LCD_TIMING_3
-#define PL111_BIT_SHIFT_LEE 16
-#define PL111_BIT_SHIFT_LED 0
-
-#define PL111_CTRL_WATERMARK (1 << 16)
-#define PL111_CTRL_LCD_V_COMP (1 << 12)
-#define PL111_CTRL_LCD_PWR (1 << 11)
-#define PL111_CTRL_BEPO (1 << 10)
-#define PL111_CTRL_BEBO (1 << 9)
-#define PL111_CTRL_BGR (1 << 8)
-#define PL111_CTRL_LCD_DUAL (1 << 7)
-#define PL111_CTRL_LCD_MONO_8 (1 << 6)
-#define PL111_CTRL_LCD_TFT (1 << 5)
-#define PL111_CTRL_LCD_BW (1 << 4)
-#define PL111_CTRL_LCD_1BPP (0 << 1)
-#define PL111_CTRL_LCD_2BPP (1 << 1)
-#define PL111_CTRL_LCD_4BPP (2 << 1)
-#define PL111_CTRL_LCD_8BPP (3 << 1)
-#define PL111_CTRL_LCD_16BPP (4 << 1)
-#define PL111_CTRL_LCD_24BPP (5 << 1)
-#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
-#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
-#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
-#define PL111_CTRL_LCD_EN 1
+#define PL111_BIT_SHIFT_LEE 16
+#define PL111_BIT_SHIFT_LED 0
+
+#define PL111_CTRL_WATERMARK (1 << 16)
+#define PL111_CTRL_LCD_V_COMP (1 << 12)
+#define PL111_CTRL_LCD_PWR (1 << 11)
+#define PL111_CTRL_BEPO (1 << 10)
+#define PL111_CTRL_BEBO (1 << 9)
+#define PL111_CTRL_BGR (1 << 8)
+#define PL111_CTRL_LCD_DUAL (1 << 7)
+#define PL111_CTRL_LCD_MONO_8 (1 << 6)
+#define PL111_CTRL_LCD_TFT (1 << 5)
+#define PL111_CTRL_LCD_BW (1 << 4)
+#define PL111_CTRL_LCD_1BPP (0 << 1)
+#define PL111_CTRL_LCD_2BPP (1 << 1)
+#define PL111_CTRL_LCD_4BPP (2 << 1)
+#define PL111_CTRL_LCD_8BPP (3 << 1)
+#define PL111_CTRL_LCD_16BPP (4 << 1)
+#define PL111_CTRL_LCD_24BPP (5 << 1)
+#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
+#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
+#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
+#define PL111_CTRL_LCD_EN 1
/**********************************************************************/
// Register: PL111_REG_LCD_TIMING_0
-#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
-#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
-#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
-#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
+#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
+#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
+#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
+#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
// Register: PL111_REG_LCD_TIMING_1
-#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
-#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
-#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
-#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
+#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
+#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
+#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
+#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
// Register: PL111_REG_LCD_TIMING_2
-#define PL111_BIT_MASK_PCD_HI 0xF8000000
-#define PL111_BIT_MASK_BCD 0x04000000
-#define PL111_BIT_MASK_CPL 0x03FF0000
-#define PL111_BIT_MASK_IOE 0x00004000
-#define PL111_BIT_MASK_IPC 0x00002000
-#define PL111_BIT_MASK_IHS 0x00001000
-#define PL111_BIT_MASK_IVS 0x00000800
-#define PL111_BIT_MASK_ACB 0x000007C0
-#define PL111_BIT_MASK_CLKSEL 0x00000020
-#define PL111_BIT_MASK_PCD_LO 0x0000001F
+#define PL111_BIT_MASK_PCD_HI 0xF8000000
+#define PL111_BIT_MASK_BCD 0x04000000
+#define PL111_BIT_MASK_CPL 0x03FF0000
+#define PL111_BIT_MASK_IOE 0x00004000
+#define PL111_BIT_MASK_IPC 0x00002000
+#define PL111_BIT_MASK_IHS 0x00001000
+#define PL111_BIT_MASK_IVS 0x00000800
+#define PL111_BIT_MASK_ACB 0x000007C0
+#define PL111_BIT_MASK_CLKSEL 0x00000020
+#define PL111_BIT_MASK_PCD_LO 0x0000001F
// Register: PL111_REG_LCD_TIMING_3
-#define PL111_BIT_MASK_LEE 0x00010000
-#define PL111_BIT_MASK_LED 0x0000007F
+#define PL111_BIT_MASK_LEE 0x00010000
+#define PL111_BIT_MASK_LED 0x0000007F
#endif /* _PL111LCD_H__ */
diff --git a/ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointer.c b/ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointer.c index fe70be56d5..5b0b31b144 100644 --- a/ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointer.c +++ b/ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointer.c @@ -25,11 +25,9 @@ PrePeiGetHobList ( VOID
)
{
- return (VOID *)ArmReadTpidrurw();
+ return (VOID *)ArmReadTpidrurw ();
}
-
-
/**
Updates the pointer to the HOB list.
@@ -39,10 +37,10 @@ PrePeiGetHobList ( EFI_STATUS
EFIAPI
PrePeiSetHobList (
- IN VOID *HobList
+ IN VOID *HobList
)
{
- ArmWriteTpidrurw((UINTN)HobList);
+ ArmWriteTpidrurw ((UINTN)HobList);
return EFI_SUCCESS;
}
|