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-rw-r--r--ArmPlatformPkg/Library/HdLcd/HdLcd.c88
-rw-r--r--ArmPlatformPkg/Library/HdLcd/HdLcd.h21
-rw-r--r--ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c64
3 files changed, 98 insertions, 75 deletions
diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/HdLcd/HdLcd.c
index 24efb68f23..2cd1be9d25 100644
--- a/ArmPlatformPkg/Library/HdLcd/HdLcd.c
+++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c
@@ -1,6 +1,6 @@
-/** @file Lcd.c
+/** @file
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -21,12 +21,9 @@
#include "HdLcd.h"
-/**********************************************************************
- *
- * This file contains all the bits of the Lcd that are
- * platform independent.
- *
- **********************************************************************/
+/** This file contains all the bits of the Lcd that are
+ platform independent.
+**/
STATIC
UINTN
@@ -34,7 +31,7 @@ GetBytesPerPixel (
IN LCD_BPP Bpp
)
{
- switch(Bpp) {
+ switch (Bpp) {
case LCD_BITS_PER_PIXEL_24:
return 4;
@@ -60,21 +57,27 @@ LcdInitialize (
)
{
// Disable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
// Disable all interrupts
- MmioWrite32(HDLCD_REG_INT_MASK, 0);
+ MmioWrite32 (HDLCD_REG_INT_MASK, 0);
// Define start of the VRAM. This never changes for any graphics mode
- MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
+ MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);
// Setup various registers that never change
- MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
- MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
- MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
- MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
- MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
- MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
+ MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
+
+ MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);
+
+ MmioWrite32 (
+ HDLCD_REG_PIXEL_FORMAT,
+ HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL
+ );
+
+ MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
+ MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
+ MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
return EFI_SUCCESS;
}
@@ -96,46 +99,53 @@ LcdSetMode (
UINT32 BytesPerPixel;
LCD_BPP LcdBpp;
-
// Set the video mode timings and other relevant information
- Status = LcdPlatformGetTimings (ModeNumber,
- &HRes,&HSync,&HBackPorch,&HFrontPorch,
- &VRes,&VSync,&VBackPorch,&VFrontPorch);
+ Status = LcdPlatformGetTimings (
+ ModeNumber,
+ &HRes,
+ &HSync,
+ &HBackPorch,
+ &HFrontPorch,
+ &VRes,
+ &VSync,
+ &VBackPorch,
+ &VFrontPorch
+ );
ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
+ if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
- Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
+ Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
+ if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
- BytesPerPixel = GetBytesPerPixel(LcdBpp);
+ BytesPerPixel = GetBytesPerPixel (LcdBpp);
// Disable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);
// Update the frame buffer information with the new settings
- MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
- MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
- MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);
+ MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
+ MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
+ MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1);
// Set the vertical timing information
- MmioWrite32(HDLCD_REG_V_SYNC, VSync);
- MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);
- MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);
- MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
+ MmioWrite32 (HDLCD_REG_V_SYNC, VSync);
+ MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch);
+ MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1);
+ MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
// Set the horizontal timing information
- MmioWrite32(HDLCD_REG_H_SYNC, HSync);
- MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);
- MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);
- MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
+ MmioWrite32 (HDLCD_REG_H_SYNC, HSync);
+ MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch);
+ MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1);
+ MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
// Enable the controller
- MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);
+ MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE);
return EFI_SUCCESS;
}
diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/HdLcd/HdLcd.h
index 6df97a9dfe..cd2c0366c7 100644
--- a/ArmPlatformPkg/Library/HdLcd/HdLcd.h
+++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h
@@ -1,6 +1,6 @@
-/** @file HDLcd.h
+/** @file
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -12,13 +12,10 @@
**/
-#ifndef _HDLCD_H_
-#define _HDLCD_H_
+#ifndef HDLCD_H_
+#define HDLCD_H_
-//
// HDLCD Controller Register Offsets
-//
-
#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
@@ -44,10 +41,7 @@
#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
-
-//
// HDLCD Values of registers
-//
// HDLCD Interrupt mask, clear and status register
#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
@@ -79,6 +73,11 @@
#define HDLCD_DATA_LOW 0
#define HDLCD_PXCLK_LOW 0
+// Default polarities
+#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | \
+ HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | \
+ HDLCD_VSYNC_HIGH)
+
// Pixel Format
#define HDLCD_LITTLE_ENDIAN (0 << 31)
#define HDLCD_BIG_ENDIAN (1 << 31)
@@ -86,4 +85,4 @@
// Number of bytes per pixel
#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
-#endif /* _HDLCD_H_ */
+#endif /* HDLCD_H_ */
diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c
index 9b4a02045a..3f3f7019f1 100644
--- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c
+++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c
@@ -1,6 +1,6 @@
-/** @file PL111Lcd.c
+/** @file
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -19,13 +19,10 @@
#include "PL111Lcd.h"
-/**********************************************************************
- *
- * This file contains all the bits of the PL111 that are
- * platform independent.
- *
- **********************************************************************/
+/** This file contains all the bits of the PL111 that are
+ platform independent.
+**/
EFI_STATUS
LcdIdentify (
VOID
@@ -54,11 +51,11 @@ LcdInitialize (
)
{
// Define start of the VRAM. This never changes for any graphics mode
- MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);
- MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
+ MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);
+ MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
// Disable all interrupts from the PL111
- MmioWrite32(PL111_REG_LCD_IMSC, 0);
+ MmioWrite32 (PL111_REG_LCD_IMSC, 0);
return EFI_SUCCESS;
}
@@ -81,37 +78,54 @@ LcdSetMode (
LCD_BPP LcdBpp;
// Set the video mode timings and other relevant information
- Status = LcdPlatformGetTimings (ModeNumber,
- &HRes,&HSync,&HBackPorch,&HFrontPorch,
- &VRes,&VSync,&VBackPorch,&VFrontPorch);
+ Status = LcdPlatformGetTimings (
+ ModeNumber,
+ &HRes,
+ &HSync,
+ &HBackPorch,
+ &HFrontPorch,
+ &VRes,
+ &VSync,
+ &VBackPorch,
+ &VFrontPorch
+ );
ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
+ if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
- Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
+ Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR( Status )) {
+ if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
// Disable the CLCD_LcdEn bit
- LcdControl = MmioRead32( PL111_REG_LCD_CONTROL);
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1);
+ LcdControl = MmioRead32 (PL111_REG_LCD_CONTROL);
+ MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1);
// Set Timings
- MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes));
- MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes));
- MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes));
+ MmioWrite32 (
+ PL111_REG_LCD_TIMING_0,
+ HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes)
+ );
+
+ MmioWrite32 (
+ PL111_REG_LCD_TIMING_1,
+ VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes)
+ );
+
+ MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes));
MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
// PL111_REG_LCD_CONTROL
- LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
+ LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |
+ PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
+ MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
// Turn on power to the LCD Panel
LcdControl |= PL111_CTRL_LCD_PWR;
- MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
+ MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
return EFI_SUCCESS;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 21:08:36 +0000