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* MdePkg/StmApi.h: Add SMM_REV_ID definition for STM headerMichael Kubacki2024-07-121-0/+2
| | | | | | | | | | The `SMM_REV_ID` is defined in the STM specification: https://www.intel.com/content/www/us/en/content-details/671521/smi-transfer-monitor-stm-developer-or-user-guide.html?wapkw=stm, section 10.1.1. This adds it into the `StmApi.h` for potential STM usage. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: Adding EBBR EFI_CONFORMANCE_PROFILE_TABLE GUIDsSam Kaynor2024-07-102-1/+17
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352 Adding additional GUIDs for the EFI_CONFORMANCE_PROFILE_TABLE that are defined in the Embedded Base Boot Requirments (EBBR) Specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sam Kaynor <Sam.Kaynor@arm.com>
* MdePkg: Adding support for EFI_CONFORMANCE_PROFILE_TABLESam Kaynor2024-07-102-0/+61
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352 Adding support for EFI_CONFORMANCE_PROFILE_TABLE by adding an associated header file and relevant GUIDs to MdePkg.dec as defined in the UEFI 2.10 spec. This table is needed to address changes being made within ShellPkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sam Kaynor <Sam.Kaynor@arm.com>
* MdePkg/StandaloneMmServicesTableLib: Support MM_CORE_STANDALONEJiaxin Wu2024-07-051-1/+1
| | | | | | Support the module type for MM_CORE_STANDALONE Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* MdePkg/Tdx.h: Fix the order of NumVcpus and MaxVcpusXiaoyao Li2024-07-041-1/+1
| | | | | | | | | | | | For TDCALL leaf TDG.VP.INFO, the bit 31:0 in R8 returns NUM_VCPUS and bit 63:32 in R8 returns MAX_VCPUS. Current struct TDCALL_INFO_RETURN_DATA defines them in wrong order. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Add AMD SEV features to PcdConfidentialComputingGuestAttrAlexey Kardashevskiy2024-07-041-2/+13
| | | | | | | | | | | | | | | | | | | | | | PcdConfidentialComputingGuestAttr so far only contained an SEV mode bit but there are more other features which do not translate to levels such as DebugVirtualization or SecureTsc. Add the feature mask and the DebugVirtualization feature bit to the PCD. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> --- Changes: v4: * s/CCAttrFeatureAmdSevDebugSwap/CCAttrFeatureAmdSevEsDebugVirtualization/ v2: * expanded features mask * added type mask
* MdePkg/Register/Amd: Define all bits from MSR_SEV_STATUS_REGISTERAlexey Kardashevskiy2024-07-041-4/+91
| | | | | | | | | | | | | | | | For now we need DebugSwap but others are likely to be needed too. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Changes: v5: * "rb" from Tom v4: * added more from April/2024 APM
* MdePkg/Nvme.h: Add missing NVMe capability descriptionsMichael Kubacki2024-07-041-6/+6
| | | | | | | | | Most of the definitions in this file are currently well documented. This adds documentation for a few missing fields in the NVMe Controller Capabilities structure. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: UefiTcgPlatform.h updatesDionna Glaze2024-07-021-4/+12
| | | | | | | | | | | The TCG_Sp800_155_PlatformId_Event2 and 3 structures both list the platform model string twice, which is incorrect according to the TCG PC Client Platform Firmware Profile. Also add constant definitions for the locator types added in the December 2023 revision. Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
* MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache typesGerd Hoffmann2024-06-261-0/+7
| | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg/BaseLib: Fix an instruction write width error in LoongArch64Dongyan Qian2024-06-261-1/+1
| | | | | | | | | | | | Cpucfg fetch is a 32-bit register, and AsmCpucfg's function declaration is a 32-bit address storage operation in BaseLib.h, So, fix it by replacing stptr.d with stptr.w instrcution. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4797 Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Chao Li <lichao@loongson.cn>
* MdePkg: Check if compiler has __has_builtin before trying to use itRebecca Cran2024-06-201-1/+1
| | | | | | | | | | | | When building AArch64 code, cpp gets run with the `-undef` flag which on Fedora 40 with gcc version 14.1.1 20240607 (Red Hat 14.1.1-5) causes __has_builtin to be undefined. When running the check for __builtin_unreachable in Base.h it causes an error "missing binary operator before token "("". Check that we have __has_builtin before trying to use it. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg/ArmLib: Drop obsolete library declarationsArd Biesheuvel2024-06-192-41/+0
| | | | | | | | Drop obsolete library declarations that are no longer (and should not be) implemented in EDK2 or UEFI, given that they are specific to the secure world. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/Include: Update AMD specification referencesPaul Grimes2024-06-182-2/+2
| | | | | | | | | Update AMD sepcification references (code comments) as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* MdePkg/Include: Update Msr.h header guard definePaul Grimes2024-06-181-2/+2
| | | | | | | | | Update the Msr.h eader guard to comply with latest edk2 coding guidelines. This change is part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* MdePkg/Include: Remove deprecated AMD SEV-SNP header filePaul Grimes2024-06-181-153/+0
| | | | | | | | Delete Fam17Msr.h as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* MdePkg/Include: Update reference to SEV-SNP header filePaul Grimes2024-06-181-1/+1
| | | | | | | | Update reference to SevSnpMsr.h as part of a refactor of MSR definitions and SEV-SNP related defines. Remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* MdePkg/Include: Add AMD SEV-SNP header filePaul Grimes2024-06-181-0/+153
| | | | | | | | Add SevSnpMsr.h as part of a refactor of MSR definitions and SEV-SNP related defines, which aims to remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* ArmPkg,MdePkg: Move ArmPkg/Chipset/Aarch64[|Mmu].h to MdePkgPierre Gondois2024-06-153-1/+339
| | | | | | | | | | | | | | Following the discussion at [1] and as the ArmLib relies on them, move ArmPkg/Chipset/Aarch64[|Mmu].h files to the MdePkg. Update the path to correctly include the moved files. [1] https://edk2.groups.io/g/devel/message/111566 Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg,MdePkg: Move ArmPkg/Chipset/ArmV7[|Mmu].h to MdePkgPierre Gondois2024-06-153-1/+448
| | | | | | | | | | | | | | Following the discussion at [1] and as the ArmLib relies on them, move ArmPkg/Chipset/ArmV7[|Mmu].h files to the MdePkg. Update the path to correctly include the moved files. [1] https://edk2.groups.io/g/devel/message/111566 Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg,MdePkg: move ArmLib.h to MdePkgLeif Lindholm2024-06-152-0/+834
| | | | | | | | | | | | | | | | | | | | | Related to https://bugzilla.tianocore.org/show_bug.cgi?id=4121, but not resolving it. (Nearly?) all of ArmPkg describes industry standard behaviour, and hence according to general rules, ought to live in MdePkg. Addressing this will however be a substantial task. Take a first step by moving the ArmLib interface definition to MdePkg, as discussed in https://edk2.groups.io/g/devel/topic/patch_v5_2_6/102725178 Continuous-integration-options: PatchCheck.ignore-multi-package Cc: Pierre Gondois <pierre.gondois@arm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/X86UnitTestHost: set rdrand cpuid bitGerd Hoffmann2024-06-141-1/+10
| | | | | | | Set the rdrand feature bit when faking cpuid for host test cases. Needed to make the CryptoPkg test cases work. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg/BaseRngLib: Add a smoketest for RDRAND and check CPUIDPedro Falcato2024-06-131-8/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RDRAND has notoriously been broken many times over its lifespan. Add a smoketest to RDRAND, in order to better sniff out potential security concerns. Also add a proper CPUID test in order to support older CPUs which may not have it; it was previously being tested but then promptly ignored. Testing algorithm inspired by linux's arch/x86/kernel/cpu/rdrand.c :x86_init_rdrand() per commit 049f9ae9.. Many thanks to Jason Donenfeld for relicensing his linux RDRAND detection code to MIT and the public domain. >On Tue, Nov 22, 2022 at 2:21 PM Jason A. Donenfeld <Jason@zx2c4.com> wrote: <..> > I (re)wrote that function in Linux. I hereby relicense it as MIT, and > also place it into public domain. Do with it what you will now. > > Jason BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4163 Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jason A. Donenfeld <Jason@zx2c4.com>
* MdePkg/BaseLib: Let CpuDeadLoop() be breakable in debuggerRay Ni2024-06-121-2/+4
| | | | | | | | | | | | | | | | | | | Starting from certain version of Visual Studio C compiler (I don’t have the exact version. I am using VS2019), CpuDeadLoop is optimized quite well by compiler. The compiler does not generate instructions that jump out of the loop when the "Index" is non-zero. It becomes harder/impossible for developers to break out of the dead-loop in debugger. The new version of CpuDeadLoop() compares a volatile global to a volatile local. This forces 2 reads and a comparison on every loop iteration. The local variable can be set to 1 to exit the loop without modifying the global variable. Using VS2019 with max opt enabled, The dead-loop can be exit by setting Index to 1 in a debugger. Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Remove non-ASCII characters from header fileNeo Hsueh2024-06-052-6/+6
| | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4775 Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jiangang He <jiangang.he@amd.com>
* MdePkg: Add Ipmi Net Sensor Thresholds command defines.Aaron2024-06-051-0/+46
| | | | | | | Adding definitions for Ipmi Net Sensor Get/Set Thresholds commands and structures as found in Ipmi specification v2.0 Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* MdePkg: Add Ipmi definitions header file for OEM net functionNickle Wang2024-05-301-0/+18
| | | | | | | | | | | Add net function definitions for OEM/Non-IPMI group request and response Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdePkg/BaseRngLib AARCH64: Remove overzealous ASSERT()Ard Biesheuvel2024-05-241-1/+0
| | | | | | | | | | | | | | | | | | | | | | BaseRngLib on AARCH64 will discover whether or not RNDR instructions are supported, by inspecting the ISAR0 identification register, and setting a global boolean accordingly. This boolean is used in subsequent execution to decide whether or not to issue the instruction. The same discovery code also ASSERT()s that RNDR instructions are implemented, which is unnecessary, and breaks execution on systems that incorporate the library but don't implement the instruction (or fail to expose it to the exception level that the firmware executes at). So drop the ASSERT(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Committed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MockHash2 Protocol for testingDoug Flick2024-05-242-0/+94
| | | | | | | | | | | | This commit adds a new MockHash2 protocol to the MdePkg. This allows the unit tests to pick up the new protocol and use it for testing. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Adds Protocol for MockRngDoug Flick2024-05-242-0/+69
| | | | | | | | | | | | This patch adds a protocol for MockRng. This protocol is used to mock the Rng protocol for testing purposes. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add MockUefiBootServicesTableLibDoug Flick2024-05-244-0/+180
| | | | | | | | | | | This commit adds a mock library for UefiBootServicesTableLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix AARCH64 compilation errorShun Cheng Liu2024-05-152-0/+2
| | | | | | | | | | | | | Declare InternalAssertJumpBuffer as EXTERN Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Shun Cheng Liu <adam.liu@tw.synaptics.com> Reviewed-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg: Add MmUnblockMemoryLib to MdeLibs.dscRay Ni2024-05-101-1/+2
| | | | | | | | | | | | | | | | | | MdeLibs.dsc.inc included some default libraries provided by MdePkg. Platform can include MdeLibs.dsc.inc file to avoid some potential incompatible changes to platform dsc file in future. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: Updated SpcrTable structure for Revision_4praveensankarn2024-05-091-0/+32
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4656 In SPCR table, 4 structure members have been added newly as per SPCR table Revision 4, which has to be added in MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h. Signed-off-by: Praveen Sankar N <praveensankarn@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Felix Polyudov <Felixp@ami.com> Cc: Srinivasan Mani <srinivasanm@ami.com> Cc: Sundaresan S <sundaresans@ami.com> Cc: Rabisha R <rabishar@ami.com>
* MdePkg: Update Delayed Dispatch PPI as per PI 1.8 SpecSachin Ganesh2024-05-081-1/+23
| | | | | | | | | | | Added WaitOnEvent() function to EFI_DELAYTED_DISPATCH_PPI. Modified DispatchRegister() parameter list. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Define Unaccepted Memory TypeSachin Ganesh2024-05-082-18/+7
| | | | | | | | | | | | EFI_RESOURCE_MEMORY_UNACCEPTED has been officially defined in the PI 1.8 specification. So all temporary solutions have been replaced with the actual definition. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add new Resource Attributes defined in PI 1.8 SpecSachin Ganesh2024-05-081-0/+2
| | | | | | | | | | | Defined Encrypted and Special Purpose resource attributes as defined in PI 1.8 Specification Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add definition for NVMe Over Fabric Device PathSachin Ganesh2024-05-081-0/+22
| | | | | | | | | | | | In accordance with UEFI 2.10 Specification: Adding definition for NVMe Over Fabric (NVMe-oF) Device Path of Messaging Sub-Type. Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SpiConfiguration: Correct the definition spellingAbner Chang2024-05-081-2/+2
| | | | | | | Cc: Abner Chang <abner.chang@amd.com> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Signed-off-by: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* MdePkg: Add TcgSp800155Event3 type infoDionna Glaze2024-05-071-1/+37
| | | | | | | | | | | | | | TCG PC Client Platform Firmware Profile 1.06 revision 52 of December 2023 added a new event signature and extended information about where a reference measurement document for the firmware can be found. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Signed-off-by: Dionna Glaze <dionnaglaze@google.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add devAuthBoot GlobalVariableWenxing Hou2024-04-302-2/+11
| | | | | | | | | | | | | According to UEFI 2.10 spec 3.3 Globally Defined Variables section, add devAuthBoot GlobalVariable. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Add TCG PFP 1.06 support.Wenxing Hou2024-04-302-3/+187
| | | | | | | | | | | | | Add support for TCG PC Client Platform Firmware Profile Specification 1.06. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Add SPDM1.2 support.Wenxing Hou2024-04-301-49/+1061
| | | | | | | | | | | | | | Update Spdm.h to support 1.2 new features, such as: Authentication and measurement. It wil be used in DeviceSecurity. The DeviceSecurity feature is from TCG PC Client Platform Firmware Profile Specification 1.06. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Wenxing Hou <wenxing.hou@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Add Cxl30.h into IndustryStandardFoster Nong2024-04-292-1/+317
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4516 1) Add CXL 3.0 header file to comply with CXL 3.0 specification 2) CXL 3.0 header will embed Cxl20.h 3) Updated Cxl.h to point to 3.0 header file Signed-off-by: Foster Nong <foster.nong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Ray Ni <ray.ni@intel.com> Cc: Chris Li <chrisli@os.amperecomputing.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add SPI NOR Flash JEDEC SFDP header fileabnchang2024-04-201-0/+324
| | | | | | | | | | | | | | | | BZ#: 4472 Add definition of JEDEC Serial Flash Discoverable Parameters (SFDP) specification. https://www.jedec.org/standards-documents/docs/jesd216b Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Abdul Lateef Attar <abdattar@amd.com>
* MdePkg/Include: Update definitions of SPI related header filesabnchang2024-04-203-3/+35
| | | | | | | | | | | | | | BZ#: 4471 Update definitions according to PI spec 1.8 errata A Signed-off-by: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Abdul Lateef Attar <abdattar@amd.com> Cc: Brit Chesley <brit.chesley@amd.com> Reviewed-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Add a new VMGEXIT instruction invocation for SVSMTom Lendacky2024-04-174-0/+174
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The SVSM specification relies on a specific register calling convention to hold the parameters that are associated with the SVSM request. The SVSM is invoked by requesting the hypervisor to run the VMPL0 VMSA of the guest using the GHCB MSR Protocol or a GHCB NAE event. Create a new version of the VMGEXIT instruction that will adhere to this calling convention and load the SVSM function arguments into the proper register before invoking the VMGEXIT instruction. On return, perform the atomic exchange on the SVSM call pending value as specified in the SVSM specification. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg/Register/Amd: Define the SVSM related informationTom Lendacky2024-04-174-2/+156
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The Secure VM Service Module specification defines the interfaces needed to allow multi-VMPL level execution of an SEV-SNP guest. Define the SVSM related structures for the SVSM Calling Area as well as the SVSM CAA MSR. The SVSM CAA MSR is an MSR register that is reserved for software use and will not be implemented in hardware. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg: Avoid hardcoded value for number of Page State Change entriesTom Lendacky2024-04-171-3/+4
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The SNP_PAGE_STATE_MAX_ENTRY is based on the number of entries that can fit in the GHCB shared buffer. As a result, the SNP_PAGE_STATE_CHANGE_INFO structure maps the full GHCB shared buffer based on the shared buffer size being 2032 bytes. Instead of using a hardcoded value for SNP_PAGE_STATE_MAX_ENTRY, use a build calculated value. Since the SNP_PAGE_STATE_CHANGE_INFO is used as a mapping, eliminate the hardcoded array size so that the structure can be used based on any size buffer. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg: GHCB APIC ID retrieval support definitionsTom Lendacky2024-04-171-1/+11
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 When an SVSM is present, starting the APs requires knowledge of the APIC IDs. Create the definitions required to retrieve and hold the APIC ID information of all the vCPUs present in the guest. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 19:35:34 +0000