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* MdePkg/BaseLib: Add NULL version Tdx functions for other architecturesCeping Sun2024-09-092-4/+5
| | | | | | | | | | | | | | Currently, the NULL version Tdx functions are only built for Ia32. In BaseLib, the others architectures also need such NULL version Tdx functions. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* MdePkg/IndustryStandard: Add definitions for IPMI Boot Progress CodeNhi Pham2024-09-061-0/+69
| | | | | | | | | | This adds constants and structure definitions for Send/Get Boot Progress Code through IPMI, according to Server Base Manageability Requirements (SBMR) [1], Appendix F. [1] https://developer.arm.com/documentation/den0069 Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
* MdePkg:Update Return Error Macro in Base.hParth2024-09-031-1/+1
| | | | | | | | | | | | Fixing RETURN_ERROR macro. It is causing problem in Coverity Static analysis tool as we are directly converting the UINT value to INTN Changing value from UINT to INTN might cause problem. Here we know that the values would not be in loss of data. To increase the code quality and increase the static tool analysis score we have to change it Cc: Jiangang He <jiangang.he@amd.com> Cc: Neo Hsueh <Hong-Chih.Hsueh@amd.com> Signed-off-by: Parth Thakkar <ParthRajeshkumar.Thakkar@amd.com>
* MdePkg/SmBios.h: Add new Processor Upgrade definition for SMBIOS Type4Jason Zhao2024-09-031-1/+2
| | | | | | | | | The patch adds ProcessorUpgradeInvalid(0xFF) definition in Processor Upgrade(Type 4, Offset 19h) for SMBIOS Type4 based on SMBIOS v3.8.0. Processor Upgrade should be 0xFF when no other valid enumeration is available. Signed-off-by: Jason Zhao <jason.zhao@intel.com>
* MdePkg/SmBios.h: Add new Socket Type for SMBIOS Type4Jason Zhao2024-09-031-0/+4
| | | | | | | The patch adds new socket type(Type 4, Offset 32h) for SMBIOS Type4 based on SMBIOS v3.8.0. Signed-off-by: Jason Zhao <jason.zhao@intel.com>
* MdePkg: Fix a buffer overread.John Baldwin2024-09-031-1/+2
| | | | | | | | | | | | | | DevPathToTextUsbWWID allocates a separate copy of the SerialNumber string to append a null terminator if the original string is not null terminated. However, by using AllocateCopyPool, it tries to copy 'Length + 1' words from the existing string containing 'Length' characters into the target string. Split the copy out to only copy 'Length' characters instead. This was reported by GCC's -Wstringop-overread when compiling a copy of this routine included in a library on FreeBSD. Signed-off-by: John Baldwin <jhb@FreeBSD.org>
* MdePkg: Add HTTP error 429Ken Lautner2024-09-021-1/+2
| | | | | | Add support for HTTP error 429 in the protocol .h file. Signed-off-by: Kenneth Lautner <kenlautner3@gmail.com>
* MdePkg: Add Reset Reason definitionsSaloni Kasbekar2024-08-311-0/+48
| | | | | | Add Reset Reason definitions defined in ACPI 6.5 Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
* MdePkg: Remove duplicate source from BaseMemoryLib INF filesAshraf Ali2024-08-315-116/+13
| | | | Signed-off-by: Ashraf Ali <ashraf.ali.s@intel.com>
* MdePkg: Remove the old name of LoongArch CSR 0x20Chao Li2024-08-301-1/+0
| | | | | | | | | | Since all places where the old name was used for the LoongArch CSR 0x20 regiser have been changed to the new name, the old name is removed. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* MdePkg: Rename the LoongArch CSR 0x20 registerChao Li2024-08-302-12/+13
| | | | | | | | | | | | | Added a new name for CSR 0x20 because LoongArch SPEC has adjustd the CSR 0x20 register name. Ref: LoongArch Reference Manual Vol 1, Seciton 7.1. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* MdePkg: CoreValidateHandle OptimizationXiaoqiang Zhang2024-08-301-0/+1
| | | | | | | | | | | | REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4817 This commit is to add OrderedCollectionLib in MdePkg for DxeCore usage. Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Andrew Fish <afish@apple.com> Tested-by: Xiaoqiang Zhang <xiaoqiang.zhang@intel.com>
* MdePkg Nvme.h: Update fields from 1.4c specification.Ray Robles2024-08-291-23/+53
| | | | | | | Implement 1.4c specification update, specifically for nvme sanitize capabilities. Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* MdePkg:BaseArmTrngLibNull: Assert causing FVP stallingPrachotan Reddy Bathi2024-08-291-1/+1
| | | | | | | | FVP Base Revc doesn't support Trng. ASSERT (FALSE) is causing the boot to stall. Replacing ASSERT with ERROR log. Signed-off-by: Prachotan Reddy Bathi <Prachotan.Bathi@arm.com>
* MdePkg/MdePkg.dec: Add gEfiMmEndOfPeiProtocol definitionJiaxin Wu2024-08-281-0/+4
| | | | | | | | | | | | | | | | | | | This protocol is defined at PI Spec, Vol 4, section 4. It's a MM Protocol published by a standalone MM Foundation code if MM Foundation is loaded in PEI phase. This protocol should be installed immediately after DXE IPL installs EFI_PEI_END_OF_PEI_PHASE_PPI. Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Co-authored-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* MdePkg: Fix build error after enable FDT support.Linus Liu2024-08-281-2/+5
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Disable some compiling warnings caused by submodule code. Those can be removed later once issues fixed by submodule owner. Signed-off-by: Linus Liu <linus.liu@intel.com>
* MdePkg/BaseFdtLib: Add FdtNodeOffsetByCompatible()Nhi Pham2024-08-282-0/+37
| | | | | | | This adds FdtNodeOffsetByCompatible() to support finding the offset of the first node with a given 'compatible' value after an offset. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
* MdePkg: Define BrainpoolP512r1Michael G.A. Holland2024-08-271-9/+10
| | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4837 Add BrainpoolP512R1 definition to TPM20.h Signed-off-by: Michael G.A. Holland <michael.holland@intel.com>
* MdePkg: Tpm2Acpi.h: Max size for Parameters fieldDat Mach2024-08-081-0/+4
| | | | | | | Define macro for the max size of the Start Method Specific Paramemeters field. Signed-off-by: Dat Mach <dmach@nvidia.com>
* MdePkg/BaseLib: Add CRC16 CCITT False Implementation.kuqin122024-08-062-0/+86
| | | | | | | | | | | | | | This change is added to incorporate basic implementation for CRC16-CCITT-FALSE algorithm. This function is useful for providing CRC16 value used in other data structures that requires CRC16 value that complies with JEDEC SPD requirements, i.e. BDAT table. The lookup table is inherited from `https://crccalc.com/` and the result values are also compared against this site. Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* MdePkg /IoRemappingTable: Define additional IORT SMMUv3 node flags.joe2024-08-041-1/+2
| | | | | | | | | | | | | | | | | | | | | The flag for HTTU override in an SMMUv3 node in the IORT table is defined in MdePkg/Include/IndustryStandard/IoRemappingTable.h as a single bit. BIT0 or BIT1. The implementation of this field is actually two bits, with the following mapings: 0b0000: Hardware update of the Access flag and dirty state are not supported. 0b0001: Support for hardware update of the Access flag for Block and Page descriptors. 0b0010: As 0b0001, and adds support for hardware update of the Access flag for Block and Page descriptors. Hardware update of dirty state is supported. Referenced in Arm® System Memory Management Unit Architecture Specification SMMU architecture version 3: https://documentation-service.arm.com/static/63d7a2d5e4378a55c5e045b9 Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* MdePkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-015-32/+32
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg/IndustryStandard: Add definitions for MPAM ACPI specificationRohit Mathew2024-08-012-1/+252
| | | | | | | | | | | | | | | | Add definitions, macros and types for elements associated with MPAM ACPI 2.0 specification. Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseRngLib: Prefer ArmReadIdAA64Isar0Reg() over ArmReadIdIsar0()Pierre Gondois2024-08-015-82/+2
| | | | | | | | | | | | | | | A ArmReadIdAA64Isar0Reg() function was recently added to BaseLib. Use it instead of its ArmReadIdIsar0() equivalent, which was private to the BaseRngLib library. This also allows to avoid the confusion between the following registers: - ID_ISAR0_EL1: allows to probe for Divide instructions, Debug instructions, ... - ID_AA64ISAR0_EL1: AARCH64 specific register allowing to probe for AESE, RNDR, ... instructions Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()Pierre Gondois2024-08-014-0/+134
| | | | | | | | | | | | | | To enable AARCH64 native instruction support for Openssl, some interfaces must be implemented. OPENSSL_cpuid_setup() allows to probe the supported features of the platform. Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing Arm64 instruction capabilities. A similar ArmReadIdAA64Isar0() function is available in the ArmPkg, but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely on the ArmPkg. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()Pierre Gondois2024-08-014-1/+78
| | | | | | | | | | | | | To enable AARCH64 native instruction support for Openssl, some interfaces must be implemented. OPENSSL_rdtsc() requests an access to a counter to get some non-trusted entropy. Add ArmReadCntPctReg() to read system count. A similar ArmReadCntPct() function is available in the ArmPkg, but the CryptoPkg where OPENSSL_rdtsc will reside cannot rely on the ArmPkg. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
* MdePkg: Add PCI Express 6.0 Header SupportSachin Ganesh2024-08-013-22/+173
| | | | | | | | | | | | | | PCI Express 6.0 Specification introduces new registers and modifies fields in existing ones. This commit syncs PciE headers with the spec update. Cc: Sergiy Yakovlev <sergiyy@ami.com> Cc: Felix Polyudov <felixp@ami.com> Cc: Dhanaraj V <vdhanaraj@ami.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Sachin Ganesh <sachinganesh@ami.com>
* MdePkg/Acpi65.h: Fix GUID valueMichael Kubacki2024-08-011-1/+1
| | | | | | | | | | Commit c5ef1f0 added Acpi65.h by copying and updating text from Acpi64.h. In that process, `0x624B` was updated to `0x6.5B` likely due to a find/replace regex being used. This restores the value. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: IORT header update for IORT Rev E.f specAbhishek Mainkar2024-07-301-2/+3
| | | | | | | | | | | The IO Remapping Table, Platform Design Document, Revision E.f, April 2024 (https://developer.arm.com/documentation/den0049/ef/) added CANWBS Memory access flag. Therefore, update the IORT header file to add support for CANWBS Memory access flag. Signed-off-by: Abhishek Mainkar <abmainkar@nvidia.com>
* MdePkg: Update HEST Revision As 2Herman Li2024-07-301-1/+1
| | | | | | | | | This modification come from ACPI 6.5 spec. Besides, Starting with revision 2 of HEST, the Error Source Structures must be sorted in Type ascending order for Error Source Structure Types of less than 12. Signed-off-by: Herman Li <herman.li@intel.com>
* MdePkg: Move MEMORY_TYPE_* Defines to EFI_MEMORY_TYPE EnumDmitry Antipov2024-07-261-1/+16
| | | | | | | | | | | | Per TCBZ2372, clang on Linux emits a warning if an enum-typed variable is compared with a constant outside of the range of the enum. Such comparisons are performed in multiple locations in DXE core on variables of type EFI_MEMORY_TYPE. This patch moves the OEM and OS reserved types into the EFI_MEMORY_TYPE enum itself to resolve this issue and improve readability. This commit does this for the MdePkg copy of this enum. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* MdePkg/BaseLib: Optimize LOONGARCH64 csr usageDongyan Qian2024-07-172-9/+7
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4812 When the Select is out of support, use method break exception instead of method return -1, avoid unknown errors caused by untimely detection. Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* MdePkg/IndustryStandard: Update EINJ information according to ACPI 6.5levi.yun2024-07-171-2/+4
| | | | | | | | | | | | | | | | | | ACPI 6.5 specification updates EINJ revision to 0x02 and adds new Error Injection Actions - EINJV2_SET_ERROR_TYPE - EINJV2_GET_ERROR_TYPE This patches updates EINJ information based on ACPI 6.5 specification. Also, add missing Error Injection Actions too. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg/IndustryStandard: Add GET_EXECUTE_OPERATION_TIMINGS definelevi.yun2024-07-175-0/+5
| | | | | | | | | | | | | | | GET_EXECUTE_OPERATION_TIMINGS Error Injection Actions was added from ACPI 6.1 specification. Update Error Injection Action with the ACPI spec. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg/IndustryStandard: Add SET_ERROR_TYPE_WITH_ADDRESS definelevi.yun2024-07-177-0/+7
| | | | | | | | | | | | | | | SET_ERROR_TYPE_WITH_ADDRESS Error Injection Actions was added from ACPI 5.1 specification. Update Error Injection Action with the ACPI spec. Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: levi.yun <yeoreum.yun@arm.com>
* MdePkg: Added support for Smbios 3.7.0 SpecShenbagadevi R2024-07-171-1/+8
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4563 As per Smbios 3.7.0 spec, added CXL 3.0 support in Type 9, also added PMIC & RCD manufacturer ID and Revision information in Type17. Cc: Sainadh N <sainadhn@ami.com> Cc: Sundaresan S <sundaresans@ami.com> Cc: Srinivasan M <srinivasanm@ami.com> Cc: Ramesh R <rameshr@ami.com> Signed-off-by: Shenbagadevi R <shenbagadevir@ami.com> Reviewed-by: Gaoliming <gaoliming@byosoft.com.cn>
* MdePkg: Define SMBIOS Protocol header according IndustryStandardDongyan Qian2024-07-171-0/+4
| | | | | | | | | | | | | | | | | | As the SMBIOS table types belong to the SMBIOS standard, they were moved from the SMBIOS IndustryStandard into the SMBIOS Protocol header with the EFI_-prefix. Filling in definitions facilitates consistent use of header files: EFI_SMBIOS_TYPE_TPM_DEVICE EFI_SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION EFI_SMBIOS_TYPE_FIRMWARE_INVENTORY_INFORMATION EFI_SMBIOS_TYPE_STRING_PROPERTY_INFORMATION Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* MdePkg/UefiDebugLibDebugPortProtocol: ExitBootServicesCallback() staticMichael Kubacki2024-07-161-2/+3
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3083 Since this is a library, make the function ExitBootServicesCallback() STATIC to prevent the likelihood that it collides with other symbols. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg/Library: Add RISCV64 support to BaseRngLibDhaval2024-07-155-0/+316
| | | | | | | | | | | | | | | The ratified RISC-V crypto scalar extensions provide entropy bits via the seed CSR, as exposed by the Zkr extension. The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR. Guarded by a RISCV64 Feature PCD, 64-bit random numbers can be accumulated from the `seed` CSR. This driver is based on the driver in the Linux kernel. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
* MdePkg/StmApi.h: Add SMM_REV_ID definition for STM headerMichael Kubacki2024-07-121-0/+2
| | | | | | | | | | The `SMM_REV_ID` is defined in the STM specification: https://www.intel.com/content/www/us/en/content-details/671521/smi-transfer-monitor-stm-developer-or-user-guide.html?wapkw=stm, section 10.1.1. This adds it into the `StmApi.h` for potential STM usage. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: Adding EBBR EFI_CONFORMANCE_PROFILE_TABLE GUIDsSam Kaynor2024-07-102-1/+17
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352 Adding additional GUIDs for the EFI_CONFORMANCE_PROFILE_TABLE that are defined in the Embedded Base Boot Requirments (EBBR) Specification. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sam Kaynor <Sam.Kaynor@arm.com>
* MdePkg: Adding support for EFI_CONFORMANCE_PROFILE_TABLESam Kaynor2024-07-102-0/+61
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4352 Adding support for EFI_CONFORMANCE_PROFILE_TABLE by adding an associated header file and relevant GUIDs to MdePkg.dec as defined in the UEFI 2.10 spec. This table is needed to address changes being made within ShellPkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sam Kaynor <Sam.Kaynor@arm.com>
* MdePkg/StandaloneMmServicesTableLib: Support MM_CORE_STANDALONEJiaxin Wu2024-07-051-1/+1
| | | | | | Support the module type for MM_CORE_STANDALONE Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* MdePkg/Tdx.h: Fix the order of NumVcpus and MaxVcpusXiaoyao Li2024-07-041-1/+1
| | | | | | | | | | | | For TDCALL leaf TDG.VP.INFO, the bit 31:0 in R8 returns NUM_VCPUS and bit 63:32 in R8 returns MAX_VCPUS. Current struct TDCALL_INFO_RETURN_DATA defines them in wrong order. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Add AMD SEV features to PcdConfidentialComputingGuestAttrAlexey Kardashevskiy2024-07-041-2/+13
| | | | | | | | | | | | | | | | | | | | | | PcdConfidentialComputingGuestAttr so far only contained an SEV mode bit but there are more other features which do not translate to levels such as DebugVirtualization or SecureTsc. Add the feature mask and the DebugVirtualization feature bit to the PCD. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> --- Changes: v4: * s/CCAttrFeatureAmdSevDebugSwap/CCAttrFeatureAmdSevEsDebugVirtualization/ v2: * expanded features mask * added type mask
* MdePkg/Register/Amd: Define all bits from MSR_SEV_STATUS_REGISTERAlexey Kardashevskiy2024-07-041-4/+91
| | | | | | | | | | | | | | | | For now we need DebugSwap but others are likely to be needed too. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Changes: v5: * "rb" from Tom v4: * added more from April/2024 APM
* MdePkg/Nvme.h: Add missing NVMe capability descriptionsMichael Kubacki2024-07-041-6/+6
| | | | | | | | | Most of the definitions in this file are currently well documented. This adds documentation for a few missing fields in the NVMe Controller Capabilities structure. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* MdePkg: UefiTcgPlatform.h updatesDionna Glaze2024-07-021-4/+12
| | | | | | | | | | | The TCG_Sp800_155_PlatformId_Event2 and 3 structures both list the platform model string twice, which is incorrect according to the TCG PC Client Platform Firmware Profile. Also add constant definitions for the locator types added in the December 2023 revision. Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
* MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache typesGerd Hoffmann2024-06-261-0/+7
| | | | Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg/BaseLib: Fix an instruction write width error in LoongArch64Dongyan Qian2024-06-261-1/+1
| | | | | | | | | | | | Cpucfg fetch is a 32-bit register, and AsmCpucfg's function declaration is a 32-bit address storage operation in BaseLib.h, So, fix it by replacing stptr.d with stptr.w instrcution. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4797 Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Chao Li <lichao@loongson.cn>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 16:31:44 +0000