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* UefiCpuPkg: Add SmmRelocationLib classJiaxin Wu2024-05-081-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel plans to separate the smbase relocation logic from PiSmmCpuDxeSmm driver, and the related behavior will be moved to the new interface defined by the SmmRelocationLib class. The SmmRelocationLib class provides the SmmRelocationInit() interface for platform to do the smbase relocation, which shall provide below 2 functionalities: 1. Relocate smbases for each processor. 2. Create the gSmmBaseHobGuid HOB. With SmmRelocationLib, PiSmmCpuDxeSmm driver (which runs at a later phase) shall: 1. Consume the gSmmBaseHobGuid HOB for the relocated smbases for each Processor. 2. Execute the early SMM Init. This patch just provides the SmmRelocationLib class. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/AmdSvsmLib: Create the AmdSvsmLib library to support an SVSMTom Lendacky2024-04-171-0/+101
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 In order to support an SEV-SNP guest running under an SVSM at VMPL1 or lower, a new library must be created. This library includes an interface to detect if running under an SVSM, an interface to return the current VMPL, an interface to perform memory validation and an interface to set or clear the attribute that allows a page to be used as a VMSA. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Always use AP Create if GhcbApicIds HOB is presentTom Lendacky2024-04-171-0/+17
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 Currently, the first time an AP is started for an SEV-SNP guest, it relies on the VMSA as set by the hypervisor. If the list of APIC IDs has been retrieved, this is not necessary. The list of APIC IDs will be identified by a GUIDed HOB. If the GUIDed HOB is present, use the SEV-SNP AP Create protocol to start the AP for the first time and each time thereafter. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add a new GUID to store the processors resourceChao Li2024-04-161-0/+29
| | | | | | | | | | | | | On a multi-processor system, if the BSP dose not know how many APs are online or cannot wake up the AP via broadcast, it can collect AP resouces before wakeing up the AP and add a new HOB to save the processor resouces. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkgChao Li2024-04-161-0/+41
| | | | | | | | | | | | | | | | | | | | | Add a new header file CpuMmuLib.h, whitch is referenced from ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for LoongArch64 is added, and more architectures can be accommodated in the future. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Fix issue that IsModified is wrongly set in PageTableMapZhiguang Liu2024-02-221-1/+3
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4614 About the IsModified, current function doesn't consider that hardware also may change the pagetable. The issue is that in the first call of internal function PageTableLibMapInLevel, the function assume page table is not changed, and add ASSERT to check. But hardware may change the page table, which cause the ASSERT happens. Fix the issue by adding addtional condition to only check if the page table is changed when the software want to modify the page table. Also, add more comment to explain this behavior. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Crystal Lee <CrystalLee@ami.com.tw> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Enhance function header for PageTableMap()Zhiguang Liu2024-02-221-0/+1
| | | | | | | | | | | PageTableMap() only modifies the PageTable root pointer when creating from zero. Explicitly explain it in function header. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Add more Paging mode enumerationDun Tan2024-02-061-1/+7
| | | | | | | | | | | | | Add more Paging mode enumeration in CpuPageTableLib to support forced mapping a range in 4K page granularity. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: change name of gMpInformationHobGuid2Dun Tan2024-01-151-1/+1
| | | | | | | | | | | | | Change name of gMpInformationHobGuid2 to gMpInformation2HobGuid. It's to align with the file name MpInformation2.h and the structure name MP_INFORMATION2_HOB_DATA. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: set EXTENDED_PROCESSOR_INFORMATION to 0duntan2024-01-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Set EXTENDED_PROCESSOR_INFORMATION to 0 in API MpInitLibGetProcessorInfo() of MpInitLibUp. This commit use ZeroMem() to set all fileds in output EFI_PROCESSOR_INFORMATION to 0 before StatusFlag field is reassigned. Previously EXTENDED_PROCESSOR_INFORMATION in the API MpInitLibGetProcessorInfo() of MpInitLibUp is ignored. In PEI/DXE MpInitLib, EXTENDED_PROCESSOR_INFORMATION will be retrived when BIT24 of input ProcessorNumber is set. This commit can avoid garbage in the output structure in MpInitLibGetProcessorInfo() of MpInitLibUp. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Min Xu <min.m.xu@intel.com> Message-Id: <20240108050804.1718-2-dun.tan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Adds SmmCpuSyncLib library classJiaxin Wu2023-12-201-0/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. For the new SmmCpuSyncLib, it provides 3 sets of APIs: 1. ContextInit/ContextDeinit/ContextReset: ContextInit() is called in driver's entrypoint to allocate and initialize the SMM CPU Sync context. ContextDeinit() is called in driver's unload function to deinitialize SMM CPU Sync context. ContextReset() is called before CPU exist SMI, which allows CPU to check into the next SMI from this point. 2. GetArrivedCpuCount/CheckInCpu/CheckOutCpu/LockDoor: When SMI happens, all processors including BSP enter to SMM mode by calling CheckInCpu(). The elected BSP calls LockDoor() so that CheckInCpu() will return the error code after that. CheckOutCpu() can be called in error handling flow for the CPU who calls CheckInCpu() earlier. GetArrivedCpuCount() returns the number of checked-in CPUs. 3. WaitForAPs/ReleaseOneAp/WaitForBsp/ReleaseBsp WaitForAPs() & ReleaseOneAp() are called from BSP to wait the number of APs and release one specific AP. WaitForBsp() & ReleaseBsp() are called from APs to wait and release BSP. The 4 APIs are used to synchronize the running flow among BSP and APs. BSP and AP Sync flow can be easy understand as below: BSP: ReleaseOneAp --> AP: WaitForBsp BSP: WaitForAPs <-- AP: ReleaseBsp Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add a new field in MpInfo2 HOBDun Tan2023-12-121-0/+2
| | | | | | | | | | Add new field CoreType in gMpInformationHobGuid2 Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Create gMpInformationHobGuid2 in UefiCpuPkgDun Tan2023-12-121-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create gMpInformationHobGuid2 in UefiCpuPkg. Currently, there is a gMpInformationHobGuid defined, created and consumed only in StandaloneMmPkg. The HOB contains the EFI_PROCESSOR_INFORMATION structure for each CPU and the number of processors. This is the same as the information that PiSmmCpuDxeSmm uses MpService Protocol to get. This new gMpInformationHobGuid2 also contains the NumberOfProcessors and the EFI_PROCESSOR_INFORMATION for each CPU. Also the HOB is extended to support the case that the maximum HOB length is not enough for all CPU. So there might be more than one HOB instance in the HOB list. Each HOB describes the corresponding CPU index range. The plan is to create gMpInformationHob2Guid in CpuMpPei module(implemented in next commit). Then PiSmmCpuDxeSmm and other MM_STANDALONE modules can consume the hob. This can avoid calling MpService Protocol in PiSmmCpuDxeSmm. Also the issue that one gMpInformationHobGuid might be not enough when CPU number is 1~2000 or bigger can be solved. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MtrrLib: Add API MtrrGetMemoryAttributesInMtrrSettings.YuanhaoXie2023-10-091-0/+23
| | | | | | | | | | | | | | | | | | MtrrGetMemoryAttributesInMtrrSettings parses the MTRR settings either from hardware or from the parameter and returns an array containing the memory cache types of all memory addresses. This API could elinimate the needs of following APIs: 1. MtrrGetMemoryAttributeInVariableMtr 2. MtrrGetFixedMtrr Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MtrrLib: Fix MtrrSetAllMtrrs to handle absent fixed MTRRs.Ray Ni2023-10-091-3/+6
| | | | | | | | | | | | | | | Update MtrrSetAllMtrrs to not access fixed MTRRs if CPU doesn't support them. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add SendStartupIpiAllExcludingSelfYuanhao Xie2023-08-141-1/+16
| | | | | | | | | | | | | Add new API SendStartupIpiAllExcludingSelf(), and modify SendInitSipiSipiAllExcludingSelf() by let it call the new API. Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 modeTuan Phan2023-07-151-0/+68
| | | | | | | | | During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegisterAbdul Lateef Attar2023-07-031-52/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Removes SmmCpuFeaturesReadSaveStateRegister and SmmCpuFeaturesWirteSaveStateRegister function from SmmCpuFeaturesLib library. MmSaveStateLib library replaces the functionality of the above functions. Platform old/new need to use MmSaveStateLib library to read/write save state registers. Current implementation supports Intel and AMD. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Adds MmSaveStateLib library classAbdul Lateef Attar2023-07-031-0/+74
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds MmSaveStateLib Library class in UefiCpuPkg.dec. Adds function declaration header file. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuLib: Remove UefiCpuLib.Yu Pu2023-04-121-16/+0
| | | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib and all modules are updated to not depend on this library, remove it completely. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.infZhiguang Liu2023-03-271-16/+16
| | | | | | | | | | | | | | | | | | | The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.Dun Tan2023-03-271-1/+3
| | | | | | | | | | | | | Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Add check for Mask and AttrDun Tan2023-03-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for input LengthDun Tan2023-03-271-2/+2
| | | | | | | | | | | | Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* MdePkg: Move API and implementation from UefiCpuLib to CpuLibYu Pu2023-03-101-49/+0
| | | | | | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/SmmBaseHob.h: Add SMM Base HOB DataWu, Jiaxin2023-03-061-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 The default SMBASE for the x86 processor is 0x30000. When SMI happens, processor runs the SMI handler at SMBASE+0x8000. Also, the SMM save state area is within SMBASE+0x10000. One of the SMM initialization from processor perspective is to relocate and program the new SMBASE (in TSEG range) for each processor. When the SMBASE relocation happens in a PEI module, the PEI module shall produce the SMM_BASE_HOB in HOB database which tells the PiSmmCpuDxeSmm driver (runs at a later phase) about the new SMBASE for each processor. PiSmmCpuDxeSmm driver installs the SMI handler at the SMM_BASE_HOB.SmBase[Index]+0x8000 for processor Index. When the HOB doesn't exist, PiSmmCpuDxeSmm driver shall relocate and program the new SMBASE itself. This patch adds the SMM Base HOB for any PEI module to do the SmBase relocation ahead of PiSmmCpuDxeSmm driver and store the relocated SmBase address in array for each processor. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@Intel.com>
* UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitionsSunil V L2023-02-161-0/+34
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Remove unused API in SmmCpuFeaturesLib.hTan, Dun2022-12-211-25/+0
| | | | | | | | | | | Remove SmmCpuFeaturesAllocatePageTableMemory in this headfile. This API is not used by PiSmmCpuDxeSmm driver any more. Also no other files use this API. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* OvmfPkg/UefiCpuPkg: Add CcExit prefix to the APIs of CcExitLibMin M Xu2022-11-141-8/+8
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4123 APIs which are defined in CcExitLib.h are added with the CcExit prefix. This is to make the APIs' name more meaningful. This change impacts OvmfPkg/UefiCpuPkg. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* OvmfPkg/UefiCpuPkg/UefiPayloadPkg: Rename VmgExitLib to CcExitLibMin M Xu2022-11-141-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4123 VmgExitLib once was designed to provide interfaces to support #VC handler and issue VMGEXIT instruction. After TDVF (enable TDX feature in OVMF) is introduced, this library is updated to support #VE as well. Now the name of VmgExitLib cannot reflect what the lib does. This patch renames VmgExitLib to CcExitLib (Cc means Confidential Computing). This is a simple renaming and there is no logic changes. After renaming all the VmgExitLib related codes are updated with CcExitLib. These changes are in OvmfPkg/UefiCpuPkg/UefiPayloadPkg. Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structsRay Ni2022-08-091-0/+129
| | | | | | | | | | | | | | | | | | The lib includes two APIs: * PageTableMap It creates/updates mapping from LA to PA. The implementation only supports paging structures used in 64bit mode now. PAE paging structure support will be added in future. * PageTableParse It parses the page table and returns the mapping relations in an array of IA32_MAP_ENTRY. It passed some stress tests. These test code will be upstreamed in other patches following edk2 Unit Test framework. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* MdePkg: add SmmCpuRendezvousLib.h and SmmCpuRendezvousLibNull implement.Li, Zhihao2022-05-091-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF? https://bugzilla.tianocore.org/show_bug.cgi?id=3912 UefiCpuPkg define a new Protocol with the new services SmmWaitForAllProcessor(), which can be used by SMI handler to optionally wait for other APs to complete SMM rendezvous in relaxed AP mode. VariableSmm and VariableStandaloneMM driver in MdeModulePkg need to use this services but MdeModulePkg can't depend on UefiCpuPkg. Thus, the solution is moving SmmCpuRendezvouslib.h from UefiCpuPkg to MdePkg and creating SmmCpuRendezvousLib NullLib version implementation in MdePkg as dependency for the pkg that can't depend on UefiCpuPkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Zhihao Li <zhihao.li@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg: Extend VmgExitLibNull to handle #VE exceptionMin Xu2022-04-021-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 VmgExitLib performs the necessary processing to handle a #VC exception. VmgExitLibNull is a NULL instance of VmgExitLib which provides a default limited interface. In this commit VmgExitLibNull is extended to handle a #VE exception with a default limited interface. A full feature version of #VE handler will be created later. Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg: Extend SMM CPU Service with rendezvous support.Li, Zhihao2022-03-042-1/+62
| | | | | | | | | | | | | | | | | | | | REF? https://bugzilla.tianocore.org/show_bug.cgi?id=3815 This patch define a new Protocol with the new services SmmWaitForAllProcessor(), which can be used by SMI handler to optionally wait for other APs to complete SMM rendezvous in relaxed AP mode. A new library SmmCpuRendezvousLib is provided to abstract the service into library API to simple SMI handler code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Zhihao Li <zhihao.li@intel.com> Signed-off-by: Zhihao Li <zhihao.li@intel.com>
* UefiCpuPkg: Apply uncrustify changesMichael Kubacki2021-12-0723-303/+292
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Change OPTIONAL keyword usage styleMichael D Kinney2021-12-072-6/+6
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/UefiCpuLib: Add GetCpuFamilyModel and GetCpuSteppingIdNi, Ray2021-11-101-1/+22
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3698 Lots of code relies on CPU Family/Model/Stepping for different logics. The change adds two APIs for such needs. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Refactor initialization of CPU features during S3 resumeLou, Yun2021-09-161-35/+54
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3621 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3631 Refactor initialization of CPU features during S3 resume. In addition, the macro ACPI_CPU_DATA_STRUCTURE_UPDATE is used to fix incompatibility issue caused by ACPI_CPU_DATA structure update. It will be removed after all the platform code uses new ACPI_CPU_DATA structure. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/CpuCacheInfoLib: Sort CpuCacheInfo arrayLou, Yun2021-08-091-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508 Sort the CpuCacheInfo array by CPU package ID, core type, cache level and cache type. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Add MicrocodeLib for loading microcodeRay Ni2021-04-091-0/+120
| | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/CpuCacheInfoLib: Collect cache associative typeLou, Yun2021-03-171-2/+13
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265 Support collecting cache associative type in CpuCacheInfoLib. This prevents the user from using additional code to obtain the same information. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/CpuCacheInfoLib: Add MpService dependencyLou, Yun2021-02-031-2/+0
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3190 Add MpService dependency to enforce the executability of CpuCacheInfoLib. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/AcpiCpuData: update comments on register table fieldsLaszlo Ersek2021-01-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | After commit e992cc3f4859 ("UefiCpuPkg PiSmmCpuDxeSmm: Reduce SMRAM consumption in CpuS3.c", 2021-01-11), it is valid for a CPU S3 Data DXE Driver to set "ACPI_CPU_DATA.PreSmmInitRegisterTable" and/or "ACPI_CPU_DATA.RegisterTable" to 0, in case none of the CPUs needs a register table of the corresponding kind, during S3 resume. Document this fact in the "UefiCpuPkg/Include/AcpiCpuData.h" header file. Cc: Eric Dong <eric.dong@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3159 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210119155440.2262-3-lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/CpuCacheInfoLib: Add new CpuCacheInfoLib.Lou, Yun2021-01-191-0/+76
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 This new library uses a platform agnostic algorithm to get CPU cache information. It provides user with an API(GetCpuCacheInfo) to get detailed CPU cache information by each package, each core type included in this package, and each cache level & type. This library can be used by code that produces SMBIOS_TABLE_TYPE7 SMBIOS table. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/Feature: Support different thread count per coreRay Ni2020-12-041-3/+13
| | | | | | | | | | | | | | | | | Today's code assumes every core contains the same number of threads. It's not always TRUE for certain model. Such assumption causes system hang when thread count per core is different and there is core or package dependency between CPU features (using CPU_FEATURE_CORE_BEFORE/AFTER, CPU_FEATURE_PACKAGE_BEFORE/AFTER). The change removes such assumption by calculating the actual thread count per package and per core. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Yun Lou <yun.lou@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg, OvmfPkg: Disable interrupts when using the GHCBTom Lendacky2020-11-101-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 The QemuFlashPtrWrite() flash services runtime uses the GHCB and VmgExit() directly to perform the flash write when running as an SEV-ES guest. If an interrupt arrives between VmgInit() and VmgExit(), the Dr7 read in the interrupt handler will generate a #VC, which can overwrite information in the GHCB that QemuFlashPtrWrite() has set. This has been seen with the timer interrupt firing and the CpuExceptionHandlerLib library code, UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ Xcode5ExceptionHandlerAsm.nasm and ExceptionHandlerAsm.nasm reading the Dr7 register while QemuFlashPtrWrite() is using the GHCB. In general, it is necessary to protect the GHCB whenever it is used, not just in QemuFlashPtrWrite(). Disable interrupts around the usage of the GHCB by modifying the VmgInit() and VmgDone() interfaces: - VmgInit() will take an extra parameter that is a pointer to a BOOLEAN that will hold the interrupt state at the time of invocation. VmgInit() will get and save this interrupt state before updating the GHCB. - VmgDone() will take an extra parameter that is used to indicate whether interrupts are to be (re)enabled. Before exiting, VmgDone() will enable interrupts if that is requested. Fixes: 437eb3f7a8db7681afe0e6064d3a8edb12abb766 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Acked-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <c326a4fd78253f784b42eb317589176cf7d8592a.1604685192.git.thomas.lendacky@amd.com>
* UefiCpuPkg/VmgExitLib: Add interfaces to set/read GHCB ValidBitmap bitsTom Lendacky2020-11-101-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 In upcoming patches, the setting of the bits in the GHCB ValidBitmap will be performed in multiple places. In order to reduce code duplication, add an interface, VmgSetOffsetValid(), to VmgExitLib library to perform this function. Also, to keep management of the ValidBitmap within the library, add an inteface, VmgIsOffsetValid(), to return whether the bit in the ValidBitmap is set for a specified offset. The new VmgSetOffsetValid() function is a VOID function and will be an empty function in the VmgExitLibNull implementation of the VmgExitLib library. The new VmgIsOffsetValid() function returns a BOOLEAN to indicate if the offset is valid. This will always return FALSE in the VmgExitLibNull implementation of the VmgExitLib library. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <0bcb2373f8c6e0171ae277d3d7c2eb284621355e.1604685192.git.thomas.lendacky@amd.com>
* UefiCpuPkg: Implement library support for VMGEXITTom Lendacky2020-08-161-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 To support handling #VC exceptions and issuing VMGEXIT instructions, create a library with functions that can be used to perform these #VC/VMGEXIT related operations. This includes functions for: - Handling #VC exceptions - Preparing for and issuing a VMGEXIT - Performing MMIO-related write operations to support flash emulation - Performing AP related boot opeations The base functions in this driver will not do anything and will return an error if a return value is required. It is expected that other packages (like OvmfPkg) will create a version of the library to fully support an SEV-ES guest. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/SecMigrationPei: Add initial PEIM (CVE-2019-11098)Michael Kubacki2020-07-281-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 Adds a PEIM that republishes structures produced in SEC. This is done because SEC modules may not be shadowed in some platforms due to space constraints or special alignment requirements. The SecMigrationPei module locates interfaces that may be published in SEC and reinstalls the interface with permanent memory addresses. This is important if pre-memory address access is forbidden after memory initialization and data such as a PPI descriptor, PPI GUID, or PPI inteface reside in pre-memory. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/MtrrLib: Remove unnecessary API MtrrSetFixedMtrr()Ray Ni2020-07-141-15/+0
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2849 MtrrSetFixedMtrr() sets all the fixed MTRR settings. But in fact MtrrSetAllMtrrs() is always used by callers to set all MTRR settings including the fixed and variable ones. The patch removes the unnecessary API MtrrSetFixedMtrr() to simplify the MtrrLib API. There is no code in edk2 and edk2-platforms repo that calls MtrrSetFixedMtrr(). Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
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