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* UefiCpuPkg: Calculate DisplayFamily correctlyLiu, Zhiguang2023-03-071-3/+3
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4348 Per SDM: DisplayFamily = Extended_Family_ID + Family_ID. DisplayModelID = (Extended_Model_ID << 4) + Family_ID. Correct the related code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Mike Maslenkin <mike.maslenkin@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Apply uncrustify changesMichael Kubacki2021-12-075-785/+865
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()Michael D Kinney2021-12-071-3/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3767 Update use of DEBUG_CODE(Expression) if Expression is a complex code block with if/while/for/case statements that use {}. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Change OPTIONAL keyword usage styleMichael D Kinney2021-12-071-5/+4
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Cpu feature data stored in memory may be migratedLou, Yun2021-10-201-3/+6
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3634 The memory allocated through "PeiAllocatePool" is located in HOB, and in DXE phase, the HOB will be migrated to a different location. After the migration, the data stored in the HOB stays the same, but the address of pointer to the memory(such as the pointers in ACPI_CPU_DATA structure) changes, which may cause "PiSmmCpuDxeSmm" driver can't find the memory(the pointers in ACPI_CPU_DATA structure) that allocated in "PeiRegisterCpuFeaturesLib", so use "PeiAllocatePages" to allocate memory instead. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Refactor initialization of CPU features during S3 resumeLou, Yun2021-09-162-15/+15
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3621 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3631 Refactor initialization of CPU features during S3 resume. In addition, the macro ACPI_CPU_DATA_STRUCTURE_UPDATE is used to fix incompatibility issue caused by ACPI_CPU_DATA structure update. It will be removed after all the platform code uses new ACPI_CPU_DATA structure. Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: NumberOfCpus may be uninitializedZeng, Star2021-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | NumberOfCpus local variable in GetAcpiCpuData will be uninitialized when CpuS3DataDxe runs before DxeRegisterCpuFeaturesLib (linked by CpuFeaturesDxe) because there is no code to initialize it at (AcpiCpuData != NULL) execution path. The issue is exposed after cefad282fb31aff3e1a6dcbd368cbbffc3fce900 and 38ee7bafa72f58982f99ac6f61eef160f80bad69. There was negligence in that code review. One further topic may be "Could EDK2 CI be enhanced to catch this kind of uninitialized local variable case?". :) This patch fixes this regression issue. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Message-Id: <20210121093944.1621-1-star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuFeature: Don't assume CpuS3DataDxe alloc RegisterTableRay Ni2021-01-201-33/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are lots of fields in ACPI_CPU_DATA structure while only followings are accessed by CpuFeature infra: * NumberOfCpus * PreSmmInitRegisterTable // pointer * RegisterTable // pointer * CpuStatus * ApLocation // pointer So it's possible that an implementation of CpuS3DataDxe doesn't allocate memory for PreSmmInitRegisterTable/RegisterTable/ApLocation. This patch handles the case when CpuS3DataDxe doesn't allocate memory for PreSmmInitRegisterTable/RegisterTable. Cc: Eric Dong <eric.dong@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3159 Signed-off-by: Ray Ni <ray.ni@intel.com> [lersek@redhat.com: update CC list, add BZ reference, add my S-o-b] [lersek@redhat.com: deal with RegisterTable and PreSmmInitRegisterTable being zero independently of each other; replacing the ASSERT()] Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210119155440.2262-2-lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/CpuFeature: reduce time complexty to calc CpuInfo.FirstRay Ni2020-12-141-49/+47
| | | | | | | | | | | | | | | | | | | | | | CpuInfo.First stores whether the current thread belongs to the first package in the platform, first core in a package, first thread in a core. But the time complexity of original algorithm to calculate the CpuInfo.First is O (n) * O (p) * O (c). n: number of processors p: number of packages c: number of cores per package The patch trades time with space by storing the first package, first core per package, first thread per core in an array. The time complexity becomes O (n). Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Yun Lou <yun.lou@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Use AllocatePages() for InitOrderStar Zeng2020-12-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The required buffer size for InitOrder will be 96K when NumberOfCpus=1024. sizeof (CPU_FEATURES_INIT_ORDER) = 96 NumberOfCpus = 1024 = 1K sizeof (CPU_FEATURES_INIT_ORDER) * NumberOfCpus = 96K AllocateZeroPool() will call to PeiServicesAllocatePool() which will use EFI_HOB_MEMORY_POOL to management memory pool. EFI_HOB_MEMORY_POOL.Header.HobLength is UINT16 type, so there is no way for AllocateZeroPool() to allocate > 64K memory. So AllocateZeroPool() could not be used anymore for the case above or even bigger required buffer size. This patch updates the code to use AllocatePages() instead of AllocateZeroPool() to allocate buffer for InitOrder. Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Feature: Support different thread count per coreRay Ni2020-12-041-53/+60
| | | | | | | | | | | | | | | | | Today's code assumes every core contains the same number of threads. It's not always TRUE for certain model. Such assumption causes system hang when thread count per core is different and there is core or package dependency between CPU features (using CPU_FEATURE_CORE_BEFORE/AFTER, CPU_FEATURE_PACKAGE_BEFORE/AFTER). The change removes such assumption by calculating the actual thread count per package and per core. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Yun Lou <yun.lou@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Support MpServices2 only case.Chasel Chiu2020-09-143-44/+28
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2883 MpServices Ppi can be replaced by MpServices2 Ppi and MpServices2 Ppi is mandatory for RegisterCpuFeaturesLib functionality, basing on this we can drop MpServices Ppi usage from the library and the constraint that both Ppis must be installed. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Match data type and format specifierZeng, Star2020-02-191-12/+12
| | | | | | | | | | | | | | | | | Match data type and format specifier for printing. 1. Type cast ProcessorNumber and FeatureIndex to UINT32 as %d only expects a UINT32. 2. Use %08x instead of %08lx for CacheControl to print Index as it is UINT32 type. 3. Use %016lx instead of %08lx for MemoryMapped to print (Index | LShiftU64 (HighIndex, 32)) as it is UINT64 type. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuFeature: Introduce First to indicate 1st unit.Ray Ni2020-02-141-1/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1584 The flow of CPU feature initialization logic is: 1. BSP calls GetConfigDataFunc() for each thread/AP; 2. Each thread/AP calls SupportFunc() to detect its own capability; 3. BSP calls InitializeFunc() for each thread/AP. There is a design gap in step #3. For a package scope feature that only requires one thread of each package does the initialization operation, what InitializeFunc() currently does is to do the initialization operation only CPU physical location Core# is 0. But in certain platform, Core#0 might be disabled in hardware level which results the certain package scope feature isn't initialized at all. The patch adds a new field First to indicate the CPU's location in its parent scope. First.Package is set for all APs/threads under first package; First.Core is set for all APs/threads under first core of each package; First.Thread is set for the AP/thread of each core. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Rename [Before|After]FeatureBitMaskRay Ni2020-02-142-33/+41
| | | | | | | The patch doesn't have any functionality impact. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER]Ray Ni2020-02-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1366 Commit b3c71b472dff2c02f0cc38d7a1959cfb2ba8420d supported MSR setting in different scopes. It added below macro: CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_THREAD_AFTER CPU_FEATURE_CORE_BEFORE CPU_FEATURE_CORE_AFTER CPU_FEATURE_PACKAGE_BEFORE CPU_FEATURE_PACKAGE_AFTER And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE and CPU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER. This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER completely. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic.Dong, Eric2019-08-211-1/+30
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.Dong, Eric2019-08-211-47/+63
| | | | | | Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.Dong, Eric2019-08-211-3/+41
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Clean up useless ConsoleLogLock spinlock.Eric Dong2019-08-092-2/+0
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060 Remove the useless ConsoleLogLock spinlock. Signed-off-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove debug message.Eric Dong2019-08-061-22/+0
| | | | | | | | | | | | This debug message may be called by BSP and APs. It may caused ASSERT when APs call this debug code. In order to avoid system boot assert, Remove this debug message. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Start all processors simultaneously.Eric Dong2019-07-295-23/+53
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 For semaphore type register, it required all processors to do the task at the same time. Current logic begins BSP's task after all APs have finished their tasks. This will caused set semaphore task hang if semaphore has package level type. This patch use new EDKII_PEI_MP_SERVICES2_PPI to start all processors at the same time to fix the potential hang issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: avoid use dynamic PCD.Dong, Eric2019-07-183-102/+79
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 Function in this library may be used by APs. Assert will be trig if AP uses dynamic pcd. This patch enhance the current code, remove the unnecessary usage of dynamic PCD. This change try to avoid report this issue again later. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiServices table.Eric Dong2019-07-182-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 AP calls CollectProcessorData() to collect processor info. CollectProcessorData function finally calls PcdGetSize function to get DynamicPCD PcdCpuFeaturesSetting value. PcdGetSize will use PeiServices table which caused below assert info: Processor Info: Package: 1, MaxCore : 4, MaxThread: 1 Package: 0, Valid Core : 4 ASSERT [CpuFeaturesPei] c:\projects\jsl\jsl_v1193\Edk2\MdePkg\Library \PeiServicesTablePointerLibIdt\PeiServicesTablePointer.c(48): PeiServices != ((void *) 0) This change uses saved global pcd size instead of calls PcdGetSize to fix this issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg DxeRegisterCpuFeaturesLib: Fix VS2012 build failureStar Zeng2019-07-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 The new VS2012 build failure is caused by 7a0df26. xxx\registercpufeatureslib\dxeregistercpufeatureslib.c(258) : warning C4701: potentially uninitialized local variable 'MpEvent' used It is a false positive alarm. MpEvent is assigned at line 238 and will be used at line 258, both lines are controlled by "if (CpuFeaturesData->NumberOfCpus > 1)". This patch initializes MpEvent to suppress incorrect compiler/analyzer warnings. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Fix an ASSERTION issueStar Zeng2019-07-113-27/+37
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 We met assertion like below, it happens when there is only one processor. ASSERT_EFI_ERROR (Status = Not started) ASSERT [CpuFeaturesDxe] X:\XXX\XXX\RegisterCpuFeaturesLib\ DxeRegisterCpuFeaturesLib.c(149): !EFI_ERROR (Status) The code should not call StartupAllAPs when there is only one processor. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-098-58/+12
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Correct comments.Eric Dong2019-04-041-2/+2
| | | | | | | | Cc: Ray Ni <Ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport.Eric Dong2019-04-043-32/+22
| | | | | | | | | | | | | | | | PcdCpuFeaturesSupport used to specify the platform policy about what CPU features this platform supports. This PCD will be used in IsCpuFeatureSupported only. Now RegisterCpuFeaturesLib use this PCD as an template to Get the pcd size. Update the code logic to replace it with PcdCpuFeaturesSetting. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCDEric Dong2019-04-044-66/+24
| | | | | | | | | | | | | | PcdCpuFeaturesUserConfiguration. Merge PcdCpuFeaturesUserConfiguration into PcdCpuFeaturesSetting. Use PcdCpuFeaturesSetting as input for the user input feature setting Use PcdCpuFeaturesSetting as output for the final CPU feature setting BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.Eric Dong2019-04-041-51/+1
| | | | | | | | | | Remove useless APIs, simplify the code logic. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Replace AcquireSpinLock.Eric Dong2019-01-151-2/+7
| | | | | | | | | | | | | | | In AcquireSpinLock function, it may call GetPerformanceCounter which final calls PeiService table. This code may also been used by AP but AP should not calls PeiService. This patch update code to avoid use AcquireSpinLock function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.Eric Dong2019-01-144-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | V3: Define union to specify the ppi or protocol. V2: 1. Initialize CpuFeaturesData->MpService in CpuInitDataInitialize and make this function been called at the begin of the initialization. 2. let all other functions use CpuFeaturesData->MpService install of locate the protocol itself. V1: GetProcessorIndex function calls GetMpPpi to get the MP Ppi. Ap will calls GetProcessorIndex function which final let AP calls PeiService. This patch avoid GetProcessorIndex call PeiService. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message.Eric Dong2019-01-141-6/+11
| | | | | | | | | | Enhance debug message format to let them easy to read. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Separate semaphore container.Eric Dong2018-11-112-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation, core and package level sync uses same semaphores. Sharing the semaphore may cause wrong execution order. For example: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependency with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependency with Feature B. The expected feature initialization order is A B C: A ---- (Core Depends) ----> B ---- (Package Depends) ----> C For a CPU has 1 package, 2 cores and 4 threads. The feature initialization order may like below: Thread#1 Thread#2 Thread#3 Thread#4 [A.Init] [A.Init] [A.Init] Release(S1, S2) Release(S1, S2) Release(S3, S4) Wait(S1) * 2 Wait(S2) * 2 <------------------------------- Core sync [B.Init] [B.Init] Release (S1,S2,S3,S4) Wait (S1) * 4 <----------------------------------------------------- Package sync Wait(S4 * 2) <- Core sync [B.Init] In above case, for thread#4, when it syncs in core level, Wait(S4) * 2 isn't blocked and [B.Init] runs. But [A.Init] hasn't run in thread#3. It's wrong! Thread#4 should execute [B.Init] after thread#3 executes [A.Init] because B core level depends on A. The reason of the wrong execution order is that S4 is released in thread#1 by calling Release (S1, S2, S3, S4) and in thread #4 by calling Release (S3, S4). To fix this issue, core level sync and package level sync should use separate semaphores. In above example, the S4 released in Release (S1, S2, S3, S4) should not be the same semaphore as that in Release (S3, S4). Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Adjust Order.Eric Dong2018-11-113-20/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V2 changes: V1 change has regression which caused by change feature order. V2 changes logic to detect dependence not only for the neighborhood features. It need to check all features in the list. V1 Changes: In current code logic, only adjust feature position if current CPU feature position not follow the request order. Just like Feature A need to be executed before feature B, but current feature A registers after feature B. So code will adjust the position for feature A, move it to just before feature B. If the position already met the requirement, code will not adjust the position. This logic has issue when met all below cases: 1. feature A has core or package level dependence with feature B. 2. feature A is register before feature B. 3. Also exist other features exist between feature A and B. Root cause is driver ignores the dependence for this case, so threads may execute not follow the dependence order. Fix this issue by change code logic to adjust feature position for CPU features which has dependence relationship. Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure.Eric Dong2018-10-311-1/+1
| | | | | | | | | | | | | | | | | | | | Build UefiCpuPkg with below configuration: Architecture(s) = IA32 Build target = NOOPT Toolchain = VS2015x86 Below error info shows up: DxeRegisterCpuFeaturesLib.lib(CpuFeaturesInitialize.obj) : error LNK2001: unresolved external symbol __allmul Valid mDependTypeStr type only have 5 items, use UINT32 type cast to fix this error. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix GCC build failure.Dong, Eric2018-10-272-2/+2
| | | | | | | Cc: Liming Gao <liming.gao@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Support combo CPU feature style.Eric Dong2018-10-263-67/+45
| | | | | | | | | | | | Current code assume only one dependence (before or after) for one feature. Enhance code logic to support feature has two dependence (before and after) type. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix ECC issues.Eric Dong2018-10-262-12/+14
| | | | | | | | | | | | | | Changes include: 1. Remove extra white space at the end of line. 2. Add comments for the new add function parameter. 3. Update IN OUT tag for function parameter. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix build failure for VS2012 and GCC49.Eric Dong2018-10-261-0/+1
| | | | | | | | | | | | Code initialized in function can't be correctly detected by build tool. Add code to clearly initialize the local variable before use it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type.Eric Dong2018-10-226-133/+939
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V4 changes include: 1. Serial debug message for different threads when program the register table. V3 changes include: 1. Use global variable instead of internal function to return string for register type and dependence type. 2. Add comments for some complicated logic. V2 changes include: 1. Add more description for the code part which need easy to understand. 2. Refine some code base on feedback for V1 changes. V1 changes include: In a system which has multiple cores, current set register value task costs huge times. After investigation, current set MSR task costs most of the times. Current logic uses SpinLock to let set MSR task as an single thread task for all cores. Because MSR has scope attribute which may cause GP fault if multiple APs set MSR at the same time, current logic use an easiest solution (use SpinLock) to avoid this issue, but it will cost huge times. In order to fix this performance issue, new solution will set MSRs base on their scope attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A must been set after MSR B has been set. Also MSR B is package scope level and MSR A is thread scope level. If system has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 and thread 2 like below: Thread 1 Thread 2 MSR B N Y MSR A Y Y If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but at this time, MSR B not been executed yet by thread 2. system may trig exception at this time. In order to fix the above issue, driver introduces semaphore logic to control the MSR execute sequence. For the above case, a semaphore will be add between MSR A and B for all threads. Semaphore has scope info for it. The possible scope value is core or package. For each thread, when it meets a semaphore during it set registers, it will 1) release semaphore (+1) for each threads in this core or package(based on the scope info for this semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based on the scope info for this semaphore). With these two steps, driver can control MSR sequence. Sample code logic like below: // // First increase semaphore count by 1 for processors in this package. // for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); } // // Second, check whether the count has reach the check number. // for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { LibWaitForSemaphore (&SemaphorePtr[ApOffset]); } Platform Requirement: 1. This change requires register MSR setting base on MSR scope info. If still register MSR for all threads, exception may raised. Known limitation: 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature PEI instance not works after this change. We plan to support async mode for PEI in phase 2 for this task. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Fix ECC issues.Eric Dong2018-09-061-1/+1
| | | | | | | | | Fix trailing white spaces and invalid line ending issue. Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Combine implementation.Eric Dong2018-08-164-218/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V1 changes: > Current code logic can't confirm CpuS3DataDxe driver start before > CpuFeaturesDxe driver. So the assumption in CpuFeaturesDxe not valid. > Add implementation for AllocateAcpiCpuData function to remove this > assumption. V2 changes: > Because CpuS3Data memory will be copy to smram at SmmReadToLock point, > so the memory type no need to be ACPI NVS type, also the address not > limit to below 4G. > This change remove the limit of ACPI NVS memory type and below 4G. V3 changes: > Remove function definition in header file. > Add STATIC in function implementation. Pass OS boot and resume from S3 test. Bugz: https://bugzilla.tianocore.org/show_bug.cgi?id=959 Reported-by: Marvin Häuser <Marvin.Haeuser@outlook.com> Suggested-by: Fan Jeff <vanjeff_919@hotmail.com> Cc: Marvin Häuser <Marvin.Haeuser@outlook.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-281-3/+3
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Delete redundant PcdGetSize PcdCpuFeaturesSupportSong, BinX2017-12-271-1/+0
| | | | | | | | | | | | | When CpuCommonFeaturesLib use RegisterCpuFeaturesLib to register CPU features, the CpuFeaturesData->BitMaskSize has already been initialized. So delete redundant PcdGetSize PcdCpuFeaturesSupport in CpuInitDataInitialize. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-271-29/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Singularize function nameSong, BinX2017-12-152-28/+28
| | | | | | | | | | | Change GetSupportPcds and GetConfigurationPcds to be singular Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-131-0/+29
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Fix buffer pointer error usage.Eric Dong2017-08-171-8/+8
| | | | | | | | | | | | | | | | | Current code allocate buffer for the pointer which later get value from PCD database. but current code error use "=" for this case. Use AllocateCopyPool instead to fix it. V2 enhanced to directly use AllocateCopyPool to get the PCD value. V3 enhanced to avoid using local temp variable. V4 enhanced to keep the functions to get the pcd values. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Shao Ming <ming.shao@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
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