From 0c0e7ef451a3f74d6756d6ec65685114b3dacea8 Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Tue, 27 Sep 2011 16:33:20 +0000 Subject: ArmPkg/ArmLib: Update Arm11 port git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12454 6f19259b-4bc3-4df7-8a09-765794883524 --- .../Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S | 67 ++++++++ .../ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm | 54 ++++++ ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c | 112 +++++++++++++ .../ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf | 42 +++++ ArmPkg/Include/Chipset/ARM1176JZ-S.h | 16 ++ ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf | 46 ------ ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf | 46 ------ ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c | 182 ++++++--------------- ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf | 51 ++++++ ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c | 133 +++++++++++++++ ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf | 51 ++++++ ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf | 47 ++++++ ArmPkg/Library/ArmLib/Arm11/Arm11Support.S | 107 +++++++++++- 13 files changed, 728 insertions(+), 226 deletions(-) create mode 100644 ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S create mode 100644 ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm create mode 100644 ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c create mode 100644 ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf delete mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf delete mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf create mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf create mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c create mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf create mode 100644 ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S new file mode 100644 index 0000000000..96acde19e8 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.S @@ -0,0 +1,67 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmCpuSynchronizeWait) +GCC_ASM_IMPORT(CArmCpuSynchronizeWait) + +// VOID +// ArmCpuSynchronizeWait ( +// IN ARM_CPU_SYNCHRONIZE_EVENT Event +// ); +ASM_PFX(ArmCpuSynchronizeWait): + cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT + // The SCU enabled is the event to tell us the Init Boot Memory is initialized + bx lr + b CArmCpuSynchronizeWait + + +#if 0 +GCC_ASM_EXPORT(ArmCpuSynchronizeWait) +GCC_ASM_EXPORT(ArmGetScuBaseAddress) +GCC_ASM_IMPORT(CArmCpuSynchronizeWait) + +// VOID +// ArmCpuSynchronizeWait ( +// IN ARM_CPU_SYNCHRONIZE_EVENT Event +// ); +ASM_PFX(ArmCpuSynchronizeWait): + cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT + // The SCU enabled is the event to tell us the Init Boot Memory is initialized + beq ArmWaitScuEnabled + b CArmCpuSynchronizeWait + +// IN None +// OUT r0 = SCU Base Address +ASM_PFX(ArmGetScuBaseAddress): + // Read Configuration Base Address Register. ArmCBar cannot be called to get + // the Configuration BAR as a stack is not necessary setup. The SCU is at the + // offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + bx lr + +ASM_PFX(ArmWaitScuEnabled): + // Read Configuration Base Address Register. ArmCBar cannot be called to get + // the Configuration BAR as a stack is not necessary setup. The SCU is at the + // offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + add r0, r0, #A9_SCU_CONTROL_OFFSET + ldr r0, [r0] + cmp r0, #1 + bne ArmWaitScuEnabled + bx lr +#endif diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm new file mode 100644 index 0000000000..d0fc2b5a8a --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Helper.asm @@ -0,0 +1,54 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include +#include + + EXPORT ArmCpuSynchronizeWait + EXPORT ArmGetScuBaseAddress + IMPORT CArmCpuSynchronizeWait + + PRESERVE8 + AREA ArmCortexA9Helper, CODE, READONLY + +// VOID +// ArmCpuSynchronizeWait ( +// IN ARM_CPU_SYNCHRONIZE_EVENT Event +// ); +ArmCpuSynchronizeWait + cmp r0, #ARM_CPU_EVENT_BOOT_MEM_INIT + // The SCU enabled is the event to tell us the Init Boot Memory is initialized + beq ArmWaitScuEnabled + b CArmCpuSynchronizeWait + +// IN None +// OUT r0 = SCU Base Address +ArmGetScuBaseAddress + // Read Configuration Base Address Register. ArmCBar cannot be called to get + // the Configuration BAR as a stack is not necessary setup. The SCU is at the + // offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + bx lr + +ArmWaitScuEnabled + // Read Configuration Base Address Register. ArmCBar cannot be called to get + // the Configuration BAR as a stack is not necessary setup. The SCU is at the + // offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + add r0, r0, #A9_SCU_CONTROL_OFFSET + ldr r0, [r0] + cmp r0, #1 + bne ArmWaitScuEnabled + bx lr + + END diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c new file mode 100644 index 0000000000..2e285d54c7 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11Lib.c @@ -0,0 +1,112 @@ +/** @file + + Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +VOID +ArmCpuSynchronizeSignal ( + IN ARM_CPU_SYNCHRONIZE_EVENT Event + ) +{ + if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) { + // Do nothing, Cortex A9 secondary cores are waiting for the SCU to be + // enabled (done by ArmCpuSetup()) as a way to know when the Init Boot + // Mem as been initialized + } else { + // Send SGI to all Secondary core to wake them up from WFI state. + ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); + } +} + +VOID +CArmCpuSynchronizeWait ( + IN ARM_CPU_SYNCHRONIZE_EVENT Event + ) +{ + // Waiting for the SGI from the primary core + ArmCallWFI (); + + // Acknowledge the interrupt and send End of Interrupt signal. + ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID); +} + +#if 0 +VOID +ArmEnableScu ( + VOID + ) +{ + INTN ScuBase; + + ScuBase = ArmGetScuBaseAddress(); + + // Invalidate all: write -1 to SCU Invalidate All register + MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff); + // Enable SCU + MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1); +} +#endif + +VOID +ArmCpuSetup ( + IN UINTN MpId + ) +{ + /*AMP mode and SMP mode + + By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is: + + 1.Write the SCU register to change CPU mode. + 2.Disable interrupts. + 3.Clean and invalidate all the D-cache. + 4.Write SMP/nAMP bit as 1. + 5.Enable interrupts. + + Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html + */ + + // If MPCore then Enable the SCU + if (ArmIsMpCore()) { + //ArmEnableScu (); + } +} + + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ) +{ +#if 0 + INTN ScuBase; + + ArmSetAuxCrBit (A9_FEATURE_SMP); + + // Make the SCU accessible in Non Secure world + if (IS_PRIMARY_CORE(MpId)) { + ScuBase = ArmGetScuBaseAddress(); + + // Allow NS access to SCU register + MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf); + // Allow NS access to Private Peripherals + MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff); + } +#endif +} + diff --git a/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf new file mode 100644 index 0000000000..2b9621c6ec --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/Arm11MpCoreLib/Arm11MpCoreLib.inf @@ -0,0 +1,42 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Arm11MpCoreLib + FILE_GUID = dc8a69e0-6be0-469c-94d3-5e6d71aa9808 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmCpuLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + ArmLib + ArmGicSecLib + IoLib + PcdLib + +[Sources.common] + Arm11Lib.c + Arm11Helper.asm | RVCT + Arm11Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase diff --git a/ArmPkg/Include/Chipset/ARM1176JZ-S.h b/ArmPkg/Include/Chipset/ARM1176JZ-S.h index 68e120abcd..8ae43c735d 100644 --- a/ArmPkg/Include/Chipset/ARM1176JZ-S.h +++ b/ArmPkg/Include/Chipset/ARM1176JZ-S.h @@ -108,4 +108,20 @@ TT_DESCRIPTOR_SECTION_AP_RW_RW | \ TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE) +#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF + +// NSACR - Non-Secure Access Control Register definitions +#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF) +#define NSACR_PLE 0 +#define NSACR_TL 0 +#define NSACR_NS_SMP 0 + +// SCR - Secure Configuration Register definitions +#define SCR_NS (1 << 0) +#define SCR_IRQ (1 << 1) +#define SCR_FIQ (1 << 2) +#define SCR_EA (1 << 3) +#define SCR_FW (1 << 4) +#define SCR_AW (1 << 5) + #endif // __ARM1176JZ_S_H__ diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf deleted file mode 100644 index cb5b8aabee..0000000000 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# Semihosting serail port lib -# -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Arm11ArmLib - FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmLib - -[Sources.common] - ../Common/ArmLibSupport.S | GCC - ../Common/ArmLibSupport.asm | RVCT - ../Common/ArmLib.c - - Arm11Support.S | GCC - Arm11Support.asm | RVCT - - Arm11Lib.c - ../Arm9/Arm9CacheInformation.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - MemoryAllocationLib - -[Protocols] - gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf deleted file mode 100644 index e3047b28f4..0000000000 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf +++ /dev/null @@ -1,46 +0,0 @@ -#/** @file -# Semihosting serail port lib -# -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = Arm11ArmLib - FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - LIBRARY_CLASS = ArmLib - -[Sources.common] - ../Common/ArmLibSupport.S | GCC - ../Common/ArmLibSupport.asm | RVCT - ../Common/ArmLib.c - - Arm11Support.S | GCC - Arm11Support.asm | RVCT - - Arm11Lib.c - ../Arm9/Arm9CacheInformation.c - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - -[LibraryClasses] - PrePiLib - -[Protocols] - gEfiCpuArchProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c index 1257be8cf6..c512c03557 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c @@ -1,133 +1,49 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include - -VOID -FillTranslationTable ( - IN UINT32 *TranslationTable, - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion - ) -{ - UINT32 *Entry; - UINTN Sections; - UINTN Index; - UINT32 Attributes; - UINT32 PhysicalBase = MemoryRegion->PhysicalBase; - - switch (MemoryRegion->Attributes) { - case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: - Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); - break; - case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: - Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); - break; - case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); - break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK: - Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); - break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH: - Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); - break; - case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED: - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); - break; - default: - Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); - break; - } - - Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); - Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 ); - - for (Index = 0; Index < Sections; Index++) - { - *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes; - PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; - } -} - -VOID -EFIAPI -ArmConfigureMmu ( - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, - OUT VOID **TranslationTableBase OPTIONAL, - OUT UINTN *TranslationTableSize OPTIONAL - ) -{ - VOID *TranslationTable; - - // Allocate pages for translation table. - TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT)); - TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK); - - if (TranslationTableBase != NULL) { - *TranslationTableBase = TranslationTable; - } - - if (TranslationTableBase != NULL) { - *TranslationTableSize = TRANSLATION_TABLE_SIZE; - } - - ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE); - - ArmCleanInvalidateDataCache(); - ArmInvalidateInstructionCache(); - ArmInvalidateTlb(); - - ArmDisableDataCache(); - ArmDisableInstructionCache(); - ArmDisableMmu(); - - // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache(); - ArmInvalidateInstructionCache(); - - while (MemoryTable->Length != 0) { - FillTranslationTable(TranslationTable, MemoryTable); - MemoryTable++; - } - - ArmSetTTBR0(TranslationTable); - - ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) | - DOMAIN_ACCESS_CONTROL_NONE(14) | - DOMAIN_ACCESS_CONTROL_NONE(13) | - DOMAIN_ACCESS_CONTROL_NONE(12) | - DOMAIN_ACCESS_CONTROL_NONE(11) | - DOMAIN_ACCESS_CONTROL_NONE(10) | - DOMAIN_ACCESS_CONTROL_NONE( 9) | - DOMAIN_ACCESS_CONTROL_NONE( 8) | - DOMAIN_ACCESS_CONTROL_NONE( 7) | - DOMAIN_ACCESS_CONTROL_NONE( 6) | - DOMAIN_ACCESS_CONTROL_NONE( 5) | - DOMAIN_ACCESS_CONTROL_NONE( 4) | - DOMAIN_ACCESS_CONTROL_NONE( 3) | - DOMAIN_ACCESS_CONTROL_NONE( 2) | - DOMAIN_ACCESS_CONTROL_NONE( 1) | - DOMAIN_ACCESS_CONTROL_MANAGER(0)); - - ArmEnableInstructionCache(); - ArmEnableDataCache(); - ArmEnableMmu(); -} - - - - +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include + +VOID +EFIAPI +ArmWriteVBar ( + IN UINT32 VectorBase + ) +{ + ASSERT(FeaturePcdGet (PcdRelocateVectorTable) == TRUE); + + if (VectorBase == 0x0) { + ArmSetLowVectors (); + } else if (VectorBase == 0xFFFF0000) { + ArmSetHighVectors (); + } else { + // Feature not supported by ARM11. The Vector Table is either at 0x0 or 0xFFFF0000 + ASSERT(0); + } +} + +UINT32 +EFIAPI +ArmReadVBar ( + VOID + ) +{ + ASSERT((FeaturePcdGet (PcdRelocateVectorTable) == TRUE) && ((PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) || (PcdGet32 (PcdCpuVectorBaseAddress) == 0xFFFF0000))); + return PcdGet32 (PcdCpuVectorBaseAddress); +} + diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf new file mode 100644 index 0000000000..b28a4578b0 --- /dev/null +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf @@ -0,0 +1,51 @@ +#/** @file +# Semihosting serail port lib +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Arm11ArmLib + FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmLib + +[Sources.common] + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT + ../Common/ArmLib.c + + Arm11Support.S | GCC + Arm11Support.asm | RVCT + + Arm11Lib.c + Arm11LibMem.c + ../Arm9/Arm9CacheInformation.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + MemoryAllocationLib + +[Protocols] + gEfiCpuArchProtocolGuid + +[FeaturePcd] + gArmTokenSpaceGuid.PcdRelocateVectorTable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmCacheOperationThreshold + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c new file mode 100644 index 0000000000..1257be8cf6 --- /dev/null +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c @@ -0,0 +1,133 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +VOID +FillTranslationTable ( + IN UINT32 *TranslationTable, + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion + ) +{ + UINT32 *Entry; + UINTN Sections; + UINTN Index; + UINT32 Attributes; + UINT32 PhysicalBase = MemoryRegion->PhysicalBase; + + switch (MemoryRegion->Attributes) { + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: + Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0); + break; + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH: + Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0); + break; + case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED: + Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); + break; + case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK: + Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1); + break; + case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH: + Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1); + break; + case ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED: + Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1); + break; + default: + Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); + break; + } + + Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); + Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 ); + + for (Index = 0; Index < Sections; Index++) + { + *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes; + PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; + } +} + +VOID +EFIAPI +ArmConfigureMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable, + OUT VOID **TranslationTableBase OPTIONAL, + OUT UINTN *TranslationTableSize OPTIONAL + ) +{ + VOID *TranslationTable; + + // Allocate pages for translation table. + TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT)); + TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK); + + if (TranslationTableBase != NULL) { + *TranslationTableBase = TranslationTable; + } + + if (TranslationTableBase != NULL) { + *TranslationTableSize = TRANSLATION_TABLE_SIZE; + } + + ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE); + + ArmCleanInvalidateDataCache(); + ArmInvalidateInstructionCache(); + ArmInvalidateTlb(); + + ArmDisableDataCache(); + ArmDisableInstructionCache(); + ArmDisableMmu(); + + // Make sure nothing sneaked into the cache + ArmCleanInvalidateDataCache(); + ArmInvalidateInstructionCache(); + + while (MemoryTable->Length != 0) { + FillTranslationTable(TranslationTable, MemoryTable); + MemoryTable++; + } + + ArmSetTTBR0(TranslationTable); + + ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) | + DOMAIN_ACCESS_CONTROL_NONE(14) | + DOMAIN_ACCESS_CONTROL_NONE(13) | + DOMAIN_ACCESS_CONTROL_NONE(12) | + DOMAIN_ACCESS_CONTROL_NONE(11) | + DOMAIN_ACCESS_CONTROL_NONE(10) | + DOMAIN_ACCESS_CONTROL_NONE( 9) | + DOMAIN_ACCESS_CONTROL_NONE( 8) | + DOMAIN_ACCESS_CONTROL_NONE( 7) | + DOMAIN_ACCESS_CONTROL_NONE( 6) | + DOMAIN_ACCESS_CONTROL_NONE( 5) | + DOMAIN_ACCESS_CONTROL_NONE( 4) | + DOMAIN_ACCESS_CONTROL_NONE( 3) | + DOMAIN_ACCESS_CONTROL_NONE( 2) | + DOMAIN_ACCESS_CONTROL_NONE( 1) | + DOMAIN_ACCESS_CONTROL_MANAGER(0)); + + ArmEnableInstructionCache(); + ArmEnableDataCache(); + ArmEnableMmu(); +} + + + + diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf new file mode 100644 index 0000000000..cd36d8b3c7 --- /dev/null +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf @@ -0,0 +1,51 @@ +#/** @file +# Semihosting serail port lib +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Arm11ArmLib + FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmLib + +[Sources.common] + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT + ../Common/ArmLib.c + + Arm11Support.S | GCC + Arm11Support.asm | RVCT + + Arm11Lib.c + Arm11LibMem.c + ../Arm9/Arm9CacheInformation.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + PrePiLib + +[Protocols] + gEfiCpuArchProtocolGuid + +[FeaturePcd] + gArmTokenSpaceGuid.PcdRelocateVectorTable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmCacheOperationThreshold + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf new file mode 100644 index 0000000000..4c3566e3c5 --- /dev/null +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf @@ -0,0 +1,47 @@ +#/** @file +# Semihosting serail port lib +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Arm11LibSec + FILE_GUID = bfecdbc7-a860-4993-bc09-8e3ea762a758 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmLib + +[Sources.common] + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT + ../Common/ArmLib.c + + Arm11Support.S | GCC + Arm11Support.asm | RVCT + + Arm11Lib.c + ../Arm9/Arm9CacheInformation.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[Protocols] + gEfiCpuArchProtocolGuid + +[FeaturePcd] + gArmTokenSpaceGuid.PcdRelocateVectorTable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmCacheOperationThreshold + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S index 35774a8e62..7ff377c023 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S @@ -1,6 +1,7 @@ #------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -16,6 +17,8 @@ .text .align 2 +GCC_ASM_EXPORT(ArmDisableCachesAndMmu) +GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb) GCC_ASM_EXPORT(ArmCleanInvalidateDataCache) GCC_ASM_EXPORT(ArmCleanDataCache) GCC_ASM_EXPORT(ArmInvalidateDataCache) @@ -35,11 +38,39 @@ GCC_ASM_EXPORT(ArmDisableBranchPrediction) GCC_ASM_EXPORT(ArmDataMemoryBarrier) GCC_ASM_EXPORT(ArmDataSyncronizationBarrier) GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier) +GCC_ASM_EXPORT(ArmSetLowVectors) +GCC_ASM_EXPORT(ArmSetHighVectors) +GCC_ASM_EXPORT(ArmIsMpCore) +GCC_ASM_EXPORT(ArmCallWFI) +GCC_ASM_EXPORT(ArmReadMpidr) +GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) +GCC_ASM_EXPORT(ArmEnableFiq) +GCC_ASM_EXPORT(ArmDisableFiq) +GCC_ASM_EXPORT(ArmEnableInterrupts) +GCC_ASM_EXPORT(ArmDisableInterrupts) +GCC_ASM_EXPORT (ArmEnableVFP) +Arm11PartNumberMask: .word 0xFFF0 +Arm11PartNumber: .word 0xB020 .set DC_ON, (0x1<<2) .set IC_ON, (0x1<<12) .set XP_ON, (0x1<<23) +.set CTRL_M_BIT, (1 << 0) +.set CTRL_C_BIT, (1 << 2) +.set CTRL_I_BIT, (1 << 12) + +ASM_PFX(ArmDisableCachesAndMmu): + mrc p15, 0, r0, c1, c0, 0 @ Get control register + bic r0, r0, #CTRL_M_BIT @ Disable MMU + bic r0, r0, #CTRL_C_BIT @ Disable D Cache + bic r0, r0, #CTRL_I_BIT @ Disable I Cache + mcr p15, 0, r0, c1, c0, 0 @ Write control register + bx LR + +ASM_PFX(ArmInvalidateInstructionAndDataTlb): + mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB + bx lr ASM_PFX(ArmInvalidateDataCacheEntryByMVA): mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line @@ -152,6 +183,80 @@ ASM_PFX(ArmInstructionSynchronizationBarrier): mov R0, #0 mcr P15, #0, R0, C7, C5, #4 bx LR - + +ASM_PFX(ArmSetLowVectors): + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00002000 @ clear V bit + mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) + bx LR + +ASM_PFX(ArmSetHighVectors): + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) + orr r0, r0, #0x00002000 @ clear V bit + mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) + bx LR + +ASM_PFX(ArmIsMpCore): + push { r1 } + mrc p15, 0, r0, c0, c0, 0 + # Extract Part Number to check it is an ARM11MP core (0xB02) + LoadConstantToReg (Arm11PartNumberMask, r1) + and r0, r0, r1 + LoadConstantToReg (Arm11PartNumber, r1) + cmp r0, r1 + movne r0, #0 + pop { r1 } + bx lr + +ASM_PFX(ArmCallWFI): + wfi + bx lr + +ASM_PFX(ArmReadMpidr): + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + bx lr + +ASM_PFX(ArmEnableFiq): + mrs R0,CPSR + bic R0,R0,#0x40 @Enable FIQ interrupts + msr CPSR_c,R0 + bx LR + +ASM_PFX(ArmDisableFiq): + mrs R0,CPSR + orr R1,R0,#0x40 @Disable FIQ interrupts + msr CPSR_c,R1 + tst R0,#0x80 + moveq R0,#1 + movne R0,#0 + bx LR + +ASM_PFX(ArmEnableInterrupts): + mrs R0,CPSR + bic R0,R0,#0x80 @Enable IRQ interrupts + msr CPSR_c,R0 + bx LR + +ASM_PFX(ArmDisableInterrupts): + mrs R0,CPSR + orr R1,R0,#0x80 @Disable IRQ interrupts + msr CPSR_c,R1 + tst R0,#0x80 + moveq R0,#1 + movne R0,#0 + bx LR + +ASM_PFX(ArmEnableVFP): + # Read CPACR (Coprocessor Access Control Register) + mrc p15, 0, r0, c1, c0, 2 + # Enable VPF access (Full Access to CP10, CP11) (V* instructions) + orr r0, r0, #0x00f00000 + # Write back CPACR (Coprocessor Access Control Register) + mcr p15, 0, r0, c1, c0, 2 + # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. + mov r0, #0x40000000 + #TODO: Fixme - need compilation flag + #fmxr FPEXC, r0 + bx lr ASM_FUNCTION_REMOVE_IF_UNREFERENCED -- cgit v1.2.3