From 34b162d078aa59d55059f08a0f15dd114e7b7db4 Mon Sep 17 00:00:00 2001 From: Star Zeng Date: Thu, 14 Mar 2019 10:10:21 +0800 Subject: UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedly BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek Cc: Eric Dong Cc: Ruiyu Ni Cc: Chandana Kumar Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng Reviewed-by: Eric Dong --- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c index 56b1b551d9..3f7c933e51 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -1,7 +1,7 @@ /** @file AESNI feature. - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -123,7 +123,7 @@ AesniInitialize ( MSR_SANDY_BRIDGE_FEATURE_CONFIG, MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER, Bits.AESConfiguration, - BIT1 | ((State) ? 0 : BIT0) + BIT0 | ((State) ? 0 : BIT1) ); } } -- cgit v1.2.3