From 8bcddbcce2fa9eaa2e2e1ee2bb469189f76b7cbd Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Thu, 18 May 2023 11:00:54 +0100 Subject: ArmPkg: Adjust variable type and cast for RegShift & RegOffset According to the GIC architecture version 3 and 4 specification, the maximum number of INTID bits supported in the CPU interface is 24. Considering this the RegShift variable is not required to be more than 8 bits. Therefore, make the RegShift variable type to UINT8. Also add necessary typecasts when calculating the RegOffset and RegShift values. Signed-off-by: Sami Mujawar --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 24 ++++++++++++------------ ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 6 +++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index 0127cca3bf..8f3315d76f 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -228,13 +228,13 @@ ArmGicSetInterruptPriority ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; // Calculate register offset and bit position - RegOffset = Source / 4; - RegShift = (Source % 4) * 8; + RegOffset = (UINT32)(Source / 4); + RegShift = (UINT8)((Source % 4) * 8); Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || @@ -272,13 +272,13 @@ ArmGicEnableInterrupt ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; // Calculate enable register offset and bit position - RegOffset = Source / 32; - RegShift = Source % 32; + RegOffset = (UINT32)(Source / 32); + RegShift = (UINT8)(Source % 32); Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || @@ -317,13 +317,13 @@ ArmGicDisableInterrupt ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; // Calculate enable register offset and bit position - RegOffset = Source / 32; - RegShift = Source % 32; + RegOffset = (UINT32)(Source / 32); + RegShift = (UINT8)(Source % 32); Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || @@ -361,14 +361,14 @@ ArmGicIsInterruptEnabled ( ) { UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; ARM_GIC_ARCH_REVISION Revision; UINTN GicCpuRedistributorBase; UINT32 Interrupts; // Calculate enable register offset and bit position - RegOffset = Source / 32; - RegShift = Source % 32; + RegOffset = (UINT32)(Source / 32); + RegShift = (UINT8)(Source % 32); Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c index a7970e51b3..cd65cf06d7 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -393,7 +393,7 @@ GicV2DxeInitialize ( EFI_STATUS Status; UINTN Index; UINT32 RegOffset; - UINTN RegShift; + UINT8 RegShift; UINT32 CpuTarget; // Make sure the Interrupt Controller Protocol is not already installed in @@ -411,8 +411,8 @@ GicV2DxeInitialize ( GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index); // Set Priority - RegOffset = Index / 4; - RegShift = (Index % 4) * 8; + RegOffset = (UINT32)(Index / 4); + RegShift = (UINT8)((Index % 4) * 8); MmioAndThenOr32 ( mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), ~(0xff << RegShift), -- cgit v1.2.3