From 1bb76029eff4993b31dbbb19acd86d1c8ad4933f Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Fri, 22 Feb 2019 19:43:28 +0000 Subject: ArmPkg: Fix writes to GICv3 GICD_IROUTER reg According to ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0, GICD_IROUTER is a 64-bit register. Fixed code to use 64 bit MMIO write operations so that the Aff3 value (bits [39:32]) is written to GICD_IROUTER. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar Reported-by: Carl van Schaik Reviewed-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'ArmPkg/Drivers') diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db3171..67c74f7965 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2017, ARM Limited. All rights reserved. +* Copyright (c) 2011-2018, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -467,7 +467,7 @@ GicV3DxeInitialize ( // Route the SPIs to the primary CPU. SPIs start at the INTID 32 for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { - MmioWrite32 ( + MmioWrite64 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget ); -- cgit v1.2.3