From 0c8ea9fe1adbbee230ee0c68f28b68ca2b0534bc Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Thu, 19 Mar 2020 10:37:05 -0600 Subject: ArmPkg/ArmLib: Fix cache-invalidate initial page tables Because of a bug, current EL gets passed to DC IVAC instruction instead of the VA entry that needs to be invalidated. Signed-off-by: Ashish Singhal Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ArmPkg/Library/ArmLib') diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index f744cd6738..ba0ec5682b 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR) ASM_FUNC(ArmUpdateTranslationTableEntry) dsb nshst lsr x1, x1, #12 - EL1_OR_EL2_OR_EL3(x0) + EL1_OR_EL2_OR_EL3(x2) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 mrs x2, sctlr_el1 b 4f -- cgit v1.2.3