From 35d9b7ea2d46f784365c14eb293fcd802a2bafff Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Wed, 4 May 2022 02:48:11 +0800 Subject: ArmPkg: Remove RVCT support RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran Reviewed-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 174 ------------ ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm | 107 -------- .../Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm | 93 ------- ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 292 --------------------- ArmPkg/Library/ArmLib/ArmBaseLib.inf | 5 - 5 files changed, 671 deletions(-) delete mode 100644 ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm delete mode 100644 ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm delete mode 100644 ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm delete mode 100644 ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm (limited to 'ArmPkg/Library/ArmLib') diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm deleted file mode 100644 index 1265dddea6..0000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm +++ /dev/null @@ -1,174 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------------ - - INCLUDE AsmMacroIoLib.inc - - - INCLUDE AsmMacroExport.inc - - RVCT_ASM_EXPORT ArmReadMidr - mrc p15,0,R0,c0,c0,0 - bx LR - - RVCT_ASM_EXPORT ArmCacheInfo - mrc p15,0,R0,c0,c0,1 - bx LR - - RVCT_ASM_EXPORT ArmGetInterruptState - mrs R0,CPSR - tst R0,#0x80 // Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - - RVCT_ASM_EXPORT ArmGetFiqState - mrs R0,CPSR - tst R0,#0x40 // Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - - RVCT_ASM_EXPORT ArmSetDomainAccessControl - mcr p15,0,r0,c3,c0,0 - bx lr - - RVCT_ASM_EXPORT CPSRMaskInsert - stmfd sp!, {r4-r12, lr} // save all the banked registers - mov r3, sp // copy the stack pointer into a non-banked register - mrs r2, cpsr // read the cpsr - bic r2, r2, r0 // clear mask in the cpsr - and r1, r1, r0 // clear bits outside the mask in the input - orr r2, r2, r1 // set field - msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch) - isb - mov sp, r3 // restore stack pointer - ldmfd sp!, {r4-r12, lr} // restore registers - bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) - - RVCT_ASM_EXPORT CPSRRead - mrs r0, cpsr - bx lr - - RVCT_ASM_EXPORT ArmReadCpacr - mrc p15, 0, r0, c1, c0, 2 - bx lr - - RVCT_ASM_EXPORT ArmWriteCpacr - mcr p15, 0, r0, c1, c0, 2 - isb - bx lr - - RVCT_ASM_EXPORT ArmWriteAuxCr - mcr p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmReadAuxCr - mrc p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmSetTTBR0 - mcr p15,0,r0,c2,c0,0 - isb - bx lr - - RVCT_ASM_EXPORT ArmSetTTBCR - mcr p15, 0, r0, c2, c0, 2 - isb - bx lr - - RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress - mrc p15,0,r0,c2,c0,0 - MOV32 r1, 0xFFFFC000 - and r0, r0, r1 - isb - bx lr - -// -//VOID -//ArmUpdateTranslationTableEntry ( -// IN VOID *TranslationTableEntry // R0 -// IN VOID *MVA // R1 -// ); - RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry - mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA - dsb - mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA - mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmInvalidateTlb - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmReadScr - mrc p15, 0, r0, c1, c1, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteScr - mcr p15, 0, r0, c1, c1, 0 - isb - bx lr - - RVCT_ASM_EXPORT ArmReadHVBar - mrc p15, 4, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteHVBar - mcr p15, 4, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmReadMVBar - mrc p15, 0, r0, c12, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmWriteMVBar - mcr p15, 0, r0, c12, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmCallWFE - wfe - bx lr - - RVCT_ASM_EXPORT ArmCallSEV - sev - bx lr - - RVCT_ASM_EXPORT ArmReadSctlr - mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data) - bx lr - - RVCT_ASM_EXPORT ArmWriteSctlr - mcr p15, 0, r0, c1, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmReadCpuActlr - mrc p15, 0, r0, c1, c0, 1 - bx lr - - RVCT_ASM_EXPORT ArmWriteCpuActlr - mcr p15, 0, r0, c1, c0, 1 - dsb - isb - bx lr - - RVCT_ASM_EXPORT ArmGetPhysicalAddressBits - mrc p15, 0, r0, c0, c1, 4 ; MMFR0 - and r0, r0, #0xf ; VMSA [3:0] - cmp r0, #5 ; >= 5 implies LPAE support - movlt r0, #32 ; 32 bits if no LPAE - movge r0, #40 ; 40 bits if LPAE - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm deleted file mode 100644 index e14f156625..0000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm +++ /dev/null @@ -1,107 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------------ - - - - INCLUDE AsmMacroExport.inc - - -//------------------------------------------------------------------------------ - - RVCT_ASM_EXPORT ArmIsMpCore - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) & U bit (bit30) - and R0, R0, #0xC0000000 - // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system - cmp R0, #0x80000000 - moveq R0, #1 - movne R0, #0 - bx LR - - RVCT_ASM_EXPORT ArmEnableAsynchronousAbort - cpsie a - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableAsynchronousAbort - cpsid a - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableIrq - cpsie i - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableIrq - cpsid i - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableFiq - cpsie f - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableFiq - cpsid f - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableInterrupts - cpsie if - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableInterrupts - cpsid if - isb - bx LR - - RVCT_ASM_EXPORT ArmReadIdMmfr4 - mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register - bx LR - -// UINTN -// ReadCCSIDR ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCCSIDR - mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) - bx lr - -// UINT32 -// ReadCCSIDR2 ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCCSIDR2 - mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2) - bx lr - -// UINT32 -// ReadCLIDR ( -// IN UINT32 CSSELR -// ) - RVCT_ASM_EXPORT ReadCLIDR - mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register - bx lr - - RVCT_ASM_EXPORT ArmReadNsacr - mrc p15, 0, r0, c1, c1, 2 - bx lr - - RVCT_ASM_EXPORT ArmWriteNsacr - mcr p15, 0, r0, c1, c1, 2 - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm deleted file mode 100644 index 6896c1be2b..0000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm +++ /dev/null @@ -1,93 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2011, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------------ - - - INCLUDE AsmMacroExport.inc - PRESERVE8 - - RVCT_ASM_EXPORT ArmReadCntFrq - mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ - bx lr - - RVCT_ASM_EXPORT ArmWriteCntFrq - mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ - bx lr - - RVCT_ASM_EXPORT ArmReadCntPct - mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntkCtl - mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntkCtl - mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpTval - mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpTval - mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpCtl - mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpCtl - mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvTval - mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvTval - mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCtl - mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvCtl - mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCt - mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntpCval - mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntpCval - mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvCval - mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvCval - mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register) - bx lr - - RVCT_ASM_EXPORT ArmReadCntvOff - mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register) - bx lr - - RVCT_ASM_EXPORT ArmWriteCntvOff - mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register) - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm deleted file mode 100644 index 3146c2b521..0000000000 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm +++ /dev/null @@ -1,292 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. -// -// SPDX-License-Identifier: BSD-2-Clause-Patent -// -//------------------------------------------------------------------------------ - - - INCLUDE AsmMacroExport.inc - PRESERVE8 - -DC_ON EQU ( 0x1:SHL:2 ) -IC_ON EQU ( 0x1:SHL:12 ) -CTRL_M_BIT EQU (1 << 0) -CTRL_C_BIT EQU (1 << 2) -CTRL_B_BIT EQU (1 << 7) -CTRL_I_BIT EQU (1 << 12) - - - RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line - bx lr - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA - mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU - mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor - bx lr - - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA - mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU - bx lr - - - RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line - bx lr - - - RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line - bx lr - - - RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line - bx lr - - - RVCT_ASM_EXPORT ArmInvalidateInstructionCache - mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - - mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB - mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableCachesAndMmu - mrc p15, 0, r0, c1, c0, 0 ; Get control register - bic r0, r0, #CTRL_M_BIT ; Disable MMU - bic r0, r0, #CTRL_C_BIT ; Disable D Cache - bic r0, r0, #CTRL_I_BIT ; Disable I Cache - mcr p15, 0, r0, c1, c0, 0 ; Write control register - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmMmuEnabled - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - and R0,R0,#1 - bx LR - - RVCT_ASM_EXPORT ArmEnableDataCache - ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableDataCache - ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableInstructionCache - ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableInstructionCache - ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableSWPInstruction - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00000400 - mcr p15, 0, r0, c1, c0, 0 - isb - bx LR - - RVCT_ASM_EXPORT ArmEnableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmDisableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - - RVCT_ASM_EXPORT ArmSetLowVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmSetHighVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00002000 ; Set V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - - RVCT_ASM_EXPORT ArmV7AllDataCachesOperation - stmfd SP!,{r4-r12, LR} - mov R1, R0 ; Save Function call in R1 - mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR - ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) - mov R3, R3, LSR #23 ; Cache level value (naturally aligned) - beq Finished - mov R10, #0 - -Loop1 - add R2, R10, R10, LSR #1 ; Work out 3xcachelevel - mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level - and R12, R12, #7 ; get those 3 bits alone - cmp R12, #2 - blt Skip ; no cache or only instruction cache at this level - mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg - mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) - and R2, R12, #&7 ; extract the line length field - add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) - ldr R4, =0x3FF - ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) - clz R5, R4 ; R5 is the bit position of the way size increment - ldr R7, =0x00007FFF - ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) - -Loop2 - mov R9, R4 ; R9 working copy of the max way size (right aligned) - -Loop3 - orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 - orr R0, R0, R7, LSL R2 ; factor in the index number - - blx R1 - - subs R9, R9, #1 ; decrement the way number - bge Loop3 - subs R7, R7, #1 ; decrement the index - bge Loop2 -Skip - add R10, R10, #2 ; increment the cache number - cmp R3, R10 - bgt Loop1 - -Finished - dsb - ldmfd SP!, {r4-r12, lr} - bx LR - - RVCT_ASM_EXPORT ArmDataMemoryBarrier - dmb - bx LR - - RVCT_ASM_EXPORT ArmDataSynchronizationBarrier - dsb - bx LR - - RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier - isb - bx LR - - RVCT_ASM_EXPORT ArmReadVBar - // Set the Address of the Vector Table in the VBAR register - mrc p15, 0, r0, c12, c0, 0 - bx lr - - RVCT_ASM_EXPORT ArmWriteVBar - // Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 - // Ensure the SCTLR.V bit is clear - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx lr - - RVCT_ASM_EXPORT ArmEnableVFP - // Read CPACR (Coprocessor Access Control Register) - mrc p15, 0, r0, c1, c0, 2 - // Enable VPF access (Full Access to CP10, CP11) (V* instructions) - orr r0, r0, #0x00f00000 - // Write back CPACR (Coprocessor Access Control Register) - mcr p15, 0, r0, c1, c0, 2 - isb - // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. - mov r0, #0x40000000 - mcr p10,#0x7,r0,c8,c0,#0 - bx lr - - RVCT_ASM_EXPORT ArmCallWFI - wfi - bx lr - -//Note: Return 0 in Uniprocessor implementation - RVCT_ASM_EXPORT ArmReadCbar - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register - bx lr - - RVCT_ASM_EXPORT ArmReadMpidr - mrc p15, 0, r0, c0, c0, 5 ; read MPIDR - bx lr - - RVCT_ASM_EXPORT ArmReadTpidrurw - mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW - bx lr - - RVCT_ASM_EXPORT ArmWriteTpidrurw - mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW - bx lr - - RVCT_ASM_EXPORT ArmIsArchTimerImplemented - mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 - and r0, r0, #0x000F0000 - bx lr - - RVCT_ASM_EXPORT ArmReadIdPfr1 - mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register - bx lr - - END diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/ArmBaseLib.inf index f61c71b673..e37d85bee4 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -30,11 +30,6 @@ Arm/ArmV7Support.S | GCC Arm/ArmV7ArchTimerSupport.S | GCC - Arm/ArmLibSupport.asm | RVCT - Arm/ArmLibSupportV7.asm | RVCT - Arm/ArmV7Support.asm | RVCT - Arm/ArmV7ArchTimerSupport.asm | RVCT - [Sources.AARCH64] AArch64/AArch64Lib.h AArch64/AArch64Lib.c -- cgit v1.2.3