From 2afeabd1a9cee51745f51b7b51d02f19c0a36429 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 8 Oct 2015 18:51:56 +0000 Subject: ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXN The non-privileged execute never (UXN) page table bit defined for the EL1&0 translation regime and the execute never (XN) bit defined for the EL2 and EL3 translation regimes happen to share the same bit position, but they are in fact defined distinctly by the architecture. So define both bits explicitly, and add comments in places where we take advantage of the fact that they share the same bit position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18585 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'ArmPkg/Library') diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index 3765d61ccd..d82c82c202 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -335,7 +335,8 @@ GetBlockEntryListFromAddress ( if (Attributes & TT_PXN_MASK) { TableAttributes = TT_TABLE_PXN; } - if (Attributes & TT_UXN_MASK) { + // XN maps to UXN in the EL1&0 translation regime + if (Attributes & TT_XN_MASK) { TableAttributes = TT_TABLE_XN; } if (Attributes & TT_NS) { -- cgit v1.2.3