From 429309e0c6b74792d679681a8edd0d5ae0ff850c Mon Sep 17 00:00:00 2001 From: Michael Kubacki Date: Sun, 5 Dec 2021 14:53:50 -0800 Subject: ArmPkg: Apply uncrustify changes REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish Cc: Leif Lindholm Cc: Michael D Kinney Signed-off-by: Michael Kubacki Reviewed-by: Andrew Fish --- ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c | 46 +- .../ArmCacheMaintenanceLib.c | 68 +- .../ArmDisassemblerLib/Aarch64Disassembler.c | 12 +- .../Library/ArmDisassemblerLib/ArmDisassembler.c | 150 +- .../Library/ArmDisassemblerLib/ThumbDisassembler.c | 1681 ++++++++++---------- .../ArmExceptionLib/AArch64/AArch64Exception.c | 22 +- ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c | 17 +- ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c | 135 +- .../ArmGenericTimerPhyCounterLib.c | 15 +- .../ArmGenericTimerVirtCounterLib.c | 15 +- ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c | 5 +- ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c | 3 +- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 6 +- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 7 +- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 4 +- ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h | 35 +- ArmPkg/Library/ArmLib/ArmLib.c | 14 +- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 46 +- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 331 ++-- .../ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c | 21 +- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c | 4 +- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 212 +-- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 170 +- ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c | 2 +- .../ArmPsciResetSystemLib/ArmPsciResetSystemLib.c | 36 +- ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c | 2 +- .../ArmSmcPsciResetSystemLib.c | 44 +- ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c | 322 ++-- ArmPkg/Library/ArmSoftFloatLib/platform.h | 6 +- ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c | 33 +- ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c | 51 +- ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c | 29 +- ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c | 29 +- ArmPkg/Library/CompilerIntrinsicsLib/memset.c | 75 +- ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c | 27 +- .../DebugAgentSymbolsBaseLib.c | 179 ++- .../DebugPeCoffExtraActionLib.c | 62 +- .../AArch64/DefaultExceptionHandler.c | 264 +-- .../Arm/DefaultExceptionHandler.c | 226 +-- .../DefaultExceptionHandlerUefi.c | 19 +- .../Library/LinuxBootBootManagerLib/LinuxBootBm.c | 27 +- ArmPkg/Library/OpteeLib/Optee.c | 272 ++-- ArmPkg/Library/OpteeLib/OpteeSmc.h | 28 +- .../PeiServicesTablePointer.c | 12 +- ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c | 481 +++--- .../RvdPeCoffExtraActionLib.c | 47 +- ArmPkg/Library/SemiHostingDebugLib/DebugLib.c | 54 +- .../SemiHostingSerialPortLib/SerialPortLib.c | 63 +- ArmPkg/Library/SemihostLib/SemihostLib.c | 47 +- ArmPkg/Library/SemihostLib/SemihostPrivate.h | 140 +- .../StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c | 64 +- 51 files changed, 3110 insertions(+), 2550 deletions(-) (limited to 'ArmPkg/Library') diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c index 4b1c9ac49e..d663a76a9b 100644 --- a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c +++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c @@ -7,7 +7,6 @@ **/ - #include #include #include @@ -16,16 +15,15 @@ #include #include -#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U) +#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U) // Select appropriate multiply function for platform architecture. #ifdef MDE_CPU_ARM -#define MULT_U64_X_N MultU64x32 +#define MULT_U64_X_N MultU64x32 #else -#define MULT_U64_X_N MultU64x64 +#define MULT_U64_X_N MultU64x64 #endif - RETURN_STATUS EFIAPI TimerConstructor ( @@ -36,7 +34,6 @@ TimerConstructor ( // Check if the ARM Generic Timer Extension is implemented. // if (ArmIsArchTimerImplemented ()) { - // // Check if Architectural Timer frequency is pre-determined by the platform // (ie. nonzero). @@ -49,7 +46,7 @@ TimerConstructor ( // ASSERT (TICKS_PER_MICRO_SEC); -#ifdef MDE_CPU_ARM + #ifdef MDE_CPU_ARM // // Only set the frequency for ARMv7. We expect the secure firmware to // have already done it. @@ -59,7 +56,8 @@ TimerConstructor ( if (ArmHasSecurityExtensions ()) { ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz)); } -#endif + + #endif } // @@ -68,7 +66,6 @@ TimerConstructor ( // If the reset value (0) is returned, just ASSERT. // ASSERT (ArmGenericTimerGetTimerFreq () != 0); - } else { DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n")); ASSERT (0); @@ -90,16 +87,16 @@ EFIAPI GetPlatformTimerFreq ( ) { - UINTN TimerFreq; + UINTN TimerFreq; TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz); if (TimerFreq == 0) { TimerFreq = ArmGenericTimerGetTimerFreq (); } + return TimerFreq; } - /** Stalls the CPU for the number of microseconds specified by MicroSeconds. @@ -111,11 +108,11 @@ GetPlatformTimerFreq ( UINTN EFIAPI MicroSecondDelay ( - IN UINTN MicroSeconds + IN UINTN MicroSeconds ) { - UINT64 TimerTicks64; - UINT64 SystemCounterVal; + UINT64 TimerTicks64; + UINT64 SystemCounterVal; // Calculate counter ticks that represent requested delay: // = MicroSeconds x TICKS_PER_MICRO_SEC @@ -141,7 +138,6 @@ MicroSecondDelay ( return MicroSeconds; } - /** Stalls the CPU for at least the given number of nanoseconds. @@ -158,13 +154,13 @@ MicroSecondDelay ( UINTN EFIAPI NanoSecondDelay ( - IN UINTN NanoSeconds + IN UINTN NanoSeconds ) { UINTN MicroSeconds; // Round up to 1us Tick Number - MicroSeconds = NanoSeconds / 1000; + MicroSeconds = NanoSeconds / 1000; MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1; MicroSecondDelay (MicroSeconds); @@ -219,13 +215,13 @@ GetPerformanceCounter ( UINT64 EFIAPI GetPerformanceCounterProperties ( - OUT UINT64 *StartValue OPTIONAL, - OUT UINT64 *EndValue OPTIONAL + OUT UINT64 *StartValue OPTIONAL, + OUT UINT64 *EndValue OPTIONAL ) { if (StartValue != NULL) { // Timer starts at 0 - *StartValue = (UINT64)0ULL ; + *StartValue = (UINT64)0ULL; } if (EndValue != NULL) { @@ -250,7 +246,7 @@ GetPerformanceCounterProperties ( UINT64 EFIAPI GetTimeInNanoSecond ( - IN UINT64 Ticks + IN UINT64 Ticks ) { UINT64 NanoSeconds; @@ -267,7 +263,8 @@ GetTimeInNanoSecond ( DivU64x32Remainder ( Ticks, TimerFreq, - &Remainder), + &Remainder + ), 1000000000U ); @@ -277,8 +274,9 @@ GetTimeInNanoSecond ( // NanoSeconds += DivU64x32 ( MULT_U64_X_N ( - (UINT64) Remainder, - 1000000000U), + (UINT64)Remainder, + 1000000000U + ), TimerFreq ); diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index db9290f275..bad5d244cb 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -20,20 +20,21 @@ CacheRangeOperation ( IN UINTN LineLength ) { - UINTN ArmCacheLineAlignmentMask; + UINTN ArmCacheLineAlignmentMask; // Align address (rounding down) - UINTN AlignedAddress; - UINTN EndAddress; + UINTN AlignedAddress; + UINTN EndAddress; ArmCacheLineAlignmentMask = LineLength - 1; - AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); - EndAddress = (UINTN)Start + Length; + AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask); + EndAddress = (UINTN)Start + Length; // Perform the line operation on an address in each cache line while (AlignedAddress < EndAddress) { - LineOperation(AlignedAddress); + LineOperation (AlignedAddress); AlignedAddress += LineLength; } + ArmDataSynchronizationBarrier (); } @@ -58,15 +59,22 @@ InvalidateDataCache ( VOID * EFIAPI InvalidateInstructionCacheRange ( - IN VOID *Address, - IN UINTN Length + IN VOID *Address, + IN UINTN Length ) { - CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA, - ArmDataCacheLineLength ()); - CacheRangeOperation (Address, Length, + CacheRangeOperation ( + Address, + Length, + ArmCleanDataCacheEntryToPoUByMVA, + ArmDataCacheLineLength () + ); + CacheRangeOperation ( + Address, + Length, ArmInvalidateInstructionCacheEntryToPoUByMVA, - ArmInstructionCacheLineLength ()); + ArmInstructionCacheLineLength () + ); ArmInstructionSynchronizationBarrier (); @@ -85,12 +93,16 @@ WriteBackInvalidateDataCache ( VOID * EFIAPI WriteBackInvalidateDataCacheRange ( - IN VOID *Address, - IN UINTN Length + IN VOID *Address, + IN UINTN Length ) { - CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA, - ArmDataCacheLineLength ()); + CacheRangeOperation ( + Address, + Length, + ArmCleanInvalidateDataCacheEntryByMVA, + ArmDataCacheLineLength () + ); return Address; } @@ -106,23 +118,31 @@ WriteBackDataCache ( VOID * EFIAPI WriteBackDataCacheRange ( - IN VOID *Address, - IN UINTN Length + IN VOID *Address, + IN UINTN Length ) { - CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA, - ArmDataCacheLineLength ()); + CacheRangeOperation ( + Address, + Length, + ArmCleanDataCacheEntryByMVA, + ArmDataCacheLineLength () + ); return Address; } VOID * EFIAPI InvalidateDataCacheRange ( - IN VOID *Address, - IN UINTN Length + IN VOID *Address, + IN UINTN Length ) { - CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA, - ArmDataCacheLineLength ()); + CacheRangeOperation ( + Address, + Length, + ArmInvalidateDataCacheEntryByMVA, + ArmDataCacheLineLength () + ); return Address; } diff --git a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c index 353f41bfba..ac334f0ebf 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c @@ -26,12 +26,12 @@ **/ VOID DisassembleInstruction ( - IN UINT8 **OpCodePtr, - IN BOOLEAN Thumb, - IN BOOLEAN Extended, - IN OUT UINT32 *ItBlock, - OUT CHAR8 *Buf, - OUT UINTN Size + IN UINT8 **OpCodePtr, + IN BOOLEAN Thumb, + IN BOOLEAN Extended, + IN OUT UINT32 *ItBlock, + OUT CHAR8 *Buf, + OUT UINTN Size ) { // Not yet supported for AArch64. diff --git a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c index 03a9f1fbe2..0e09062957 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -13,7 +13,7 @@ #include #include -CHAR8 *gCondition[] = { +CHAR8 *gCondition[] = { "EQ", "NE", "CS", @@ -34,7 +34,7 @@ CHAR8 *gCondition[] = { #define COND(_a) gCondition[((_a) >> 28)] -CHAR8 *gReg[] = { +CHAR8 *gReg[] = { "r0", "r1", "r2", @@ -53,37 +53,36 @@ CHAR8 *gReg[] = { "pc" }; -CHAR8 *gLdmAdr[] = { +CHAR8 *gLdmAdr[] = { "DA", "IA", "DB", "IB" }; -CHAR8 *gLdmStack[] = { +CHAR8 *gLdmStack[] = { "FA", "FD", "EA", "ED" }; -#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)]) +#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)]) +#define SIGN(_U) ((_U) ? "" : "-") +#define WRITE(_Write) ((_Write) ? "!" : "") +#define BYTE(_B) ((_B) ? "B":"") +#define USER(_B) ((_B) ? "^" : "") -#define SIGN(_U) ((_U) ? "" : "-") -#define WRITE(_Write) ((_Write) ? "!" : "") -#define BYTE(_B) ((_B) ? "B":"") -#define USER(_B) ((_B) ? "^" : "") - -CHAR8 mMregListStr[4*15 + 1]; +CHAR8 mMregListStr[4*15 + 1]; CHAR8 * MRegList ( UINT32 OpCode ) { - UINTN Index, Start, End; - BOOLEAN First; + UINTN Index, Start, End; + BOOLEAN First; mMregListStr[0] = '\0'; AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{"); @@ -110,9 +109,11 @@ MRegList ( } } } + if (First) { AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR"); } + AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}"); // BugBug: Make caller pass in buffer it is cleaner @@ -129,14 +130,13 @@ FieldMask ( UINT32 RotateRight ( - IN UINT32 Op, - IN UINT32 Shift + IN UINT32 Op, + IN UINT32 Shift ) { return (Op >> Shift) | (Op << (32 - Shift)); } - /** Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to point to next instruction. @@ -152,39 +152,38 @@ RotateRight ( **/ VOID DisassembleArmInstruction ( - IN UINT32 **OpCodePtr, - OUT CHAR8 *Buf, - OUT UINTN Size, - IN BOOLEAN Extended + IN UINT32 **OpCodePtr, + OUT CHAR8 *Buf, + OUT UINTN Size, + IN BOOLEAN Extended ) { - UINT32 OpCode; - CHAR8 *Type; - CHAR8 *Root; - BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half; - UINT32 Rn, Rd, Rm; - UINT32 IMod, Offset8, Offset12; - UINT32 Index; - UINT32 ShiftImm, Shift; + UINT32 OpCode; + CHAR8 *Type; + CHAR8 *Root; + BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half; + UINT32 Rn, Rd, Rm; + UINT32 IMod, Offset8, Offset12; + UINT32 Index; + UINT32 ShiftImm, Shift; OpCode = **OpCodePtr; - Imm = (OpCode & BIT25) == BIT25; // I - Pre = (OpCode & BIT24) == BIT24; // P - Up = (OpCode & BIT23) == BIT23; // U + Imm = (OpCode & BIT25) == BIT25; // I + Pre = (OpCode & BIT24) == BIT24; // P + Up = (OpCode & BIT23) == BIT23; // U WriteBack = (OpCode & BIT22) == BIT22; // B, also called S - Write = (OpCode & BIT21) == BIT21; // W - Load = (OpCode & BIT20) == BIT20; // L - Sign = (OpCode & BIT6) == BIT6; // S - Half = (OpCode & BIT5) == BIT5; // H - Rn = (OpCode >> 16) & 0xf; - Rd = (OpCode >> 12) & 0xf; - Rm = (OpCode & 0xf); - + Write = (OpCode & BIT21) == BIT21; // W + Load = (OpCode & BIT20) == BIT20; // L + Sign = (OpCode & BIT6) == BIT6; // S + Half = (OpCode & BIT5) == BIT5; // H + Rn = (OpCode >> 16) & 0xf; + Rd = (OpCode >> 12) & 0xf; + Rm = (OpCode & 0xf); if (Extended) { Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode); - Buf += Index; + Buf += Index; Size -= Index; } @@ -194,9 +193,10 @@ DisassembleArmInstruction ( // A4.1.27 LDREX{} , [] AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]); } else { - // A4.1.103 STREX{} , , [] + // A4.1.103 STREX{} , , [] AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]); } + return; } @@ -206,23 +206,25 @@ DisassembleArmInstruction ( // A4.1.20 LDM{} {!}, // A4.1.21 LDM{} , ^ // A4.1.22 LDM{} {!}, ^ - AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); + AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); } else { // A4.1.97 STM{} {!}, // A4.1.98 STM{} , ^ - AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); + AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack)); } + return; } // LDR/STR Address Mode 2 - if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) { + if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) { Offset12 = OpCode & 0xfff; - if ((OpCode & 0xfd70f000 ) == 0xf550f000) { + if ((OpCode & 0xfd70f000) == 0xf550f000) { Index = AsciiSPrint (Buf, Size, "PLD"); } else { - Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]); + Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]); } + if (Pre) { if (!Imm) { // A5.2.2 [, #+/-] @@ -236,7 +238,7 @@ DisassembleArmInstruction ( // A5.2.4 [, +/-, LSL #] // A5.2.7 [, +/-, LSL #]! ShiftImm = (OpCode >> 7) & 0x1f; - Shift = (OpCode >> 5) & 0x3; + Shift = (OpCode >> 5) & 0x3; if (Shift == 0x0) { Type = "LSL"; } else if (Shift == 0x1) { @@ -255,7 +257,8 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write)); } - } else { // !Pre + } else { + // !Pre if (!Imm) { // A5.2.8 [], #+/- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12); @@ -265,7 +268,7 @@ DisassembleArmInstruction ( } else { // A5.2.10 [], +/-, LSL # ShiftImm = (OpCode >> 7) & 0x1f; - Shift = (OpCode >> 5) & 0x3; + Shift = (OpCode >> 5) & 0x3; if (Shift == 0x0) { Type = "LSL"; @@ -287,6 +290,7 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm); } } + return; } @@ -313,30 +317,31 @@ DisassembleArmInstruction ( Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]); - Sign = (OpCode & BIT6) == BIT6; - Half = (OpCode & BIT5) == BIT5; + Sign = (OpCode & BIT6) == BIT6; + Half = (OpCode & BIT5) == BIT5; Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff; if (Pre & !Write) { // Immediate offset/index if (WriteBack) { // A5.3.2 [, #+/-] // A5.3.4 [, #+/-]! - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write)); } else { // A5.3.3 [, +/-] // A5.3.5 [, +/-]! - AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write)); + AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write)); } } else { // Register offset/index if (WriteBack) { // A5.3.6 [], #+/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8); } else { // A5.3.7 [], +/- - AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]); + AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]); } } + return; } @@ -370,16 +375,21 @@ DisassembleArmInstruction ( if (((OpCode >> 6) & 0x7) == 0) { AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f)); } else { - IMod = (OpCode >> 18) & 0x3; - Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", - (IMod == 3) ? "ID":"IE", - ((OpCode & BIT8) != 0) ? "A":"", - ((OpCode & BIT7) != 0) ? "I":"", - ((OpCode & BIT6) != 0) ? "F":""); + IMod = (OpCode >> 18) & 0x3; + Index = AsciiSPrint ( + Buf, + Size, + "CPS%a %a%a%a", + (IMod == 3) ? "ID" : "IE", + ((OpCode & BIT8) != 0) ? "A" : "", + ((OpCode & BIT7) != 0) ? "I" : "", + ((OpCode & BIT6) != 0) ? "F" : "" + ); if ((OpCode & BIT17) != 0) { AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f); } } + return; } @@ -395,16 +405,16 @@ DisassembleArmInstruction ( return; } - if ((OpCode & 0x0db00000) == 0x01200000) { // A4.1.38 MSR{} CPSR_, # MSR{} CPSR_, if (Imm) { // MSR{} CPSR_, # - AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2)); + AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2)); } else { // MSR{} CPSR_, AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]); } + return; } @@ -417,35 +427,34 @@ DisassembleArmInstruction ( if ((OpCode & 0x0e000000) == 0x0c000000) { // A4.1.19 LDC and A4.1.96 SDC if ((OpCode & 0xf0000000) == 0xf0000000) { - Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd); + Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd); } else { - Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); + Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd); } if (!Pre) { if (!Write) { // A5.5.5.5 [],