From f0247796cbc23568121463683fefe7a211d439e3 Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Sat, 1 Mar 2014 10:58:46 +0000 Subject: ArmPkg/ArmLib: ArmReadVBar implementation missing in AArch64 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15274 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'ArmPkg/Library') diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index 66c310bb31..211457bd75 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -45,6 +45,7 @@ GCC_ASM_EXPORT (ArmDataMemoryBarrier) GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) GCC_ASM_EXPORT (ArmWriteVBar) +GCC_ASM_EXPORT (ArmReadVBar) GCC_ASM_EXPORT (ArmVFPImplemented) GCC_ASM_EXPORT (ArmEnableVFP) GCC_ASM_EXPORT (ArmCallWFI) @@ -411,6 +412,16 @@ ASM_PFX(ArmWriteVBar): 4: isb ret +ASM_PFX(ArmReadVBar): + EL1_OR_EL2_OR_EL3(x1) +1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register + ret +2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register + ret +3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register + ret + + ASM_PFX(ArmEnableVFP): // Check whether floating-point is implemented in the processor. mov x1, x30 // Save LR -- cgit v1.2.3