From 28f8d28faabf50a82ef8d137308592c64ea9e2b6 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 7 Jul 2016 19:18:39 +0200 Subject: ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributor Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) (limited to 'ArmPkg') diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index 248e896c4b..73795ed4e5 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -19,6 +19,19 @@ #include #include +/** + * + * Return whether the Source interrupt index refers to a shared interrupt (SPI) + */ +STATIC +BOOLEAN +SourceIsSpi ( + IN UINTN Source + ) +{ + return Source >= 32 && Source < 1020; +} + /** * Return the base address of the GIC redistributor for the current CPU * @@ -183,7 +196,9 @@ ArmGicEnableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { // Write set-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift); } else { @@ -216,7 +231,9 @@ ArmGicDisableInterrupt ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { // Write clear-enable register MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift); } else { @@ -249,7 +266,9 @@ ArmGicIsInterruptEnabled ( RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); - if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) { + if ((Revision == ARM_GIC_ARCH_REVISION_2) || + FeaturePcdGet (PcdArmGicV3WithV2Legacy) || + SourceIsSpi (Source)) { Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0); } else { GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision); -- cgit v1.2.3