From 0787bc6184631f20f8bf3b4abd61630a4a9bc672 Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Thu, 22 Sep 2011 23:01:13 +0000 Subject: ArmPlatformPkg: Introduce Primary core macros On MpCore system, the primary core can now be any core of the system. To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask' and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'. These PCDs by default use the ClusterId and CoreId to identify the core. And the primary core is defined as the ClusetrId=0 and CoreId=0. The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId), GET_CORE_POS(MpId), PRIMARY_CORE_ID. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Sec/Sec.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'ArmPlatformPkg/Sec/Sec.c') diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c index 5610168df1..6f4738fd4d 100644 --- a/ArmPlatformPkg/Sec/Sec.c +++ b/ArmPlatformPkg/Sec/Sec.c @@ -26,8 +26,6 @@ #include #include -#define ARM_PRIMARY_CORE 0 - #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); extern VOID *monitor_vector_table; @@ -66,7 +64,7 @@ copy_cpsr_into_spsr ( VOID CEntryPoint ( - IN UINTN CoreId + IN UINTN MpId ) { CHAR8 Buffer[100]; @@ -74,7 +72,7 @@ CEntryPoint ( UINTN JumpAddress; // Primary CPU clears out the SCU tag RAMs, secondaries wait - if (CoreId == ARM_PRIMARY_CORE) { + if (IS_PRIMARY_CORE(MpId)) { if (FixedPcdGet32(PcdMPCoreSupport)) { ArmInvalidScu(); } @@ -118,7 +116,7 @@ CEntryPoint ( ArmEnableVFP(); } - if (CoreId == ARM_PRIMARY_CORE) { + if (IS_PRIMARY_CORE(MpId)) { // Initialize peripherals that must be done at the early stage // Example: Some L2x0 controllers must be initialized in Secure World ArmPlatformSecInitialize (); @@ -138,18 +136,18 @@ CEntryPoint ( if (ArmPlatformTrustzoneSupported()) { if (FixedPcdGet32(PcdMPCoreSupport)) { // Setup SMP in Non Secure world - ArmSetupSmpNonSecure (CoreId); + ArmSetupSmpNonSecure (GET_CORE_ID(MpId)); } // Enter Monitor Mode - enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId))); + enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId)))); //Write the monitor mode vector table address ArmWriteVMBar((UINT32) &monitor_vector_table); //-------------------- Monitor Mode --------------------- // Setup the Trustzone Chipsets - if (CoreId == ARM_PRIMARY_CORE) { + if (IS_PRIMARY_CORE(MpId)) { ArmPlatformTrustzoneInit(); // Wake up the secondary cores by sending a interrupt to everyone else @@ -193,12 +191,12 @@ CEntryPoint ( // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW) ArmWriteScr(SCR_NS | SCR_FW | SCR_AW); } else { - if (CoreId == ARM_PRIMARY_CORE) { + if (IS_PRIMARY_CORE(MpId)) { SerialPrint ("Trust Zone Configuration is disabled\n\r"); } // Trustzone is not enabled, just enable the Distributor and CPU interface - if (CoreId == ARM_PRIMARY_CORE) { + if (IS_PRIMARY_CORE(MpId)) { ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); } ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); @@ -210,7 +208,7 @@ CEntryPoint ( } JumpAddress = PcdGet32 (PcdNormalFvBaseAddress); - ArmPlatformSecExtraAction (CoreId, &JumpAddress); + ArmPlatformSecExtraAction (MpId, &JumpAddress); return_from_exception (JumpAddress); //-------------------- Non Secure Mode --------------------- -- cgit v1.2.3