From f527942e6bdd9f198db90f2de99a0482e9be5b1b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Antoine=20C=C5=93ur?= <coeur@gmx.fr>
Date: Tue, 9 Jul 2019 17:10:11 +0800
Subject: FmpDevicePkg: Fix various typos
MIME-Version: 1.0
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Fix one typo in FmpDevicePkg.

Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm      | 4 ++--
 IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm     | 4 ++--
 IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 ++--
 IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm             | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'IntelFsp2Pkg/FspSecCore/Ia32')

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index f14c18c7b9..e7261b41cd 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -194,9 +194,9 @@ StackSetupDone:
 
   ;
   ; Pass BFV into the PEI Core
-  ; It uses relative address to calucate the actual boot FV base
+  ; It uses relative address to calculate the actual boot FV base
   ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
-  ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
+  ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
   ; they are different. The code below can handle both cases.
   ;
   call    ASM_PFX(AsmGetFspBaseAddress)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
index e1886ea11b..ebc91c41e4 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Abstract:
@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits):
     fldcw    [ASM_PFX(mFpuControlWord)]
 
     ;
-    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+    ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
     ; whether the processor supports SSE instruction.
     ;
     mov     eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
index b257deb76c..4c321cbece 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Abstract:
@@ -150,7 +150,7 @@ NextAddress:
             fldcw   [FpuControlWord]
 
             ;
-            ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+            ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
             ; whether the processor supports SSE instruction.
             ;
             mov     eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
index d72212ed45..5a7e27c240 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ; Abstract:
@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack):
     mov   esp, eax                     ; From now, esp is pointed to permanent memory
 
     ;
-    ; Fixup the ebp point to permenent memory
+    ; Fixup the ebp point to permanent memory
     ;
     mov   eax, ebp
     sub   eax, ebx
-- 
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