From 7e6a7a637839c3664cd39e3650116571235d0ea5 Mon Sep 17 00:00:00 2001 From: klu2 Date: Tue, 2 Dec 2008 05:52:37 +0000 Subject: Fix doxygen comment for structure definitions. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6800 6f19259b-4bc3-4df7-8a09-765794883524 --- MdePkg/Include/IndustryStandard/Pal.h | 2118 +++++++++++++++------------------ 1 file changed, 928 insertions(+), 1190 deletions(-) (limited to 'MdePkg/Include/IndustryStandard/Pal.h') diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/IndustryStandard/Pal.h index fdeea7fe31..b726201f9c 100644 --- a/MdePkg/Include/IndustryStandard/Pal.h +++ b/MdePkg/Include/IndustryStandard/Pal.h @@ -17,18 +17,18 @@ #define PAL_SUCCESS 0x0 -// -// CacheType of PAL_CACHE_FLUSH. -// +/// +/// CacheType of PAL_CACHE_FLUSH. +/// #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1 #define PAL_CACHE_FLUSH_DATA_ALL 2 #define PAL_CACHE_FLUSH_ALL 3 #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4 -// -// Bitmask of Opearation of PAL_CACHE_FLUSH. -// +/// +/// Bitmask of Opearation of PAL_CACHE_FLUSH. +/// #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0 #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0 #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1 @@ -72,35 +72,35 @@ #define PAL_CACHE_FLUSH 1 -// -// Attributes of PAL_CACHE_CONFIG_INFO1 -// +/// +/// Attributes of PAL_CACHE_CONFIG_INFO1 +/// #define PAL_CACHE_ATTR_WT 0 #define PAL_CACHE_ATTR_WB 1 -// -// PAL_CACHE_CONFIG_INFO1.StoreHint -// +/// +/// PAL_CACHE_CONFIG_INFO1.StoreHint +/// #define PAL_CACHE_STORE_TEMPORAL 0 #define PAL_CACHE_STORE_NONE_TEMPORAL 3 -// -// PAL_CACHE_CONFIG_INFO1.StoreHint -// +/// +/// PAL_CACHE_CONFIG_INFO1.StoreHint +/// #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0 #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3 -// -// PAL_CACHE_CONFIG_INFO1.StoreHint -// +/// +/// PAL_CACHE_CONFIG_INFO1.StoreHint +/// #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1 #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3 -// -// Detail the characteristics of a given processor controlled -// cache in the cache hierarchy. -// +/// +/// Detail the characteristics of a given processor controlled +/// cache in the cache hierarchy. +/// typedef struct { UINT64 IsUnified : 1; UINT64 Attributes : 2; @@ -112,10 +112,10 @@ typedef struct { UINT64 LoadHint:8; } PAL_CACHE_INFO_RETURN1; -// -// Detail the characteristics of a given processor controlled -// cache in the cache hierarchy. -// +/// +/// Detail the characteristics of a given processor controlled +/// cache in the cache hierarchy. +/// typedef struct { UINT64 CacheSize:32; UINT64 AliasBoundary:8; @@ -162,21 +162,21 @@ typedef struct { -// -// Level of PAL_CACHE_INIT. -// +/// +/// Level of PAL_CACHE_INIT. +/// #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL -// -// CacheType -// +/// +/// CacheType +/// #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1 #define PAL_CACHE_INIT_TYPE_DATA 0x2 #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3 -// -// Restrict of PAL_CACHE_INIT. -// +/// +/// Restrict of PAL_CACHE_INIT. +/// #define PAL_CACHE_INIT_NO_RESTRICT 0 #define PAL_CACHE_INIT_RESTRICTED 1 @@ -218,9 +218,9 @@ typedef struct { #define PAL_CACHE_INIT 3 -// -// PAL_CACHE_PROTECTION.Method. -// +/// +/// PAL_CACHE_PROTECTION.Method. +/// #define PAL_CACHE_PROTECTION_NONE_PROTECT 0 #define PAL_CACHE_PROTECTION_ODD_PROTECT 1 #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2 @@ -228,17 +228,17 @@ typedef struct { -// -// PAL_CACHE_PROTECTION.TagOrData. -// +/// +/// PAL_CACHE_PROTECTION.TagOrData. +/// #define PAL_CACHE_PROTECTION_PROTECT_DATA 0 #define PAL_CACHE_PROTECTION_PROTECT_TAG 1 #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2 #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3 -// -// 32-bit protection information structures. -// +/// +/// 32-bit protection information structures. +/// typedef struct { UINT32 DataBits:8; UINT32 TagProtLsb:6; @@ -286,38 +286,26 @@ typedef struct { **/ #define PAL_CACHE_PROT_INFO 38 -/** - - @param ThreadId The thread identifier of the logical - processor for which information is being - returned. This value will be unique on a per - core basis. - - @param CoreId The core identifier of the logical processor - for which information is being returned. - This value will be unique on a per physical - processor package basis. - -**/ typedef struct { - UINT64 ThreadId : 16; + UINT64 ThreadId : 16; /// The thread identifier of the logical + /// processor for which information is being + /// returned. This value will be unique on a per core basis. UINT64 Reserved1: 16; - UINT64 CoreId: 16; + UINT64 CoreId: 16; /// The core identifier of the logical processor + /// for which information is being returned. + /// This value will be unique on a per physical + /// processor package basis. UINT64 Reserved2: 16; } PAL_PCOC_N_CACHE_INFO1; -/** - - @param LogicalAddress Logical address: geographical address - of the logical processor for which - information is being returned. This is - the same value that is returned by the - PAL_FIXED_ADDR procedure when it is - called on the logical processor. -**/ typedef struct { - UINT64 LogicalAddress : 16; + UINT64 LogicalAddress : 16; /// Logical address: geographical address + /// of the logical processor for which + /// information is being returned. This is + /// the same value that is returned by the + /// PAL_FIXED_ADDR procedure when it is + /// called on the logical processor. UINT64 Reserved1: 16; UINT64 Reserved2: 32; } PAL_PCOC_N_CACHE_INFO2; @@ -492,45 +480,27 @@ typedef struct { **/ #define PAL_PTCE_INFO 6 - - -/** - - @param NumberSets Unsigned 8-bit integer denoting the number - of hash sets for the specified level - (1=fully associative) - - @param NumberWays Unsigned 8-bit integer denoting the - associativity of the specified level - (1=direct). - - @param NumberEntries Unsigned 16-bit integer denoting the - number of entries in the specified TC. - - - @param PageSizeIsOptimized Flag denoting whether the - specified level is optimized for - the region's preferred page size - (1=optimized) tc_pages indicates - which page sizes are usable by - this translation cache. - - @param TcIsUnified Flag denoting whether the specified TC is - unified (1=unified). - - @param EntriesReduction Flag denoting whether installed - translation registers will reduce - the number of entries within the - specified TC. - -**/ typedef struct { - UINT64 NumberSets:8; - UINT64 NumberWays:8; - UINT64 NumberEntries:16; - UINT64 PageSizeIsOptimized:1; - UINT64 TcIsUnified:1; - UINT64 EntriesReduction:1; + UINT64 NumberSets:8; /// Unsigned 8-bit integer denoting the number + /// of hash sets for the specified level + /// (1=fully associative) + UINT64 NumberWays:8; /// Unsigned 8-bit integer denoting the + /// associativity of the specified level + /// (1=direct). + UINT64 NumberEntries:16; /// Unsigned 16-bit integer denoting the + /// number of entries in the specified TC. + UINT64 PageSizeIsOptimized:1; /// Flag denoting whether the + /// specified level is optimized for + /// the region's preferred page size + /// (1=optimized) tc_pages indicates + /// which page sizes are usable by + /// this translation cache. + UINT64 TcIsUnified:1; /// Flag denoting whether the specified TC is + /// unified (1=unified). + UINT64 EntriesReduction:1; /// Flag denoting whether installed + /// translation registers will reduce + /// the number of entries within the + /// specified TC. } PAL_TC_INFO; /** @@ -593,79 +563,49 @@ typedef struct { **/ #define PAL_VM_PAGE_SIZE 34 -/** - - @param WalkerPresent 1-bit flag indicating whether a hardware - TLB walker is implemented (1 = walker - present). - - @param WidthOfPhysicalAddress Unsigned 7-bit integer - denoting the number of bits of - physical address implemented. - - @param WidthOfKey Unsigned 8-bit integer denoting the number - of bits mplemented in the PKR.key field. - - @param MaxPkrIndex Unsigned 8-bit integer denoting the - maximum PKR index (number of PKRs-1). - - @param HashTagId Unsigned 8-bit integer which uniquely - identifies the processor hash and tag - algorithm. - - @param MaxDtrIndex Unsigned 8 bit integer denoting the - maximum data translation register index - (number of dtr entries - 1). - - @param MaxItrIndex Unsigned 8 bit integer denoting the - maximum instruction translation register - index (number of itr entries - 1). - - @param NumberOfUniqueTc Unsigned 8-bit integer denoting the - number of unique TCs implemented. - This is a maximum of - 2*num_tc_levels. - - @param NumberOfTcLevels Unsigned 8-bit integer denoting the - number of TC levels. - -**/ typedef struct { - UINT64 WalkerPresent:1; - UINT64 WidthOfPhysicalAddress: 7; - UINT64 WidthOfKey:8; - UINT64 MaxPkrIndex:8; - UINT64 HashTagId:8; - UINT64 MaxDtrIndex:8; - UINT64 MaxItrIndex:8; - UINT64 NumberOfUniqueTc:8; - UINT64 NumberOfTcLevels:8; + UINT64 WalkerPresent:1; /// 1-bit flag indicating whether a hardware + /// TLB walker is implemented (1 = walker + /// present). + UINT64 WidthOfPhysicalAddress: 7; /// Unsigned 7-bit integer + /// denoting the number of bits of + /// physical address implemented. + UINT64 WidthOfKey:8; /// Unsigned 8-bit integer denoting the number + /// of bits mplemented in the PKR.key field. + UINT64 MaxPkrIndex:8; /// Unsigned 8-bit integer denoting the + /// maximum PKR index (number of PKRs-1). + UINT64 HashTagId:8; /// Unsigned 8-bit integer which uniquely + /// identifies the processor hash and tag + /// algorithm. + UINT64 MaxDtrIndex:8; /// Unsigned 8 bit integer denoting the + /// maximum data translation register index + /// (number of dtr entries - 1). + UINT64 MaxItrIndex:8; /// Unsigned 8 bit integer denoting the + /// maximum instruction translation register + /// index (number of itr entries - 1). + UINT64 NumberOfUniqueTc:8; /// Unsigned 8-bit integer denoting the + /// number of unique TCs implemented. + /// This is a maximum of + /// 2*num_tc_levels. + UINT64 NumberOfTcLevels:8; /// Unsigned 8-bit integer denoting the + /// number of TC levels. } PAL_VM_INFO1; -/** - - @param WidthOfVirtualAddress Unsigned 8-bit integer denoting - is the total number of virtual - address bits - 1. - - @param WidthOfRid Unsigned 8-bit integer denoting the number - of bits implemented in the RR.rid field. - - @param MaxPurgedTlbs Unsigned 16 bit integer denoting the - maximum number of concurrent outstanding - TLB purges allowed by the processor. A - value of 0 indicates one outstanding - purge allowed. A value of 216-1 - indicates no limit on outstanding - purges. All other values indicate the - actual number of concurrent outstanding - purges allowed. - -**/ typedef struct { - UINT64 WidthOfVirtualAddress:8; - UINT64 WidthOfRid:8; - UINT64 MaxPurgedTlbs:16; + UINT64 WidthOfVirtualAddress:8; /// Unsigned 8-bit integer denoting + /// is the total number of virtual + /// address bits - 1. + UINT64 WidthOfRid:8; /// Unsigned 8-bit integer denoting the number + /// of bits implemented in the RR.rid field. + UINT64 MaxPurgedTlbs:16; /// Unsigned 16 bit integer denoting the + /// maximum number of concurrent outstanding + /// TLB purges allowed by the processor. A + /// value of 0 indicates one outstanding + /// purge allowed. A value of 216-1 + /// indicates no limit on outstanding + /// purges. All other values indicate the + /// actual number of concurrent outstanding + /// purges allowed. UINT64 Reserved:32; } PAL_VM_INFO2; @@ -1044,72 +984,47 @@ typedef struct { **/ #define PAL_FREQ_RATIOS 14 -/** - - @param NumberOfLogicalProcessors Total number of logical - processors on this physical - processor package that are - enabled. - - @param ThreadsPerCore Number of threads per core. - - @param CoresPerProcessor Total number of cores on this - physical processor package. - - @param PhysicalProcessorPackageId Physical processor package - identifier which was - assigned at reset by the - platform or bus - controller. This value may - or may not be unique - across the entire platform - since it depends on the - platform vendor's policy. -**/ typedef struct { - UINT64 NumberOfLogicalProcessors:16; - UINT64 ThreadsPerCore:8; + UINT64 NumberOfLogicalProcessors:16; /// Total number of logical + /// processors on this physical + /// processor package that are + /// enabled. + UINT64 ThreadsPerCore:8; /// Number of threads per core. UINT64 Reserved1:8; - UINT64 CoresPerProcessor; + UINT64 CoresPerProcessor; /// Total number of cores on this + /// physical processor package. UINT64 Reserved2:8; - UINT64 PhysicalProcessorPackageId:8; + UINT64 PhysicalProcessorPackageId:8; /// Physical processor package + /// identifier which was + /// assigned at reset by the + /// platform or bus + /// controller. This value may + /// or may not be unique + /// across the entire platform + /// since it depends on the + /// platform vendor's policy. UINT64 Reserved3:8; } PAL_LOGICAL_PROCESSPR_OVERVIEW; -/** - - @param ThreadId The thread identifier of the logical - processor for which information is being - returned. This value will be unique on a per - core basis. - - @param CoreId The core identifier of the logical processor - for which information is being returned. - This value will be unique on a per physical - processor package basis. - -**/ typedef struct { - UINT64 ThreadId:16; + UINT64 ThreadId:16; /// The thread identifier of the logical + /// processor for which information is being + /// returned. This value will be unique on a per + /// core basis. UINT64 Reserved1:16; - UINT64 CoreId:16; + UINT64 CoreId:16; /// The core identifier of the logical processor + /// for which information is being returned. + /// This value will be unique on a per physical + /// processor package basis. UINT64 Reserved2:16; } PAL_LOGICAL_PROCESSORN_INFO1; - -/** - - @param LogicalAddress Geographical address of the logical - processor for which information is being - returned. This is the same value that is - returned by the PAL_FIXED_ADDR procedure - when it is called on the logical - processor. - - -**/ typedef struct { - UINT64 LogicalAddress:16; + UINT64 LogicalAddress:16; /// Geographical address of the logical + /// processor for which information is being + /// returned. This is the same value that is + /// returned by the PAL_FIXED_ADDR procedure + /// when it is called on the logical processor. UINT64 Reserved:48; } PAL_LOGICAL_PROCESSORN_INFO2; @@ -1147,32 +1062,18 @@ typedef struct { **/ #define PAL_LOGICAL_TO_PHYSICAL 42 - -/** - - @param NumberOfPmcPairs Unsigned 8-bit number defining the - number of generic PMC/PMD pairs. - - @param WidthOfCounter Unsigned 8-bit number in the range - 0:60 defining the number of - implemented counter bits. - - @param TypeOfCycleCounting Unsigned 8-bit number defining the - event type for counting processor - cycles. - - - @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit - number defining the - event type for retired - instruction bundles. - -**/ typedef struct { - UINT64 NumberOfPmcPairs:8; - UINT64 WidthOfCounter:8; - UINT64 TypeOfCycleCounting:8; - UINT64 TypeOfRetiredInstructionBundle:8; + UINT64 NumberOfPmcPairs:8; /// Unsigned 8-bit number defining the + /// number of generic PMC/PMD pairs. + UINT64 WidthOfCounter:8; /// Unsigned 8-bit number in the range + /// 0:60 defining the number of + /// implemented counter bits. + UINT64 TypeOfCycleCounting:8; /// Unsigned 8-bit number defining the + /// event type for counting processor cycles. + UINT64 TypeOfRetiredInstructionBundle:8; /// Retired Unsigned 8-bit + /// number defining the + /// event type for retired + /// instruction bundles. UINT64 Reserved:32; } PAL_PERFORMANCE_INFO; @@ -1231,349 +1132,316 @@ typedef struct { **/ #define PAL_PLATFORM_ADDR 16 - -/** - - @param EnableBerrPromotion Bit63. Enable BERR promotion. When - 1, the Bus Error (BERR) signal is - promoted to the Bus Initialization - (BINIT) signal, and the BINIT pin - is asserted on the occurrence of - each Bus Error. Setting this bit - has no effect if BINIT signalling - is disabled. (See - PAL_BUS_GET/SET_FEATURES) - - @param EnableMcaPromotion Bit62, Enable MCA promotion. When - 1, machine check aborts (MCAs) are - promoted to the Bus Error signal, - and the BERR pin is assert on each - occurrence of an MCA. Setting this - bit has no effect if BERR - signalling is disabled. (See - PAL_BUS_GET/SET_FEATURES) - - @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT - promotion. When 1, machine - check aborts (MCAs) are - promoted to the Bus - Initialization signal, and - the BINIT pin is assert on - each occurrence of an MCA. - Setting this bit has no - effect if BINIT signalling - is disabled. (See - PAL_BUS_GET/SET_FEATURES) - - @param EnableCmciPromotion Bit60, Enable CMCI promotion When - 1, Corrected Machine Check - Interrupts (CMCI) are promoted to - MCAs. They are also further - promoted to BERR if bit 39, Enable - MCA promotion, is also set and - they are promoted to BINIT if bit - 38, Enable MCA to BINIT promotion, - is also set. This bit has no - effect if MCA signalling is - disabled (see - PAL_BUS_GET/SET_FEATURES) - - @param DisableCache Bit59, Disable Cache. When 0, the - processor performs cast outs on - cacheable pages and issues and responds - to coherency requests normally. When 1, - the processor performs a memory access - for each reference regardless of cache - contents and issues no coherence - requests and responds as if the line - were not present. Cache contents cannot - be relied upon when the cache is - disabled. WARNING: Semaphore - instructions may not be atomic or may - cause Unsupported Data Reference faults - if caches are disabled. - - @param DisableCoherency Bit58, Disable Coherency. When 0, - the processor uses normal coherency - requests and responses. When 1, the - processor answers all requests as if - the line were not present. - - @param DisableDPM Bit57, Disable Dynamic Power Management - (DPM). When 0, the hardware may reduce - power consumption by removing the clock - input from idle functional units. When 1, - all functional units will receive clock - input, even when idle. - - @param DisableBinitWithTimeout Bit56, Disable a BINIT on - internal processor time-out. - When 0, the processor may - generate a BINIT on an - internal processor time-out. - When 1, the processor will not - generate a BINIT on an - internal processor time-out. - The event is silently ignored. - - - @param EnableEnvNotification Bit55, Enable external - notification when the processor - detects hardware errors caused - by environmental factors that - could cause loss of - deterministic behavior of the - processor. When 1, this bit will - enable external notification, - when 0 external notification is - not provided. The type of - external notification of these - errors is processor-dependent. A - loss of processor deterministic - behavior is considered to have - occurred if these - environmentally induced errors - cause the processor to deviate - from its normal execution and - eventually causes different - behavior which can be observed - at the processor bus pins. - Processor errors that do not - have this effects (i.e., - software induced machine checks) - may or may not be promoted - depending on the processor - implementation. - - @param EnableVmsw Bit54, Enable the use of the vmsw - instruction. When 0, the vmsw instruction - causes a Virtualization fault when - executed at the most privileged level. - When 1, this bit will enable normal - operation of the vmsw instruction. - - @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling - on data-poisoning event - detection. When 0, a CMCI - will be signaled on error - detection. When 1, an MCA - will be signaled on error - detection. If this feature - is not supported, then the - corresponding argument is - ignored when calling - PAL_PROC_SET_FEATURES. Note - that the functionality of - this bit is independent of - the setting in bit 60 - (Enable CMCI promotion), and - that the bit 60 setting does - not affect CMCI signaling - for data-poisoning related - events. Volume 2: Processor - Abstraction Layer 2:431 - PAL_PROC_GET_FEATURES - - @param DisablePState Bit52, Disable P-states. When 1, the PAL - P-state procedures (PAL_PSTATE_INFO, - PAL_SET_PSTATE, PAL_GET_PSTATE) will - return with a status of -1 - (Unimplemented procedure). - - @param DisableBranchPrediction Bit47, Disable Dynamic branch - prediction. When 0, the - processor may predict branch - targets and speculatively - execute, but may not commit - results. When 1, the processor - must wait until branch targets - are known to execute. - - @param DisableDynamicInsCachePrefetch Bit46, Disable - DynamicInstruction Cache - Prefetch. When 0, the - processor may prefetch - into the caches any - instruction which has - not been executed, but - whose execution is - likely. When 1, - instructions may not be - fetched until needed or - hinted for execution. - (Prefetch for a hinted - branch is allowed even - when dynamic instruction - cache prefetch is - disabled.) - - @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic - Data Cache Prefetch. - When 0, the processor - may prefetch into the - caches any data which - has not been accessed - by instruction - execution, but which - is likely to be - accessed. When 1, no - data may be fetched - until it is needed for - instruction execution - or is fetched by an - lfetch instruction. - - @param DisableSpontaneousDeferral Bit44, Disable Spontaneous - Deferral. When 1, the - processor may optionally - defer speculative loads - that do not encounter any - exception conditions, but - that trigger other - implementation-dependent - conditions (e.g., cache - miss). When 0, spontaneous - deferral is disabled. - - @param DisableDynamicPrediction Bit43, Disable Dynamic - Predicate Prediction. When - 0, the processor may predict - predicate results and - execute speculatively, but - may not commit results until - the actual predicates are - known. When 1, the processor - shall not execute predicated - instructions until the - actual predicates are known. - - @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented. - Denotes whether XR1 XR3 are - implemented for machine check - recovery. This feature may only be - interrogated by PAL_PROC_GET_FEATURES. - It may not be enabled or disabled by - PAL_PROC_SET_FEATURES. The - corresponding argument is ignored. - - @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS - implemented. Denotes whether XIP, XPSR, - and XFS are implemented for machine - check recovery. This feature may only be - interrogated by PAL_PROC_GET_FEATURES. - It may not be enabled or disabled by - PAL_PROC_SET_FEATURES. The corresponding - argument is ignored. - - @param NoVM Bit40, No Virtual Machine features implemented. - Denotes whether PSR.vm is implemented. This - feature may only be interrogated by - PAL_PROC_GET_FEATURES. It may not be enabled or - disabled by PAL_PROC_SET_FEATURES. The - corresponding argument is ignored. - - @param NoVariablePState Bit39, No Variable P-state - performance: A value of 1, indicates - that a processor implements - techniques to optimize performance - for the given P-state power budget - by dynamically varying the - frequency, such that maximum - performance is achieved for the - power budget. A value of 0, - indicates that P-states have no - frequency variation or very small - frequency variations for their given - power budget. This feature may only - be interrogated by - PAL_PROC_GET_FEATURES. it may not be - enabled or disabled by - PAL_PROC_SET_FEATURES. The - corresponding argument is ignored. - - - @param NoSimpleImpInUndefinedIns Bit38, No Simple - implementation of - unimplemented instruction - addresses. Denotes how an - unimplemented instruction - address is recorded in IIP - on an Unimplemented - Instruction Address trap or - fault. When 1, the full - unimplemented address is - recorded in IIP; when 0, the - address is sign extended - (virtual addresses) or zero - extended (physical - addresses). This feature may - only be interrogated by - PAL_PROC_GET_FEATURES. It - may not be enabled or - disabled by - PAL_PROC_SET_FEATURES. The - corresponding argument is - ignored. - - @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins - present. Denotes the absence of INIT, - PMI, LINT0 and LINT1 pins on the - processor. When 1, the pins are absent. - When 0, the pins are present. This - feature may only be interrogated by - PAL_PROC_GET_FEATURES. It may not be - enabled or disabled by - PAL_PROC_SET_FEATURES. The corresponding - argument is ignored. - - @param FaultInUndefinedIns Bit36, No Unimplemented - instruction address reported as - fault. Denotes how the processor - reports the detection of - unimplemented instruction - addresses. When 1, the processor - reports an Unimplemented - Instruction Address fault on the - unimplemented address; when 0, it - reports an Unimplemented - Instruction Address trap on the - previous instruction in program - order. This feature may only be - interrogated by - PAL_PROC_GET_FEATURES. It may not - be enabled or disabled by - PAL_PROC_SET_FEATURES. The - corresponding argument is - ignored. - -**/ typedef struct { UINT64 Reserved1:36; - UINT64 FaultInUndefinedIns:1; - UINT64 NoPresentPmi:1; - UINT64 NoSimpleImpInUndefinedIns:1; - UINT64 NoVariablePState:1; - UINT64 NoVM:1; - UINT64 NoXipXpsrXfs:1; - UINT64 NoXr1ThroughXr3:1; - UINT64 DisableDynamicPrediction:1; - UINT64 DisableSpontaneousDeferral:1; - UINT64 DisableDynamicDataCachePrefetch:1; - UINT64 DisableDynamicInsCachePrefetch:1; - UINT64 DisableBranchPrediction:1; + UINT64 FaultInUndefinedIns:1; /// Bit36, No Unimplemented + /// instruction address reported as + /// fault. Denotes how the processor + /// reports the detection of + /// unimplemented instruction + /// addresses. When 1, the processor + /// reports an Unimplemented + /// Instruction Address fault on the + /// unimplemented address; when 0, it + /// reports an Unimplemented + /// Instruction Address trap on the + /// previous instruction in program + /// order. This feature may only be + /// interrogated by + /// PAL_PROC_GET_FEATURES. It may not + /// be enabled or disabled by + /// PAL_PROC_SET_FEATURES. The + /// corresponding argument is ignored. + + UINT64 NoPresentPmi:1; /// Bit37, No INIT, PMI, and LINT pins + /// present. Denotes the absence of INIT, + /// PMI, LINT0 and LINT1 pins on the + /// processor. When 1, the pins are absent. + /// When 0, the pins are present. This + /// feature may only be interrogated by + /// PAL_PROC_GET_FEATURES. It may not be + /// enabled or disabled by + /// PAL_PROC_SET_FEATURES. The corresponding + /// argument is ignored. + + UINT64 NoSimpleImpInUndefinedIns:1; /// Bit38, No Simple + /// implementation of + /// unimplemented instruction + /// addresses. Denotes how an + /// unimplemented instruction + /// address is recorded in IIP + /// on an Unimplemented + /// Instruction Address trap or + /// fault. When 1, the full + /// unimplemented address is + /// recorded in IIP; when 0, the + /// address is sign extended + /// (virtual addresses) or zero + /// extended (physical + /// addresses). This feature may + /// only be interrogated by + /// PAL_PROC_GET_FEATURES. It + /// may not be enabled or + /// disabled by + /// PAL_PROC_SET_FEATURES. The + /// corresponding argument is + /// ignored. + + UINT64 NoVariablePState:1; /// Bit39, No Variable P-state + /// performance: A value of 1, indicates + /// that a processor implements + /// techniques to optimize performance + /// for the given P-state power budget + /// by dynamically varying the + /// frequency, such that maximum + /// performance is achieved for the + /// power budget. A value of 0, + /// indicates that P-states have no + /// frequency variation or very small + /// frequency variations for their given + /// power budget. This feature may only + /// be interrogated by + /// PAL_PROC_GET_FEATURES. it may not be + /// enabled or disabled by + /// PAL_PROC_SET_FEATURES. The + /// corresponding argument is ignored. + + UINT64 NoVM:1; /// Bit40, No Virtual Machine features implemented. + /// Denotes whether PSR.vm is implemented. This + /// feature may only be interrogated by + /// PAL_PROC_GET_FEATURES. It may not be enabled or + /// disabled by PAL_PROC_SET_FEATURES. The + /// corresponding argument is ignored. + + UINT64 NoXipXpsrXfs:1; /// Bit41, No XIP, XPSR, and XFS + /// implemented. Denotes whether XIP, XPSR, + /// and XFS are implemented for machine + /// check recovery. This feature may only be + /// interrogated by PAL_PROC_GET_FEATURES. + /// It may not be enabled or disabled by + /// PAL_PROC_SET_FEATURES. The corresponding + /// argument is ignored. + + UINT64 NoXr1ThroughXr3:1; /// Bit42, No XR1 through XR3 implemented. + /// Denotes whether XR1 XR3 are + /// implemented for machine check + /// recovery. This feature may only be + /// interrogated by PAL_PROC_GET_FEATURES. + /// It may not be enabled or disabled by + /// PAL_PROC_SET_FEATURES. The + /// corresponding argument is ignored. + + UINT64 DisableDynamicPrediction:1; /// Bit43, Disable Dynamic + /// Predicate Prediction. When + /// 0, the processor may predict + /// predicate results and + /// execute speculatively, but + /// may not commit results until + /// the actual predicates are + /// known. When 1, the processor + /// shall not execute predicated + /// instructions until the + /// actual predicates are known. + + UINT64 DisableSpontaneousDeferral:1; /// Bit44, Disable Spontaneous + /// Deferral. When 1, the + /// processor may optionally + /// defer speculative loads + /// that do not encounter any + /// exception conditions, but + /// that trigger other + /// implementation-dependent + /// conditions (e.g., cache + /// miss). When 0, spontaneous + /// deferral is disabled. + + UINT64 DisableDynamicDataCachePrefetch:1; /// Bit45, Disable Dynamic + /// Data Cache Prefetch. + /// When 0, the processor + /// may prefetch into the + /// caches any data which + /// has not been accessed + /// by instruction + /// execution, but which + /// is likely to be + /// accessed. When 1, no + /// data may be fetched + /// until it is needed for + /// instruction execution + /// or is fetched by an + /// lfetch instruction. + + UINT64 DisableDynamicInsCachePrefetch:1; /// Bit46, Disable + /// DynamicInstruction Cache + /// Prefetch. When 0, the + /// processor may prefetch + /// into the caches any + /// instruction which has + /// not been executed, but + /// whose execution is + /// likely. When 1, + /// instructions may not be + /// fetched until needed or + /// hinted for execution. + /// (Prefetch for a hinted + /// branch is allowed even + /// when dynamic instruction + /// cache prefetch is + /// disabled.) + + UINT64 DisableBranchPrediction:1; /// Bit47, Disable Dynamic branch + /// prediction. When 0, the + /// processor may predict branch + /// targets and speculatively + /// execute, but may not commit + /// results. When 1, the processor + /// must wait until branch targets + /// are known to execute. UINT64 Reserved2:4; - UINT64 DisablePState:1; - UINT64 EnableMcaOnDataPoisoning:1; - UINT64 EnableVmsw:1; - UINT64 EnableEnvNotification:1; - UINT64 DisableBinitWithTimeout:1; - UINT64 DisableDPM:1; - UINT64 DisableCoherency:1; - UINT64 DisableCache:1; - UINT64 EnableCmciPromotion:1; - UINT64 EnableMcaToBinitPromotion:1; - UINT64 EnableMcaPromotion:1; - UINT64 EnableBerrPromotion:1; + UINT64 DisablePState:1; /// Bit52, Disable P-states. When 1, the PAL + /// P-state procedures (PAL_PSTATE_INFO, + /// PAL_SET_PSTATE, PAL_GET_PSTATE) will + /// return with a status of -1 + /// (Unimplemented procedure). + + UINT64 EnableMcaOnDataPoisoning:1; /// Bit53, Enable MCA signaling + /// on data-poisoning event + /// detection. When 0, a CMCI + /// will be signaled on error + /// detection. When 1, an MCA + /// will be signaled on error + /// detection. If this feature + /// is not supported, then the + /// corresponding argument is + /// ignored when calling + /// PAL_PROC_SET_FEATURES. Note + /// that the functionality of + /// this bit is independent of + /// the setting in bit 60 + /// (Enable CMCI promotion), and + /// that the bit 60 setting does + /// not affect CMCI signaling + /// for data-poisoning related + /// events. Volume 2: Processor + /// Abstraction Layer 2:431 + /// PAL_PROC_GET_FEATURES + + UINT64 EnableVmsw:1; /// Bit54, Enable the use of the vmsw + /// instruction. When 0, the vmsw instruction + /// causes a Virtualization fault when + /// executed at the most privileged level. + /// When 1, this bit will enable normal + /// operation of the vmsw instruction. + + UINT64 EnableEnvNotification:1; /// Bit55, Enable external + /// notification when the processor + /// detects hardware errors caused + /// by environmental factors that + /// could cause loss of + /// deterministic behavior of the + /// processor. When 1, this bit will + /// enable external notification, + /// when 0 external notification is + /// not provided. The type of + /// external notification of these + /// errors is processor-dependent. A + /// loss of processor deterministic + /// behavior is considered to have + /// occurred if these + /// environmentally induced errors + /// cause the processor to deviate + /// from its normal execution and + /// eventually causes different + /// behavior which can be observed + /// at the processor bus pins. + /// Processor errors that do not + /// have this effects (i.e., + /// software induced machine checks) + /// may or may not be promoted + /// depending on the processor + /// implementation. + + UINT64 DisableBinitWithTimeout:1; /// Bit56, Disable a BINIT on + /// internal processor time-out. + /// When 0, the processor may + /// generate a BINIT on an + /// internal processor time-out. + /// When 1, the processor will not + /// generate a BINIT on an + /// internal processor time-out. + /// The event is silently ignored. + + UINT64 DisableDPM:1; /// Bit57, Disable Dynamic Power Management + /// (DPM). When 0, the hardware may reduce + /// power consumption by removing the clock + /// input from idle functional units. When 1, + /// all functional units will receive clock + /// input, even when idle. + + UINT64 DisableCoherency:1; /// Bit58, Disable Coherency. When 0, + /// the processor uses normal coherency + /// requests and responses. When 1, the + /// processor answers all requests as if + /// the line were not present. + + UINT64 DisableCache:1; /// Bit59, Disable Cache. When 0, the + /// processor performs cast outs on + /// cacheable pages and issues and responds + /// to coherency requests normally. When 1, + /// the processor performs a memory access + /// for each reference regardless of cache + /// contents and issues no coherence + /// requests and responds as if the line + /// were not present. Cache contents cannot + /// be relied upon when the cache is + /// disabled. WARNING: Semaphore + /// instructions may not be atomic or may + /// cause Unsupported Data Reference faults + /// if caches are disabled. + + UINT64 EnableCmciPromotion:1; /// Bit60, Enable CMCI promotion When + /// 1, Corrected Machine Check + /// Interrupts (CMCI) are promoted to + /// MCAs. They are also further + /// promoted to BERR if bit 39, Enable + /// MCA promotion, is also set and + /// they are promoted to BINIT if bit + /// 38, Enable MCA to BINIT promotion, + /// is also set. This bit has no + /// effect if MCA signalling is + /// disabled (see + /// PAL_BUS_GET/SET_FEATURES) + + UINT64 EnableMcaToBinitPromotion:1; /// Bit61, Enable MCA to BINIT + /// promotion. When 1, machine + /// check aborts (MCAs) are + /// promoted to the Bus + /// Initialization signal, and + /// the BINIT pin is assert on + /// each occurrence of an MCA. + /// Setting this bit has no + /// effect if BINIT signalling + /// is disabled. (See + /// PAL_BUS_GET/SET_FEATURES) + + UINT64 EnableMcaPromotion:1; /// Bit62, Enable MCA promotion. When + /// 1, machine check aborts (MCAs) are + /// promoted to the Bus Error signal, + /// and the BERR pin is assert on each + /// occurrence of an MCA. Setting this + /// bit has no effect if BERR + /// signalling is disabled. (See + /// PAL_BUS_GET/SET_FEATURES) + + UINT64 EnableBerrPromotion:1; /// Bit63. Enable BERR promotion. When + /// 1, the Bus Error (BERR) signal is + /// promoted to the Bus Initialization + /// (BINIT) signal, and the BINIT pin + /// is asserted on the occurrence of + /// each Bus Error. Setting this bit + /// has no effect if BINIT signalling + /// is disabled. (See + /// PAL_BUS_GET/SET_FEATURES) } PAL_PROCESSOR_FEATURES; /** @@ -1698,30 +1566,21 @@ typedef struct { **/ #define PAL_RSE_INFO 19 -/** - - @param VersionOfPalB Is a 16-bit binary coded decimal (BCD) - number that provides identification - information about the PAL_B firmware. - - @param PalVendor Is an unsigned 8-bit integer indicating the - vendor of the PAL code. - - @param VersionOfPalB Is a 16-bit binary coded decimal (BCD) - number that provides identification - information about the PAL_A firmware. In - the split PAL_A model, this return value - is the version number of the - processor-specific PAL_A. The generic - PAL_A version is not returned by this - procedure in the split PAL_A model. - -**/ typedef struct { - UINT64 VersionOfPalB:16; + UINT64 VersionOfPalB:16; /// Is a 16-bit binary coded decimal (BCD) + /// number that provides identification + /// information about the PAL_B firmware. UINT64 Reserved1:8; - UINT64 PalVendor:8; - UINT64 VersionOfPalA:16; + UINT64 PalVendor:8; /// Is an unsigned 8-bit integer indicating the + /// vendor of the PAL code. + UINT64 VersionOfPalA:16; /// Is a 16-bit binary coded decimal (BCD) + /// number that provides identification + /// information about the PAL_A firmware. In + /// the split PAL_A model, this return value + /// is the version number of the + /// processor-specific PAL_A. The generic + /// PAL_A version is not returned by this + /// procedure in the split PAL_A model. UINT64 Reserved2:16; } PAL_VERSION_INFO; @@ -1833,54 +1692,39 @@ typedef struct { #define PAL_PROCESSOR_STATE_PARAM 1 #define PAL_STRUCTURE_SPECIFIC_ERROR 2 -/** - - @param CoreId Bit3:0, Processor core ID (default is 0 for - processors with a single core) - - @param ThreadId Bit7:4, Logical thread ID (default is 0 for - processors that execute a single thread) - - @param InfoOfInsCache Bit11:8, Error information is - available for 1st, 2nd, 3rd, and 4th - level instruction caches. - - @param InfoOfDataCache Bit15:12, Error information is - available for 1st, 2nd, 3rd, and 4th - level data/unified caches. - - @param InfoOfInsTlb Bit19:16 Error information is available - for 1st, 2nd, 3rd, and 4th level - instruction TLB. - - @param InfoOfDataTlb Bit23:20, Error information is available - for 1st, 2nd, 3rd, and 4th level - data/unified TLB - - @param InfoOfProcessorBus Bit27:24 Error information is - available for the 1st, 2nd, 3rd, - and 4th level processor bus - hierarchy. - - @param InfoOfRegisterFile Bit31:28 Error information is - available on register file - structures. - - @param InfoOfMicroArch Bit47:32, Error information is - available on micro-architectural - structures. - -**/ typedef struct { - UINT64 CoreId:4; - UINT64 ThreadId:4; - UINT64 InfoOfInsCache:4; - UINT64 InfoOfDataCache:4; - UINT64 InfoOfInsTlb:4; - UINT64 InfoOfDataTlb:4; - UINT64 InfoOfProcessorBus:4; - UINT64 InfoOfRegisterFile:4; - UINT64 InfoOfMicroArch:4; + UINT64 CoreId:4; /// Bit3:0, Processor core ID (default is 0 for + /// processors with a single core) + + UINT64 ThreadId:4; /// Bit7:4, Logical thread ID (default is 0 for + /// processors that execute a single thread) + + UINT64 InfoOfInsCache:4; /// Bit11:8, Error information is + /// available for 1st, 2nd, 3rd, and 4th + /// level instruction caches. + + UINT64 InfoOfDataCache:4; /// Bit15:12, Error information is + /// available for 1st, 2nd, 3rd, and 4th + /// level data/unified caches. + + UINT64 InfoOfInsTlb:4; /// Bit19:16 Error information is available + /// for 1st, 2nd, 3rd, and 4th level + /// instruction TLB. + + UINT64 InfoOfDataTlb:4; /// Bit23:20, Error information is available + /// for 1st, 2nd, 3rd, and 4th level + /// data/unified TLB + + UINT64 InfoOfProcessorBus:4; /// Bit27:24 Error information is + /// available for the 1st, 2nd, 3rd, + /// and 4th level processor bus + /// hierarchy. + UINT64 InfoOfRegisterFile:4; /// Bit31:28 Error information is + /// available on register file + /// structures. + UINT64 InfoOfMicroArch:4; /// Bit47:32, Error information is + /// available on micro-architectural + /// structures. UINT64 Reserved:16; } PAL_MC_ERROR_INFO_LEVEL_INDEX; @@ -1893,237 +1737,179 @@ typedef struct { #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3 #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4 -/** - - @param Operation Bit3:0, Type of cache operation that caused - the machine check: 0 - unknown or internal - error 1 - load 2 - store 3 - instruction - fetch or instruction prefetch 4 - data - prefetch (both hardware and software) 5 - - snoop (coherency check) 6 - cast out - (explicit or implicit write-back of a cache - line) 7 - move in (cache line fill) - - @param FailedCacheLevel Bit5:4 Level of cache where the - error occurred. A value of 0 - indicates the first level of cache. - - @param FailedInDataPart Bit8, Failure located in the data - part of the cache line. - - @param FailedInTagPart Bit9, Failure located in the tag part - of the cache line. - - @param FailedInDataCache Bit10, Failure located in the data - cache - - @param FailedInInsCache Bit11, Failure located in the - instruction cache. - - - @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache - line is held shared. 2 - cache line is held - exclusive. 3 - cache line is modified. All other - values are reserved. - - @param MesiIsValid Bit15, The mesi field in the cache_check - parameter is valid. - - @param FailedWay Bit20:16, Failure located in the way of - the cache indicated by this value. - - @param WayIndexIsValid Bit21, The way and index field in the - cache_check parameter is valid. - - @param MultipleBitsError Bit23, A multiple-bit error was - detected, and data was poisoned for - the corresponding cache line during - castout. - - @param IndexOfCacheLineError Bit51:32, Index of the cache - line where the error occurred. - - @param InstructionSet Bit54, Instruction set. If this value - is set to zero, the instruction that - generated the machine check was an - Intel Itanium instruction. If this bit - is set to one, the instruction that - generated the machine check was IA-32 - instruction. - - @param InstructionSetIsValid Bit55, The is field in the - cache_check parameter is valid. - - @param PrivilegeLevel Bit57:56, Privilege level. The - privilege level of the instruction - bundle responsible for generating the - machine check. - - @param PrivilegeLevelIsValide Bit58, The pl field of the - cache_check parameter is - valid. - - @param McCorrected Bit59, Machine check corrected: This bit - is set to one to indicate that the machine - check has been corrected. - - @param TargetAddressIsValid Bit60, Target address is valid: - This bit is set to one to - indicate that a valid target - address has been logged. - - @param RequesterIdentifier Bit61, Requester identifier: This - bit is set to one to indicate that - a valid requester identifier has - been logged. - - @param ResponserIdentifier Bit62, Responder identifier: This - bit is set to one to indicate that - a valid responder identifier has - been logged. - - @param PreciseInsPointer Bit63, Precise instruction pointer. - This bit is set to one to indicate - that a valid precise instruction - pointer has been logged. - -**/ typedef struct { - UINT64 Operation:4; - UINT64 FailedCacheLevel:2; + UINT64 Operation:4; /// Bit3:0, Type of cache operation that caused + /// the machine check: 0 - unknown or internal + /// error 1 - load 2 - store 3 - instruction + /// fetch or instruction prefetch 4 - data + /// prefetch (both hardware and software) 5 - + /// snoop (coherency check) 6 - cast out + /// (explicit or implicit write-back of a cache + /// line) 7 - move in (cache line fill) + + UINT64 FailedCacheLevel:2; /// Bit5:4 Level of cache where the + /// error occurred. A value of 0 + /// indicates the first level of cache. UINT64 Reserved1:2; - UINT64 FailedInDataPart:1; - UINT64 FailedInTagPart:1; - UINT64 FailedInDataCache:1; - UINT64 FailedInInsCache:1; - UINT64 Mesi:3; - UINT64 MesiIsValid:1; - UINT64 FailedWay:5; - UINT64 WayIndexIsValid:1; + UINT64 FailedInDataPart:1; /// Bit8, Failure located in the data part of the cache line. + UINT64 FailedInTagPart:1; /// Bit9, Failure located in the tag part of the cache line. + UINT64 FailedInDataCache:1; /// Bit10, Failure located in the data cache + + UINT64 FailedInInsCache:1; /// Bit11, Failure located in the + /// instruction cache. + + UINT64 Mesi:3; /// Bit14:12, 0 - cache line is invalid. 1 - cache + /// line is held shared. 2 - cache line is held + /// exclusive. 3 - cache line is modified. All other + /// values are reserved. + + UINT64 MesiIsValid:1; /// Bit15, The mesi field in the cache_check + /// parameter is valid. + + UINT64 FailedWay:5; /// Bit20:16, Failure located in the way of + /// the cache indicated by this value. + + UINT64 WayIndexIsValid:1; /// Bit21, The way and index field in the + /// cache_check parameter is valid. UINT64 Reserved2:1; - UINT64 MultipleBitsError:1; + UINT64 MultipleBitsError:1; /// Bit23, A multiple-bit error was + /// detected, and data was poisoned for + /// the corresponding cache line during + /// castout. UINT64 Reserved3:8; - UINT64 IndexOfCacheLineError:20; + UINT64 IndexOfCacheLineError:20; /// Bit51:32, Index of the cache + /// line where the error occurred. UINT64 Reserved4:2; - UINT64 InstructionSet:1; - UINT64 InstructionSetIsValid:1; - - UINT64 PrivilegeLevel:2; - UINT64 PrivilegeLevelIsValide:1; - UINT64 McCorrected:1; - - UINT64 TargetAddressIsValid:1; - UINT64 RequesterIdentifier:1; - UINT64 ResponserIdentifier:1; - UINT64 PreciseInsPointer:1; + UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value + /// is set to zero, the instruction that + /// generated the machine check was an + /// Intel Itanium instruction. If this bit + /// is set to one, the instruction that + /// generated the machine check was IA-32 + /// instruction. + + UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the + /// cache_check parameter is valid. + + UINT64 PrivilegeLevel:2; /// Bit57:56, Privilege level. The + /// privilege level of the instruction + /// bundle responsible for generating the + /// machine check. + + UINT64 PrivilegeLevelIsValide:1; /// Bit58, The pl field of the + /// cache_check parameter is + /// valid. + + UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit + /// is set to one to indicate that the machine + /// check has been corrected. + + UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid: + /// This bit is set to one to + /// indicate that a valid target + /// address has been logged. + + UINT64 RequesterIdentifier:1; /// Bit61, Requester identifier: This + /// bit is set to one to indicate that + /// a valid requester identifier has + /// been logged. + + UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This + /// bit is set to one to indicate that + /// a valid responder identifier has + /// been logged. + + UINT64 PreciseInsPointer:1; /// Bit63, Precise instruction pointer. + /// This bit is set to one to indicate + /// that a valid precise instruction + /// pointer has been logged. } PAL_CACHE_CHECK_INFO; -/** - - @param FailedSlot Bit7:0, Slot number of the translation - register where the failure occurred. - @param FailedSlotIsValid Bit8, The tr_slot field in the - TLB_check parameter is valid. - - @param TlbLevel Bit11:10, The level of the TLB where the - error occurred. A value of 0 indicates the - first level of TLB - - @param FailedInDataTr Bit16, Error occurred in the data - translation registers. - - @param FailedInInsTr Bit17, Error occurred in the instruction - translation registers - - @param FailedInDataTc Bit18, Error occurred in data - translation cache. - - @param FailedInInsTc Bit19, Error occurred in the instruction - translation cache. - - @param FailedOperation Bit23:20, Type of cache operation that - caused the machine check: 0 - unknown - 1 - TLB access due to load instruction - 2 - TLB access due to store - instruction 3 - TLB access due to - instruction fetch or instruction - prefetch 4 - TLB access due to data - prefetch (both hardware and software) - 5 - TLB shoot down access 6 - TLB - probe instruction (probe, tpa) 7 - - move in (VHPT fill) 8 - purge (insert - operation that purges entries or a TLB - purge instruction) All other values - are reserved. - - @param InstructionSet Bit54, Instruction set. If this value - is set to zero, the instruction that - generated the machine check was an - Intel Itanium instruction. If this bit - is set to one, the instruction that - generated the machine check was IA-32 - instruction. - - @param InstructionSetIsValid Bit55, The is field in the - TLB_check parameter is valid. - - @param PrivelegeLevel Bit57:56, Privilege level. The - privilege level of the instruction - bundle responsible for generating the - machine check. - - @param PrivelegeLevelIsValid Bit58, The pl field of the - TLB_check parameter is valid. - - @param McCorrected Bit59, Machine check corrected: This bit - is set to one to indicate that the machine - check has been corrected. - - @param TargetAddressIsValid Bit60, Target address is valid: - This bit is set to one to - indicate that a valid target - address has been logged. - - @param RequesterIdentifier Bit61 Requester identifier: This - bit is set to one to indicate that - a valid requester identifier has - been logged. - - @param ResponserIdentifier Bit62, Responder identifier: This - bit is set to one to indicate that - a valid responder identifier has - been logged. - - @param PreciseInsPointer Bit63 Precise instruction pointer. - This bit is set to one to indicate - that a valid precise instruction - pointer has been logged. -**/ typedef struct { - UINT64 FailedSlot:8; - UINT64 FailedSlotIsValid:1; + UINT64 FailedSlot:8; /// Bit7:0, Slot number of the translation + /// register where the failure occurred. + UINT64 FailedSlotIsValid:1; /// Bit8, The tr_slot field in the + /// TLB_check parameter is valid. UINT64 Reserved1 :1; - UINT64 TlbLevel:2; + UINT64 TlbLevel:2; /// Bit11:10, The level of the TLB where the + /// error occurred. A value of 0 indicates the + /// first level of TLB UINT64 Reserved2 :4; - UINT64 FailedInDataTr:1; - UINT64 FailedInInsTr:1; - UINT64 FailedInDataTc:1; - UINT64 FailedInInsTc:1; - UINT64 FailedOperation:4; + + UINT64 FailedInDataTr:1; /// Bit16, Error occurred in the data + /// translation registers. + + UINT64 FailedInInsTr:1; /// Bit17, Error occurred in the instruction + /// translation registers + + UINT64 FailedInDataTc:1; /// Bit18, Error occurred in data + /// translation cache. + + UINT64 FailedInInsTc:1; /// Bit19, Error occurred in the instruction + /// translation cache. + + UINT64 FailedOperation:4; /// Bit23:20, Type of cache operation that + /// caused the machine check: 0 - unknown + /// 1 - TLB access due to load instruction + /// 2 - TLB access due to store + /// instruction 3 - TLB access due to + /// instruction fetch or instruction + /// prefetch 4 - TLB access due to data + /// prefetch (both hardware and software) + /// 5 - TLB shoot down access 6 - TLB + /// probe instruction (probe, tpa) 7 - + /// move in (VHPT fill) 8 - purge (insert + /// operation that purges entries or a TLB + /// purge instruction) All other values + /// are reserved. + UINT64 Reserved3:30; - UINT64 InstructionSet:1; - UINT64 InstructionSetIsValid:1; - UINT64 PrivelegeLevel:2; - UINT64 PrivelegeLevelIsValid:1; - UINT64 McCorrected:1; - UINT64 TargetAddressIsValid:1; - UINT64 RequesterIdentifier:1; - UINT64 ResponserIdentifier:1; - UINT64 PreciseInsPointer:1; + UINT64 InstructionSet:1; /// Bit54, Instruction set. If this value + /// is set to zero, the instruction that + /// generated the machine check was an + /// Intel Itanium instruction. If this bit + /// is set to one, the instruction that + /// generated the machine check was IA-32 + /// instruction. + + UINT64 InstructionSetIsValid:1; /// Bit55, The is field in the + /// TLB_check parameter is valid. + + UINT64 PrivelegeLevel:2; /// Bit57:56, Privilege level. The + /// privilege level of the instruction + /// bundle responsible for generating the + /// machine check. + + UINT64 PrivelegeLevelIsValid:1; /// Bit58, The pl field of the + /// TLB_check parameter is valid. + + UINT64 McCorrected:1; /// Bit59, Machine check corrected: This bit + /// is set to one to indicate that the machine + /// check has been corrected. + + UINT64 TargetAddressIsValid:1; /// Bit60, Target address is valid: + /// This bit is set to one to + /// indicate that a valid target + /// address has been logged. + + UINT64 RequesterIdentifier:1; /// Bit61 Requester identifier: This + /// bit is set to one to indicate that + /// a valid requester identifier has + /// been logged. + + UINT64 ResponserIdentifier:1; /// Bit62, Responder identifier: This + /// bit is set to one to indicate that + /// a valid responder identifier has + /// been logged. + + UINT64 PreciseInsPointer:1; /// Bit63 Precise instruction pointer. + /// This bit is set to one to indicate + /// that a valid precise instruction + /// pointer has been logged. } PAL_TLB_CHECK_INFO; /** @@ -2430,151 +2216,132 @@ typedef struct { **/ #define PAL_TEST_INFO 37 -/** - - @param BufferSize Indicates the size in bytes of the memory - buffer that is passed to this procedure. - BufferSize must be greater than or equal in - size to the bytes_needed return value from - PAL_TEST_INFO, otherwise this procedure will - return with an invalid argument return - value. - - @param TestPhase Defines which phase of the processor - self-tests are requested to be run. A value - of zero indicates to run phase two of the - processor self-tests. Phase two of the - processor self-tests are ones that require - external memory to execute correctly. A - value of one indicates to run phase one of - the processor self-tests. Phase one of the - processor self-tests are tests run during - PALE_RESET and do not depend on external - memory to run correctly. When the caller - requests to have phase one of the processor - self-test run via this procedure call, a - memory buffer may be needed to save and - restore state as required by the PAL calling - conventions. The procedure PAL_TEST_INFO - informs the caller about the requirements of - the memory buffer. - -**/ typedef struct { - UINT64 BufferSize:56; - UINT64 TestPhase:8; + UINT64 BufferSize:56; /// Indicates the size in bytes of the memory + /// buffer that is passed to this procedure. + /// BufferSize must be greater than or equal in + /// size to the bytes_needed return value from + /// PAL_TEST_INFO, otherwise this procedure will + /// return with an invalid argument return + /// value. + + UINT64 TestPhase:8; /// Defines which phase of the processor + /// self-tests are requested to be run. A value + /// of zero indicates to run phase two of the + /// processor self-tests. Phase two of the + /// processor self-tests are ones that require + /// external memory to execute correctly. A + /// value of one indicates to run phase one of + /// the processor self-tests. Phase one of the + /// processor self-tests are tests run during + /// PALE_RESET and do not depend on external + /// memory to run correctly. When the caller + /// requests to have phase one of the processor + /// self-test run via this procedure call, a + /// memory buffer may be needed to save and + /// restore state as required by the PAL calling + /// conventions. The procedure PAL_TEST_INFO + /// informs the caller about the requirements of + /// the memory buffer. } PAL_TEST_INFO_INFO; -/** - - @param TestControl This is an ordered implementation-specific - control word that allows the user control - over the length and runtime of the - processor self-tests. This control word is - ordered from the longest running tests up - to the shortest running tests with bit 0 - controlling the longest running test. PAL - may not implement all 47-bits of the - test_control word. PAL communicates if a - bit provides control by placing a zero in - that bit. If a bit provides no control, - PAL will place a one in it. PAL will have - two sets of test_control bits for the two - phases of the processor self-test. PAL - provides information about implemented - test_control bits at the hand-off from PAL - to SAL for the firmware recovery check. - These test_control bits provide control - for phase one of processor self-test. It - also provides this information via the PAL - procedure call PAL_TEST_INFO for both the - phase one and phase two processor tests - depending on which information the caller - is requesting. PAL interprets these bits - as input parameters on two occasions. The - first time is when SAL passes control back - to PAL after the firmware recovery check. - The second time is when a call to - PAL_TEST_PROC is made. When PAL interprets - these bits it will only interpret - implemented test_control bits and will - ignore the values located in the - unimplemented test_control bits. PAL - interprets the implemented bits such that - if a bit contains a zero, this indicates - to run the test. If a bit contains a one, - this indicates to PAL to skip the test. If - the cs bit indicates that control is not - available, the test_control bits will be - ignored or generate an illegal argument in - procedure calls if the caller sets these - bits. - - @param ControlSupport This bit defines if an implementation - supports control of the PAL self-tests - via the self-test control word. If - this bit is 0, the implementation does - not support control of the processor - self-tests via the self-test control - word. If this bit is 1, the - implementation does support control of - the processor self-tests via the - self-test control word. If control is - not supported, GR37 will be ignored at - the hand-off between SAL and PAL after - the firmware recovery check and the - PAL procedures related to the - processor self-tests may return - illegal arguments if a user tries to - use the self-test control features. - -**/ typedef struct { - UINT64 TestControl:47; - UINT64 ControlSupport:1; + UINT64 TestControl:47; /// This is an ordered implementation-specific + /// control word that allows the user control + /// over the length and runtime of the + /// processor self-tests. This control word is + /// ordered from the longest running tests up + /// to the shortest running tests with bit 0 + /// controlling the longest running test. PAL + /// may not implement all 47-bits of the + /// test_control word. PAL communicates if a + /// bit provides control by placing a zero in + /// that bit. If a bit provides no control, + /// PAL will place a one in it. PAL will have + /// two sets of test_control bits for the two + /// phases of the processor self-test. PAL + /// provides information about implemented + /// test_control bits at the hand-off from PAL + /// to SAL for the firmware recovery check. + /// These test_control bits provide control + /// for phase one of processor self-test. It + /// also provides this information via the PAL + /// procedure call PAL_TEST_INFO for both the + /// phase one and phase two processor tests + /// depending on which information the caller + /// is requesting. PAL interprets these bits + /// as input parameters on two occasions. The + /// first time is when SAL passes control back + /// to PAL after the firmware recovery check. + /// The second time is when a call to + /// PAL_TEST_PROC is made. When PAL interprets + /// these bits it will only interpret + /// implemented test_control bits and will + /// ignore the values located in the + /// unimplemented test_control bits. PAL + /// interprets the implemented bits such that + /// if a bit contains a zero, this indicates + /// to run the test. If a bit contains a one, + /// this indicates to PAL to skip the test. If + /// the cs bit indicates that control is not + /// available, the test_control bits will be + /// ignored or generate an illegal argument in + /// procedure calls if the caller sets these + /// bits. + + UINT64 ControlSupport:1; /// This bit defines if an implementation + /// supports control of the PAL self-tests + /// via the self-test control word. If + /// this bit is 0, the implementation does + /// not support control of the processor + /// self-tests via the self-test control + /// word. If this bit is 1, the + /// implementation does support control of + /// the processor self-tests via the + /// self-test control word. If control is + /// not supported, GR37 will be ignored at + /// the hand-off between SAL and PAL after + /// the firmware recovery check and the + /// PAL procedures related to the + /// processor self-tests may return + /// illegal arguments if a user tries to + /// use the self-test control features. UINT64 Reserved:16; } PAL_SELF_TEST_CONTROL; -/** - - @param Attributes Specifies the memory attributes that are - allowed to be used with the memory buffer - passed to this procedure. The attributes - parameter is a vector where each bit - represents one of the virtual memory - attributes defined by the architecture.See - MEMORY_AATRIBUTES. The caller is required - to support the cacheable attribute for the - memory buffer, otherwise an invalid - argument will be returned. - - - @param TestControl Is the self-test control word - corresponding to the test_phase passed. - This test_control directs the coverage and - runtime of the processor self-tests - specified by the test_phase input - argument. Information on if this - feature is implemented and the number of - bits supported can be obtained by the - PAL_TEST_INFO procedure call. If this - feature is implemented by the processor, - the caller can selectively skip parts of - the processor self-test by setting - test_control bits to a one. If a bit has a - zero, this test will be run. The values in - the unimplemented bits are ignored. If - PAL_TEST_INFO indicated that the self-test - control word is not implemented, this - procedure will return with an invalid - argument status if the caller sets any of - the test_control bits. See - PAL_SELF_TEST_CONTROL. -**/ typedef struct { - UINT64 Attributes:8; + UINT64 Attributes:8; /// Specifies the memory attributes that are + /// allowed to be used with the memory buffer + /// passed to this procedure. The attributes + /// parameter is a vector where each bit + /// represents one of the virtual memory + /// attributes defined by the architecture.See + /// MEMORY_AATRIBUTES. The caller is required + /// to support the cacheable attribute for the + /// memory buffer, otherwise an invalid + /// argument will be returned. UINT64 Reserved:8; - UINT64 TestControl:48; + UINT64 TestControl:48; /// Is the self-test control word + /// corresponding to the test_phase passed. + /// This test_control directs the coverage and + /// runtime of the processor self-tests + /// specified by the test_phase input + /// argument. Information on if this + /// feature is implemented and the number of + /// bits supported can be obtained by the + /// PAL_TEST_INFO procedure call. If this + /// feature is implemented by the processor, + /// the caller can selectively skip parts of + /// the processor self-test by setting + /// test_control bits to a one. If a bit has a + /// zero, this test will be run. The values in + /// the unimplemented bits are ignored. If + /// PAL_TEST_INFO indicated that the self-test + /// control word is not implemented, this + /// procedure will return with an invalid + /// argument status if the caller sets any of + /// the test_control bits. See + /// PAL_SELF_TEST_CONTROL. } PAL_TEST_CONTROL; /** @@ -2611,19 +2378,13 @@ typedef struct { **/ #define PAL_TEST_PROC 258 -/** - - @param NumberOfInterruptControllers Number of interrupt - controllers currently - enabled on the system. - - @param NumberOfProcessors Number of processors currently - enabled on the system. - -**/ typedef struct { - UINT32 NumberOfInterruptControllers; - UINT32 NumberOfProcessors; + UINT32 NumberOfInterruptControllers; /// Number of interrupt + /// controllers currently + /// enabled on the system. + + UINT32 NumberOfProcessors; /// Number of processors currently + /// enabled on the system. } PAL_PLATFORM_INFO; /** @@ -2897,175 +2658,152 @@ typedef struct { **/ #define PAL_SET_HW_POLICY 49 - -/** - - @param Mode Bit2:0, Indicates the mode of operation for this - procedure: 0 - Query mode 1 - Error inject mode - (err_inj should also be specified) 2 - Cancel - outstanding trigger. All other fields in - PAL_MC_ERROR_TYPE_INFO, - PAL_MC_ERROR_STRUCTURE_INFO and - PAL_MC_ERROR_DATA_BUFFER are ignored. All other - values are reserved. - - @param ErrorInjection Bit5:3, indicates the mode of error - injection: 0 - Error inject only (no - error consumption) 1 - Error inject - and consume All other values are - reserved. - - - @param ErrorSeverity Bit7:6, indicates the severity desired - for error injection/query. Definitions - of the different error severity types - 0 - Corrected error 1 - Recoverable - error 2 - Fatal error 3 - Reserved - - - @param ErrorStructure Bit12:8, Indicates the structure - identification for error - injection/query: 0 - Any structure - (cannot be used during query mode). - When selected, the structure type used - for error injection is determined by - PAL. 1 - Cache 2 - TLB 3 - Register - file 4 - Bus/System interconnect 5-15 - - Reserved 16-31 - Processor - specific error injection - capabilities.ErrorDataBuffer is used - to specify error types. Please refer - to the processor specific - documentation for additional details. - - @param StructureHierarchy Bit15:13, Indicates the structure - hierarchy for error - injection/query: 0 - Any level of - hierarchy (cannot be used during - query mode). When selected, the - structure hierarchy used for error - injection is determined by PAL. 1 - - Error structure hierarchy - level-1 2 - Error structure - hierarchy level-2 3 - Error - structure hierarchy level-3 4 - - Error structure hierarchy level-4 - All other values are reserved. - Reserved 63:16 Reserved - -**/ typedef struct { - UINT64 Mode:3; - UINT64 ErrorInjection:3; - UINT64 ErrorSeverity:2; - UINT64 ErrorStructure:5; - UINT64 StructureHierarchy:3; + UINT64 Mode:3; /// Bit2:0, Indicates the mode of operation for this + /// procedure: 0 - Query mode 1 - Error inject mode + /// (err_inj should also be specified) 2 - Cancel + /// outstanding trigger. All other fields in + /// PAL_MC_ERROR_TYPE_INFO, + /// PAL_MC_ERROR_STRUCTURE_INFO and + /// PAL_MC_ERROR_DATA_BUFFER are ignored. All other + /// values are reserved. + + UINT64 ErrorInjection:3; /// Bit5:3, indicates the mode of error + /// injection: 0 - Error inject only (no + /// error consumption) 1 - Error inject + /// and consume All other values are + /// reserved. + + UINT64 ErrorSeverity:2; /// Bit7:6, indicates the severity desired + /// for error injection/query. Definitions + /// of the different error severity types + /// 0 - Corrected error 1 - Recoverable + /// error 2 - Fatal error 3 - Reserved + + UINT64 ErrorStructure:5; /// Bit12:8, Indicates the structure + /// identification for error + /// injection/query: 0 - Any structure + /// (cannot be used during query mode). + /// When selected, the structure type used + /// for error injection is determined by + /// PAL. 1 - Cache 2 - TLB 3 - Register + /// file 4 - Bus/System interconnect 5-15 + /// - Reserved 16-31 - Processor + /// specific error injection + /// capabilities.ErrorDataBuffer is used + /// to specify error types. Please refer + /// to the processor specific + /// documentation for additional details. + + UINT64 StructureHierarchy:3; /// Bit15:13, Indicates the structure + /// hierarchy for error + /// injection/query: 0 - Any level of + /// hierarchy (cannot be used during + /// query mode). When selected, the + /// structure hierarchy used for error + /// injection is determined by PAL. 1 + /// - Error structure hierarchy + /// level-1 2 - Error structure + /// hierarchy level-2 3 - Error + /// structure hierarchy level-3 4 - + /// Error structure hierarchy level-4 + /// All other values are reserved. + /// Reserved 63:16 Reserved + UINT64 Reserved:48; } PAL_MC_ERROR_TYPE_INFO; -/** +typedef struct { + UINT64 StructInfoIsValid:1; /// Bit0 When 1, indicates that the + /// structure information fields + /// (c_t,cl_p,cl_id) are valid and + /// should be used for error injection. + /// When 0, the structure information + /// fields are ignored, and the values + /// of these fields used for error + /// injection are + /// implementation-specific. + + UINT64 CacheType:2; /// Bit2:1 Indicates which cache should be used + /// for error injection: 0 - Reserved 1 - + /// Instruction cache 2 - Data or unified cache + /// 3 - Reserved + + UINT64 PortionOfCacheLine:3; /// Bit5:3 Indicates the portion of the + /// cache line where the error should + /// be injected: 0 - Reserved 1 - Tag + /// 2 - Data 3 - mesi All other + /// values are reserved. + + UINT64 Mechanism:3; /// Bit8:6 Indicates which mechanism is used to + /// identify the cache line to be used for error + /// injection: 0 - Reserved 1 - Virtual address + /// provided in the inj_addr field of the buffer + /// pointed to by err_data_buffer should be used + /// to identify the cache line for error + /// injection. 2 - Physical address provided in + /// the inj_addr field of the buffer pointed to + /// by err_data_buffershould be used to identify + /// the cache line for error injection. 3 - way + /// and index fields provided in err_data_buffer + /// should be used to identify the cache line + /// for error injection. All other values are + /// reserved. + + UINT64 DataPoisonOfCacheLine:1; /// Bit9 When 1, indicates that a + /// multiple bit, non-correctable + /// error should be injected in the + /// cache line specified by cl_id. + /// If this injected error is not + /// consumed, it may eventually + /// cause a data-poisoning event + /// resulting in a corrected error + /// signal, when the associated + /// cache line is cast out (implicit + /// or explicit write-back of the + /// cache line). The error severity + /// specified by err_sev in + /// err_type_info must be set to 0 + /// (corrected error) when this bit + /// is set. - @param StructInfoIsValid Bit0 When 1, indicates that the - structure information fields - (c_t,cl_p,cl_id) are valid and - should be used for error injection. - When 0, the structure information - fields are ignored, and the values - of these fields used for error - injection are - implementation-specific. - - @param CacheType Bit2:1 Indicates which cache should be used - for error injection: 0 - Reserved 1 - - Instruction cache 2 - Data or unified cache - 3 - Reserved - - - @param PortionOfCacheLine Bit5:3 Indicates the portion of the - cache line where the error should - be injected: 0 - Reserved 1 - Tag - 2 - Data 3 - mesi All other - values are reserved. - - @param Mechanism Bit8:6 Indicates which mechanism is used to - identify the cache line to be used for error - injection: 0 - Reserved 1 - Virtual address - provided in the inj_addr field of the buffer - pointed to by err_data_buffer should be used - to identify the cache line for error - injection. 2 - Physical address provided in - the inj_addr field of the buffer pointed to - by err_data_buffershould be used to identify - the cache line for error injection. 3 - way - and index fields provided in err_data_buffer - should be used to identify the cache line - for error injection. All other values are - reserved. + UINT64 Reserved1:22; - @param DataPoisonOfCacheLine Bit9 When 1, indicates that a - multiple bit, non-correctable - error should be injected in the - cache line specified by cl_id. - If this injected error is not - consumed, it may eventually - cause a data-poisoning event - resulting in a corrected error - signal, when the associated - cache line is cast out (implicit - or explicit write-back of the - cache line). The error severity - specified by err_sev in - err_type_info must be set to 0 - (corrected error) when this bit - is set. - - - @param TrigerInfoIsValid Bit32 When 1, indicates that the - trigger information fields (trigger, - trigger_pl) are valid and should be - used for error injection. When 0, - the trigger information fields are - ignored and error injection is - performed immediately. - - @param Triger Bit36:33 Indicates the operation type to be - used as the error trigger condition. The - address corresponding to the trigger is - specified in the trigger_addr field of the - buffer pointed to by err_data_buffer: 0 - - Instruction memory access. The trigger match - conditions for this operation type are similar - to the IBR address breakpoint match conditions - 1 - Data memory access. The trigger match - conditions for this operation type are similar - to the DBR address breakpoint match conditions - All other values are reserved. - - @param PrivilegeOfTriger Bit39:37 Indicates the privilege - level of the context during which - the error should be injected: 0 - - privilege level 0 1 - privilege - level 1 2 - privilege level 2 3 - - privilege level 3 All other values - are reserved. If the implementation - does not support privilege level - qualifier for triggers (i.e. if - trigger_pl is 0 in the capabilities - vector), this field is ignored and - triggers can be taken at any - privilege level. + UINT64 TrigerInfoIsValid:1; /// Bit32 When 1, indicates that the + /// trigger information fields (trigger, + /// trigger_pl) are valid and should be + /// used for error injection. When 0, + /// the trigger information fields are + /// ignored and error injection is + /// performed immediately. + + UINT64 Triger:4; /// Bit36:33 Indicates the operation type to be + /// used as the error trigger condition. The + /// address corresponding to the trigger is + /// specified in the trigger_addr field of the + /// buffer pointed to by err_data_buffer: 0 - + /// Instruction memory access. The trigger match + /// conditions for this operation type are similar + /// to the IBR address breakpoint match conditions + /// 1 - Data memory access. The trigger match + /// conditions for this operation type are similar + /// to the DBR address breakpoint match conditions + /// All other values are reserved. + + UINT64 PrivilegeOfTriger:3; /// Bit39:37 Indicates the privilege + /// level of the context during which + /// the error should be injected: 0 - + /// privilege level 0 1 - privilege + /// level 1 2 - privilege level 2 3 - + /// privilege level 3 All other values + /// are reserved. If the implementation + /// does not support privilege level + /// qualifier for triggers (i.e. if + /// trigger_pl is 0 in the capabilities + /// vector), this field is ignored and + /// triggers can be taken at any + /// privilege level. -**/ -typedef struct { - UINT64 StructInfoIsValid:1; - UINT64 CacheType:2; - UINT64 PortionOfCacheLine:3; - UINT64 Mechanism:3; - UINT64 DataPoisonOfCacheLine:1; - UINT64 Reserved1:22; - UINT64 TrigerInfoIsValid:1; - UINT64 Triger:4; - UINT64 PrivilegeOfTriger:3; UINT64 Reserved2:24; } PAL_MC_ERROR_STRUCT_INFO; -- cgit v1.2.3