From ded0b489af09cde5afa05d74acdb12cd4b4f8394 Mon Sep 17 00:00:00 2001 From: Yong Li Date: Thu, 20 Apr 2023 12:36:40 +0800 Subject: MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64 Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Appendix A: RVWMO Explanatory Material in https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin Cc: Evan Chai Cc: Sunil V L Cc: Tuan Phan Signed-off-by: Yong Li Reviewed-by: Sunil V L --- .../Library/BaseLib/RiscV64/SpeculationBarrier.S | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S (limited to 'MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S') diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S new file mode 100644 index 0000000000..581a765399 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S @@ -0,0 +1,34 @@ +##------------------------------------------------------------------------------ +# +# SpeculationBarrier() for RISCV64 +# +# Copyright (c) 2023, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +##------------------------------------------------------------------------------ + +.text +.p2align 2 + +ASM_GLOBAL ASM_PFX(SpeculationBarrier) + + +#/** +# Uses as a barrier to stop speculative execution. +# +# Ensures that no later instruction will execute speculatively, until all prior +# instructions have completed. +# +#**/ +#VOID +#EFIAPI +#SpeculationBarrier ( +# VOID +# ); +# +ASM_PFX(SpeculationBarrier): + fence rw,rw + fence.i + fence r,r + ret -- cgit v1.2.3