From 287f4f47b42d87c670b2cb4b440f4fd0288cfd01 Mon Sep 17 00:00:00 2001 From: xli24 Date: Thu, 4 Jun 2009 14:29:12 +0000 Subject: Add ASSERT check for AsmFlushCacheRange(). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8465 6f19259b-4bc3-4df7-8a09-765794883524 --- MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c | 8 +- MdePkg/Library/BaseLib/BaseLib.inf | 5 +- MdePkg/Library/BaseLib/BaseLibInternals.h | 34 +++++++- MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c | 51 ++++++++++++ MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s | 96 ---------------------- .../Library/BaseLib/Ipf/InternalFlushCacheRange.s | 94 +++++++++++++++++++++ 6 files changed, 182 insertions(+), 106 deletions(-) create mode 100644 MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c delete mode 100644 MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s create mode 100644 MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s (limited to 'MdePkg/Library') diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c index 1e5241832f..fe14ecf301 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c @@ -1,7 +1,7 @@ /** @file Cache Maintenance Functions. - Copyright (c) 2006 - 2008, Intel Corporation
+ Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -64,7 +64,6 @@ InvalidateInstructionCacheRange ( IN UINTN Length ) { - ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); return AsmFlushCacheRange (Address, Length); } @@ -120,8 +119,6 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); - return AsmFlushCacheRange (Address, Length); } @@ -176,8 +173,6 @@ WriteBackDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); - return AsmFlushCacheRange (Address, Length); } @@ -239,7 +234,6 @@ InvalidateDataCacheRange ( IN UINTN Length ) { - ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); // // Invalidation of a data cache range without writing back is not supported on // IPF architecture, so write back and invalidate operation is performed. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 822ee59f8d..e60b9b794b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,7 +1,7 @@ #/** @file # Base Library implementation. # -# Copyright (c) 2007 - 2008, Intel Corporation. +# Copyright (c) 2007 - 2009, Intel Corporation. # # All rights reserved. This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -558,7 +558,8 @@ Ipf/AccessMsr.s | INTEL Ipf/AccessMsr.s | GCC Ipf/AccessMsrDb.s | MSFT - Ipf/FlushCacheRange.s + Ipf/InternalFlushCacheRange.s + Ipf/FlushCacheRange.c Ipf/InternalSwitchStack.c Ipf/GetInterruptState.s Ipf/CpuPause.s diff --git a/MdePkg/Library/BaseLib/BaseLibInternals.h b/MdePkg/Library/BaseLib/BaseLibInternals.h index 1c166b7c84..b1bde8dc4f 100644 --- a/MdePkg/Library/BaseLib/BaseLibInternals.h +++ b/MdePkg/Library/BaseLib/BaseLibInternals.h @@ -1,7 +1,7 @@ /** @file Declaration of internal functions in BaseLib. - Copyright (c) 2006 - 2008, Intel Corporation
+ Copyright (c) 2006 - 2009, Intel Corporation
All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -1616,6 +1616,38 @@ AsmSwitchStackAndBackingStore ( IN VOID *NewStack, IN VOID *NewBsp ); + +/** + Internal worker function to invalidate a range of instruction cache lines + in the cache coherency domain of the calling CPU. + + Internal worker function to invalidate the instruction cache lines specified + by Address and Length. If Address is not aligned on a cache line boundary, + then entire instruction cache line containing Address is invalidated. If + Address + Length is not aligned on a cache line boundary, then the entire + instruction cache line containing Address + Length -1 is invalidated. This + function may choose to invalidate the entire instruction cache if that is more + efficient than invalidating the specified range. If Length is 0, the no instruction + cache lines are invalidated. Address is returned. + This function is only available on IPF. + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode, then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction cache. + + @return Address + +**/ +VOID * +EFIAPI +InternalFlushCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + #else #endif diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c new file mode 100644 index 0000000000..4ceee5690f --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c @@ -0,0 +1,51 @@ +/** @file + AsmFlushCacheRange() function for IPF. + + Copyright (c) 2009, Intel Corporation
+ All rights reserved. This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include "BaseLibInternals.h" + +/** + Flush a range of cache lines in the cache coherency domain of the calling + CPU. + + Flushes the cache lines specified by Address and Length. If Address is not aligned + on a cache line boundary, then entire cache line containing Address is flushed. + If Address + Length is not aligned on a cache line boundary, then the entire cache + line containing Address + Length - 1 is flushed. This function may choose to flush + the entire cache if that is more efficient than flushing the specified range. If + Length is 0, the no cache lines are flushed. Address is returned. + This function is only available on IPF. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction lines to invalidate. If + the CPU is in a physical addressing mode, then Address is a + physical address. If the CPU is in a virtual addressing mode, + then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction cache. + + @return Address. + +**/ +VOID * +EFIAPI +AsmFlushCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); + return InternalFlushCacheRange (Address, Length); +} diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s deleted file mode 100644 index 5801fcbb83..0000000000 --- a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s +++ /dev/null @@ -1,96 +0,0 @@ -//++ -// Copyright (c) 2006 - 2008, Intel Corporation -// All rights reserved. This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// Module Name: -// FlushCacheRange.s -// -// Abstract: -// Assemble routine to flush cache lines -// -// Revision History: -// -//-- -.file "IpfCpuCache.s" - -#include - -// -// Invalidates a range of instruction cache lines in the cache coherency domain -// of the calling CPU. -// -// Invalidates the instruction cache lines specified by Address and Length. If -// Address is not aligned on a cache line boundary, then entire instruction -// cache line containing Address is invalidated. If Address + Length is not -// aligned on a cache line boundary, then the entire instruction cache line -// containing Address + Length -1 is invalidated. This function may choose to -// invalidate the entire instruction cache if that is more efficient than -// invalidating the specified range. If Length is 0, the no instruction cache -// lines are invalidated. Address is returned. -// This function is only available on IPF. -// -// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). -// -// @param Address The base address of the instruction cache lines to -// invalidate. If the CPU is in a physical addressing mode, then -// Address is a physical address. If the CPU is in a virtual -// addressing mode, then Address is a virtual address. -// -// @param Length The number of bytes to invalidate from the instruction cache. -// -// @return Address -// -// VOID * -// EFIAPI -// AsmFlushCacheRange ( -// IN VOID *Address, -// IN UINTN Length -// ); -// -PROCEDURE_ENTRY (AsmFlushCacheRange) - - NESTED_SETUP (5,8,0,0) - - mov loc2 = ar.lc - - mov loc3 = in0 // Start address. - mov loc4 = in1;; // Length in bytes. - - cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache - (p6) br.spnt.many DoneFlushingC;; - - add loc4 = loc4,loc3 - mov loc5 = 1;; - sub loc4 = loc4, loc5 ;; // the End address to flush - - dep loc3 = r0,loc3,0,5 - dep loc4 = r0,loc4,0,5;; - shr loc3 = loc3,5 - shr loc4 = loc4,5;; // 32 byte cache line - - sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but - // the br.cloop will first execute one time - mov loc3 = in0 - mov loc5 = 32 - mov ar.lc = loc4;; - -StillFlushingC: - fc loc3;; - sync.i;; - srlz.i;; - add loc3 = loc5,loc3;; - br.cloop.sptk.few StillFlushingC;; - -DoneFlushingC: - mov ar.lc = loc2 - mov r8 = in0 // return *Address - NESTED_RETURN - -PROCEDURE_EXIT (AsmFlushCacheRange) - diff --git a/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s new file mode 100644 index 0000000000..36aa885b9d --- /dev/null +++ b/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s @@ -0,0 +1,94 @@ +//++ +// Copyright (c) 2006 - 2009, Intel Corporation +// All rights reserved. This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// Module Name: +// InternalFlushCacheRange.s +// +// Abstract: +// Assemble routine to flush cache lines +// +// Revision History: +// +//-- +.file "IpfCpuCache.s" + +#include + +// +// Internal worker function to invalidate a range of instruction cache lines +// in the cache coherency domain of the calling CPU. +// +// Internal worker function to invalidate the instruction cache lines specified +// by Address and Length. If Address is not aligned on a cache line boundary, +// then entire instruction cache line containing Address is invalidated. If +// Address + Length is not aligned on a cache line boundary, then the entire +// instruction cache line containing Address + Length -1 is invalidated. This +// function may choose to invalidate the entire instruction cache if that is more +// efficient than invalidating the specified range. If Length is 0, the no instruction +// cache lines are invalidated. Address is returned. +// This function is only available on IPF. +// +// @param Address The base address of the instruction cache lines to +// invalidate. If the CPU is in a physical addressing mode, then +// Address is a physical address. If the CPU is in a virtual +// addressing mode, then Address is a virtual address. +// +// @param Length The number of bytes to invalidate from the instruction cache. +// +// @return Address +// +// VOID * +// EFIAPI +// InternalFlushCacheRange ( +// IN VOID *Address, +// IN UINTN Length +// ); +// +PROCEDURE_ENTRY (InternalFlushCacheRange) + + NESTED_SETUP (5,8,0,0) + + mov loc2 = ar.lc + + mov loc3 = in0 // Start address. + mov loc4 = in1;; // Length in bytes. + + cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache + (p6) br.spnt.many DoneFlushingC;; + + add loc4 = loc4,loc3 + mov loc5 = 1;; + sub loc4 = loc4, loc5 ;; // the End address to flush + + dep loc3 = r0,loc3,0,5 + dep loc4 = r0,loc4,0,5;; + shr loc3 = loc3,5 + shr loc4 = loc4,5;; // 32 byte cache line + + sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but + // the br.cloop will first execute one time + mov loc3 = in0 + mov loc5 = 32 + mov ar.lc = loc4;; + +StillFlushingC: + fc loc3;; + sync.i;; + srlz.i;; + add loc3 = loc5,loc3;; + br.cloop.sptk.few StillFlushingC;; + +DoneFlushingC: + mov ar.lc = loc2 + mov r8 = in0 // return *Address + NESTED_RETURN + +PROCEDURE_EXIT (InternalFlushCacheRange) + -- cgit v1.2.3