From b2b16999102cb466ec8cc526ff997326cc2fb859 Mon Sep 17 00:00:00 2001 From: jljusten Date: Fri, 4 May 2012 15:01:24 +0000 Subject: OvmfPkg/AcpiTables: Update GPE0 block address range for QEMU QEMU hard codes the GPE0 registers at 0xafe0. Previously the code assumed that the GPE0 block would move when the PM Base Address of the PIIX4 PCI device was programmed. It appears QEMU does not emulate this behaviour of the PIIX4 PCI device. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen Reviewed-by: Erik Bjorge Tested-by: Laszlo Ersek Reviewed-by: Laszlo Ersek Tested-by: Bei Guan Reviewed-by: Bei Guan git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524 --- OvmfPkg/AcpiTables/Dsdt.asl | 1 + OvmfPkg/AcpiTables/Platform.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'OvmfPkg/AcpiTables') diff --git a/OvmfPkg/AcpiTables/Dsdt.asl b/OvmfPkg/AcpiTables/Dsdt.asl index ac0fec49e8..a0c762291e 100644 --- a/OvmfPkg/AcpiTables/Dsdt.asl +++ b/OvmfPkg/AcpiTables/Dsdt.asl @@ -368,6 +368,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) { IO (Decode16, 0x440, 0x440, 0x00, 0x10) IO (Decode16, 0x678, 0x678, 0x00, 0x08) IO (Decode16, 0x778, 0x778, 0x00, 0x08) + IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04) // QEMU GPE0 BLK Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000) }) diff --git a/OvmfPkg/AcpiTables/Platform.h b/OvmfPkg/AcpiTables/Platform.h index 4e56947270..c9aa547067 100644 --- a/OvmfPkg/AcpiTables/Platform.h +++ b/OvmfPkg/AcpiTables/Platform.h @@ -39,7 +39,7 @@ #define PM1b_CNT_BLK 0x00000000 #define PM2_CNT_BLK 0x00000022 #define PM_TMR_BLK 0x00000408 -#define GPE0_BLK 0x0000040C +#define GPE0_BLK 0x0000afe0 #define GPE1_BLK 0x00000000 #define PM1_EVT_LEN 0x04 #define PM1_CNT_LEN 0x02 -- cgit v1.2.3