From 60e95bf5094fbb9b728729ccfaf32184b3662317 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Tue, 22 Jan 2019 20:37:31 +0100 Subject: OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the MemMapInitialization() function, we currently have a common PciSize assignment, shared between i440fx and q35. In order to simplify the rest of this series, lift and duplicate the assignment identically to both board-specific branches. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 Signed-off-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ard Biesheuvel --- OvmfPkg/PlatformPei/Platform.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'OvmfPkg/PlatformPei') diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0876316eef..5e0a154842 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -190,8 +190,10 @@ MemMapInitialization ( ASSERT (TopOfLowRam <= PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); PciBase = (UINT32)(PciExBarBase + SIZE_256MB); + PciSize = 0xFC000000 - PciBase; } else { PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; + PciSize = 0xFC000000 - PciBase; } // @@ -207,7 +209,6 @@ MemMapInitialization ( // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // - PciSize = 0xFC000000 - PciBase; AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); -- cgit v1.2.3