From 0b7c6cd4018c557677391388025b9bb2ab45997c Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Mon, 23 Feb 2015 16:02:34 +0000 Subject: PcAtChipsetPkg/PciHostBridgeDxe: fix typo in "aperture" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek Acked-by: Olivier Martin Reviewed-by: Jordan Justen git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16891 6f19259b-4bc3-4df7-8a09-765794883524 --- PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c | 6 +++--- PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h | 6 +++--- PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 18 +++++++++--------- 3 files changed, 15 insertions(+), 15 deletions(-) (limited to 'PcAtChipsetPkg') diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c index 83fcdf4f1a..2f6ef68f1d 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c @@ -18,7 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // Hard code: Root Bridge Number within the host bridge // Root Bridge's attribute // Root Bridge's device path -// Root Bridge's resource appeture +// Root Bridge's resource aperture // UINTN RootBridgeNumber[1] = { 1 }; @@ -52,7 +52,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = { } }; -PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] = { +PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1] = { {{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}} }; @@ -145,7 +145,7 @@ InitializePciHostBridge ( &PrivateData->Io, HostBridge->HostBridgeHandle, RootBridgeAttribute[Loop1][Loop2], - &mResAppeture[Loop1][Loop2] + &mResAperture[Loop1][Loop2] ); Status = gBS->InstallMultipleProtocolInterfaces( diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h index f81982985a..52ff532409 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h @@ -403,7 +403,7 @@ typedef struct { UINT64 IoBase; UINT64 IoLimit; -} PCI_ROOT_BRIDGE_RESOURCE_APPETURE; +} PCI_ROOT_BRIDGE_RESOURCE_APERTURE; typedef enum { TypeIo = 0, @@ -482,7 +482,7 @@ typedef struct { @param Protocol Point to protocol instance @param HostBridgeHandle Handle of host bridge @param Attri Attribute of host bridge - @param ResAppeture ResourceAppeture for host bridge + @param ResAperture ResourceAperture for host bridge @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. @@ -492,7 +492,7 @@ RootBridgeConstructor ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, IN EFI_HANDLE HostBridgeHandle, IN UINT64 Attri, - IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture ); #endif diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c index 7946324d9f..c7d9f06fb0 100644 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -621,7 +621,7 @@ UINT8 mOutStride[] = { @param Protocol Point to protocol instance @param HostBridgeHandle Handle of host bridge @param Attri Attribute of host bridge - @param ResAppeture ResourceAppeture for host bridge + @param ResAperture ResourceAperture for host bridge @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. @@ -631,7 +631,7 @@ RootBridgeConstructor ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, IN EFI_HANDLE HostBridgeHandle, IN UINT64 Attri, - IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture ) { EFI_STATUS Status; @@ -644,21 +644,21 @@ RootBridgeConstructor ( // The host to pci bridge, the host memory and io addresses are // direct mapped to pci addresses, so no need translate, set bases to 0. // - PrivateData->MemBase = ResAppeture->MemBase; - PrivateData->IoBase = ResAppeture->IoBase; + PrivateData->MemBase = ResAperture->MemBase; + PrivateData->IoBase = ResAperture->IoBase; // // The host bridge only supports 32bit addressing for memory // and standard IA32 16bit io // - PrivateData->MemLimit = ResAppeture->MemLimit; - PrivateData->IoLimit = ResAppeture->IoLimit; + PrivateData->MemLimit = ResAperture->MemLimit; + PrivateData->IoLimit = ResAperture->IoLimit; // - // Bus Appeture for this Root Bridge (Possible Range) + // Bus Aperture for this Root Bridge (Possible Range) // - PrivateData->BusBase = ResAppeture->BusBase; - PrivateData->BusLimit = ResAppeture->BusLimit; + PrivateData->BusBase = ResAperture->BusBase; + PrivateData->BusLimit = ResAperture->BusLimit; // // Specific for this chipset -- cgit v1.2.3