From 2cb6eabe0b358fe0d4e4dd602f84b5f5d3e39a6c Mon Sep 17 00:00:00 2001
From: Elvin Li <elvin.li@intel.com>
Date: Wed, 22 Oct 2014 05:01:58 +0000
Subject: Add DebugCommunicationLibUsb3 for USB3.0 source level debug support.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16224 6f19259b-4bc3-4df7-8a09-765794883524
---
 SourceLevelDebugPkg/SourceLevelDebugPkg.dec | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'SourceLevelDebugPkg/SourceLevelDebugPkg.dec')

diff --git a/SourceLevelDebugPkg/SourceLevelDebugPkg.dec b/SourceLevelDebugPkg/SourceLevelDebugPkg.dec
index 5c28e2934e..e634ca7638 100644
--- a/SourceLevelDebugPkg/SourceLevelDebugPkg.dec
+++ b/SourceLevelDebugPkg/SourceLevelDebugPkg.dec
@@ -91,5 +91,27 @@
   # @Prompt Assign debug port buffer size.
   gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugPortHandleBufferSize|0x0|UINT16|0x00000006
 
+  ## The memory BAR of xhci host controller, in which usb debug feature is enabled.
+  ## Note that the memory BAR address is only used before Pci bus resource allocation.
+  # @Prompt Configure ehci host controller memory BAR.
+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciMemorySpaceBase|0xD0000000|UINT64|0x00000007
+  
+  ## The pci address of xhci host controller, in which usb debug feature is enabled.
+  #  The format of pci address is :<BR>
+  #      -----------------------------------------------------------------------<BR>
+  #      | Bits 28..31 | Bits 20..27 | Bits 15..19 | Bits 12..14 | Bits 00..11 |<BR>
+  #      -----------------------------------------------------------------------<BR>
+  #      |      0      |     Bus     |   Device    |   Function  |      0      |<BR>
+  #      -----------------------------------------------------------------------<BR>
+  #  For the value 0x000A0000, it means the pci address at bus 0x0, device 0x14, function 0x0.
+  # @Prompt Configure xhci host controller pci address.
+  # @Expression  0x80000001 | (gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress & 0xF0000FFF) == 0
+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress|0x000A0000|UINT32|0x00000008
+  
+  ## Per XHCI spec, software shall impose a timeout between the detection of the Debug Host 
+  ## connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.
+  # @Prompt Configure debug device detection timeout value.
+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout|3000000|UINT64|0x00000009
+
 [UserExtensions.TianoCore."ExtraFiles"]
   SourceLevelDebugPkgExtra.uni
-- 
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