From 6cfeeb71c43173d657d86d4a38ed655b0fc5f277 Mon Sep 17 00:00:00 2001 From: Daoxiang Li Date: Wed, 2 Jun 2021 11:01:13 +0800 Subject: UefiCpuPkg/CpuCommonFeaturesLib: Correct the CPU location check REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424 Processor location information check needs to updated When Core 0 is disabled. In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in comments to match the correct MSR name. Signed-off-by: Daoxiang Li Cc: Eric Dong Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c') diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c index 8450c7ea3e..3c4c1bc706 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -130,10 +130,10 @@ PpinInitialize ( // Support function already check the processor which support PPIN feature, so this function not need // to check the processor again. // - // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for - // thread 0 core 0 in each package. + // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL + // once for each package. // - if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) { + if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { return RETURN_SUCCESS; } -- cgit v1.2.3