From 2d212083d048ee8c0f5b4b7c61720f16165427cb Mon Sep 17 00:00:00 2001 From: Dun Tan Date: Wed, 7 Jun 2023 15:46:58 +0800 Subject: UefiCpuPkg: Use CpuPageTableLib to convert SMM paging attribute. Simplify the ConvertMemoryPageAttributes API to convert paging attribute by CpuPageTableLib. In the new API, it calls PageTableMap() to update the page attributes of a memory range. With the PageTableMap() API in CpuPageTableLib, we can remove the complicated page table manipulating code. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64') diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 3deb1ffd67..0bed857cae 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -1,7 +1,7 @@ /** @file Page Fault (#PF) handler for X64 processors -Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -354,6 +354,11 @@ SmmInitPageTable ( m5LevelPagingNeeded = Is5LevelPagingNeeded (); mPhysicalAddressBits = CalculateMaximumSupportAddress (); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); + if (m5LevelPagingNeeded) { + mPagingMode = m1GPageTableSupport ? Paging5Level1GB : Paging5Level; + } else { + mPagingMode = m1GPageTableSupport ? Paging4Level1GB : Paging4Level; + } DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPagingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTableSupport)); DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRestrictedMemoryAccess)); -- cgit v1.2.3