From 3cbfba02fef9dae07a041fdbf2e89611d72d6f90 Mon Sep 17 00:00:00 2001 From: David Wei Date: Mon, 12 Jan 2015 09:37:20 +0000 Subject: Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to https://svn.code.sf.net/p/edk2/code/trunk/edk2/, which are for MinnowBoard MAX open source project. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei Reviewed-by: Mike Wu Reviewed-by: Hot Tian git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524 --- Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL | 623 ++++++++++ .../AcpiTablesPCAT/AcpiTablePlatform.h | 76 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf | 44 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl | 55 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL | 81 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc | 194 ++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc | 90 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl | 352 ++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl | 105 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL | 353 ++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc | 69 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL | 885 ++++++++++++++ .../AcpiTablesPCAT/INTELISPDev2.ASL | 77 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL | 161 +++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL | 491 ++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL | 280 +++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL | 305 +++++ .../AcpiTablesPCAT/IoTVirtualDevice.asl | 177 +++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL | 157 +++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl | 65 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc | 229 ++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h | 195 ++++ .../AcpiTablesPCAT/Madt/Madt30.aslc | 184 +++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc | 92 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL | 96 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl | 685 +++++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl | 42 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl | 275 +++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl | 1096 ++++++++++++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl | 56 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl | 616 ++++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl | 839 ++++++++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl | 385 +++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl | 373 ++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl | 830 ++++++++++++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl | 203 ++++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL | 138 +++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl | 99 ++ Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl | 40 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl | 45 + Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl | 45 + .../Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h | 30 + .../Include/Guid/PowerManagementAcpiTableStorage.h | 33 + .../ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h | 110 ++ .../CPU/Include/Protocol/PpmPlatformPolicy.h | 138 +++ .../ValleyView2Soc/CPU/Include/Types.h | 61 + .../AcpiTables/PowerManagementAcpiTables.inf | 45 + .../CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl | 116 ++ .../CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl | 172 +++ .../CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl | 268 +++++ .../PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl | 280 +++++ .../PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl | 266 +++++ .../PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl | 241 ++++ .../CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl | 799 +++++++++++++ .../NorthCluster/Include/PlatformBaseAddresses.h | 98 ++ .../NorthCluster/Include/Ppi/Capsule.h | 66 ++ .../NorthCluster/Include/Ppi/PlatformMemoryRange.h | 150 +++ .../NorthCluster/Include/Ppi/PlatformMemorySize.h | 52 + .../NorthCluster/Include/Ppi/SmmAccess.h | 171 +++ .../NorthCluster/Include/Ppi/VlvMmioPolicy.h | 45 + .../NorthCluster/Include/Ppi/VlvPeiInit.h | 41 + .../NorthCluster/Include/Ppi/VlvPolicy.h | 112 ++ .../NorthCluster/Include/Protocol/IgdOpRegion.h | 219 ++++ .../NorthCluster/Include/Protocol/MemInfo.h | 89 ++ .../Include/Protocol/PlatformGopPolicy.h | 73 ++ .../Include/Protocol/VlvPlatformPolicy.h | 111 ++ .../NorthCluster/Include/Valleyview.h | 61 + .../NorthCluster/Include/VlvAccess.h | 260 +++++ .../NorthCluster/Include/VlvCommonDefinitions.h | 258 +++++ .../SouthCluster/Include/Guid/PchInitVar.h | 54 + .../SouthCluster/Include/Guid/SataControllerGuid.h | 40 + .../SouthCluster/Include/Guid/SmbusArpMap.h | 36 + .../SouthCluster/Include/Guid/Vlv2Variable.h | 34 + .../SouthCluster/Include/IndustryStandard/CeAta.h | 132 +++ .../SouthCluster/Include/IndustryStandard/Mmc.h | 355 ++++++ .../SouthCluster/Include/IndustryStandard/SdCard.h | 163 +++ .../SouthCluster/Include/Library/I2CLib.h | 175 +++ .../SouthCluster/Include/Library/PchPlatformLib.h | 121 ++ .../SouthCluster/Include/PchAccess.h | 526 +++++++++ .../SouthCluster/Include/PchCommonDefinitions.h | 216 ++++ .../ValleyView2Soc/SouthCluster/Include/PchRegs.h | 211 ++++ .../SouthCluster/Include/PchRegs/PchRegsHda.h | 56 + .../SouthCluster/Include/PchRegs/PchRegsLpss.h | 492 ++++++++ .../SouthCluster/Include/PchRegs/PchRegsPcie.h | 89 ++ .../SouthCluster/Include/PchRegs/PchRegsPcu.h | 1205 ++++++++++++++++++++ .../SouthCluster/Include/PchRegs/PchRegsRcrb.h | 54 + .../SouthCluster/Include/PchRegs/PchRegsSata.h | 251 ++++ .../SouthCluster/Include/PchRegs/PchRegsScc.h | 59 + .../SouthCluster/Include/PchRegs/PchRegsSmbus.h | 155 +++ .../SouthCluster/Include/PchRegs/PchRegsSpi.h | 119 ++ .../SouthCluster/Include/PchRegs/PchRegsUsb.h | 98 ++ .../SouthCluster/Include/Ppi/PchInit.h | 81 ++ .../SouthCluster/Include/Ppi/PchPeiInit.h | 40 + .../SouthCluster/Include/Ppi/PchPlatformPolicy.h | 167 +++ .../SouthCluster/Include/Ppi/PchUsbPolicy.h | 75 ++ .../SouthCluster/Include/Ppi/PeiBlockIo.h | 236 ++++ .../ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h | 365 ++++++ .../SouthCluster/Include/Ppi/SmbusPolicy.h | 46 + .../ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h | 48 + .../SouthCluster/Include/Protocol/ActiveBios.h | 129 +++ .../Include/Protocol/ActiveBiosProtocol.h | 131 +++ .../Include/Protocol/DxePchPolicyUpdateProtocol.h | 57 + .../Include/Protocol/EmmcCardInfoProtocol.h | 48 + .../SouthCluster/Include/Protocol/Gpio.h | 167 +++ .../Include/Protocol/HwWatchdogTimer.h | 300 +++++ .../SouthCluster/Include/Protocol/I2cBus.h | 170 +++ .../Include/Protocol/PchExtendedReset.h | 90 ++ .../SouthCluster/Include/Protocol/PchInfo.h | 66 ++ .../Include/Protocol/PchPlatformPolicy.h | 556 +++++++++ .../SouthCluster/Include/Protocol/PchReset.h | 120 ++ .../SouthCluster/Include/Protocol/PchS3Support.h | 138 +++ .../SouthCluster/Include/Protocol/SdHostIo.h | 415 +++++++ .../Include/Protocol/SmbiosSlotPopulation.h | 53 + .../Include/Protocol/SmmIchnDispatchEx.h | 165 +++ .../SouthCluster/Include/Protocol/SmmSmbus.h | 45 + .../SouthCluster/Include/Protocol/Spi.h | 266 +++++ .../SouthCluster/Include/Protocol/TcoReset.h | 94 ++ .../ValleyView2Soc/SouthCluster/Include/Rsci.h | 34 + .../ValleyView2Soc/SouthCluster/Include/TianoApi.h | 67 ++ Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec | 121 ++ 120 files changed, 24499 insertions(+) create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl create mode 100644 Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl create mode 100644 Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h create mode 100644 Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h create mode 100644 Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec (limited to 'Vlv2DeviceRefCodePkg') diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL new file mode 100644 index 0000000000..ac13f36690 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL @@ -0,0 +1,623 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PARC,0x80,PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PBRC,0x80,PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PCRC,0x80,PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PDRC,0x80,PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PERC,0x80,PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PFRC,0x80,PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PGRC,0x80,PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PHRC,0x80,PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h new file mode 100644 index 0000000000..1f81d2586c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h @@ -0,0 +1,76 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + AcpiTablePlatform.h + + +Abstract: File contains platform specific ACPI defines for use in ACPI tables + + +--*/ +#ifndef _Platform_h_INCLUDED_ +#define _Platform_h_INCLUDED_ + +#ifdef ECP_FLAG +#include "EdkIIGlueDxe.h" +#endif +#include +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'O','E','M','I','D',' ' // OEMID 6 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000005 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('C','R','E','A') +#define EFI_ACPI_CREATOR_REVISION 0x0100000D +#define INT_MODEL 0x01 +#define PM_PROFILE EFI_ACPI_4_0_PM_PROFILE_MOBILE +#define SCI_INT_VECTOR 0x0009 +#define SMI_CMD_IO_PORT 0x000000B2 +#define ACPI_ENABLE 0x0A0 +#define ACPI_DISABLE 0x0A1 +#define S4BIOS_REQ 0x00 +#define PSTATE_CNT 0x00 +#define PM1a_EVT_BLK 0x00000400 +#define PM1b_EVT_BLK 0x00000000 +#define PM1a_CNT_BLK 0x00000404 +#define PM1b_CNT_BLK 0x00000000 +#define PM2_CNT_BLK 0x00000450 +#define PM_TMR_BLK 0x00000408 +#define GPE0_BLK 0x00000420 +#define GPE1_BLK 0x00000000 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x01 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x10 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 +#define CST_CNT 0x00 +#define P_LVL2_LAT 0x0064 +#define P_LVL3_LAT 0x01F4 +#define FLUSH_SIZE 0x0400 +#define FLUSH_STRIDE 0x0010 +#define DUTY_OFFSET 0x01 +#define DUTY_WIDTH 0x03 +#define DAY_ALRM 0x0D +#define MON_ALRM 0x00 +#define CENTURY 0x32 +#define FLAG ( EFI_ACPI_4_0_WBINVD | EFI_ACPI_4_0_SLP_BUTTON | EFI_ACPI_4_0_RESET_REG_SUP | EFI_ACPI_4_0_RTC_S4) +#define IAPC_BOOT_ARCH ( EFI_ACPI_4_0_VGA_NOT_PRESENT | EFI_ACPI_4_0_8042 | EFI_ACPI_4_0_LEGACY_DEVICES) +#define RESERVED 0x00 + +#endif diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf new file mode 100644 index 0000000000..c857ab8c9a --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf @@ -0,0 +1,44 @@ +## @file +# Component description file for PlatformAcpiTable module. +# +# Build acpi table data required by system boot. +# All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included +# by top level ASL file which will be dealed with by asl.exe application. +# +# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + +[sources.common] + DSDT.ASL + Facs/Facs.aslc + Facp/Facp.aslc + Madt/Madt30.aslc + Mcfg/Mcfg.aslc + Hpet/Hpet.aslc + Lpit/Lpit.aslc + + +[Packages] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl new file mode 100644 index 0000000000..9092ff87cc --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl @@ -0,0 +1,55 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + + +// NOTE: The _PDC Implementation is out of the scope of this +// reference code. Please see the latest Hyper-Threading Technology +// Reference Code for complete implementation details. + +Scope(\_PR) +{ + Processor(CPU0, // Unique name for Processor 0. + 1, // Unique ID for Processor 0. + 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h. + 0) // CPU0 P_BLK length = 6 bytes. + {} + + Processor(CPU1, // Unique name for Processor 1. + 2, // Unique ID for Processor 1. + 0x00, + 0) // CPU1 P_BLK length = 6 bytes. + {} + + Processor(CPU2, // Unique name for Processor 2. + 3, // Unique ID for Processor 2. + 0x00, + 0) // CPU2 P_BLK length = 6 bytes. + {} + + Processor(CPU3, // Unique name for Processor 3. + 4, // Unique ID for Processor 3. + 0x00, + 0) // CPU3 P_BLK length = 6 bytes. + {} +} // End _PR + + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL new file mode 100644 index 0000000000..56ed3372da --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL @@ -0,0 +1,81 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + "OEMID", // OEM ID (6 byte string) + "VLV-SOC", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + External(MDBG, MethodObj) + + Method(ADBG, 1, Serialized) + { + + If(CondRefOf(MDBG)) //check if SSDT is loaded + { + Return(MDBG(Arg0)) + } + + Return(0) + } + + +// Miscellaneous services enabled in Project + include ("token.asl") + include ("GloblNvs.asl") + include ("PciTree.asl") + include ("Pch.asl") + include ("Vlv.asl") + include ("CPU.asl") + include ("Platform.asl") + include ("THERMAL.ASL") + include ("PCI_DRC.ASL") + include ("Video.asl") + include ("Gpe.asl") + include ("IoTVirtualDevice.asl") + + // Sleep states supported by Chipset/Board. + // SSx - BIOS setup controlled enabled _Sx Sleep state status + // Values to be written to SLP_TYPE register are provided by SBACPI.SDL (South Bridge ACPI ModulePart) + + Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state + Name(\_S1, Package(4) {0x1,0x0,0,0}) + Name(\_S3, Package(4) {0x5,0x0,0,0}) + Name(\_S4, Package(4) {0x6,0x0,0,0}) + Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state + + Method(PTS, 1) // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE + { + If(Arg0) // entering any sleep state + { + } + } + Method(WAK, 1) // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP + { + } + +}// End of ASL File diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc new file mode 100644 index 0000000000..c9319d53ba --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc @@ -0,0 +1,194 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Facp.c + + +Abstract: The fixed ACPI description Table (FADT) Structure + + +--*/ +#ifdef ECP_FLAG +#include "EDKIIGlueDxe.h" +#else +#include +#endif +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = { + { + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98) + PM_PROFILE, // Preferred PM Profile + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + PSTATE_CNT, // PState control + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + CST_CNT, // _CST support + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag + RESERVED, // reserved + FLAG, + { + EFI_ACPI_5_0_SYSTEM_IO, + 8, + 0, + 0, + 0xCF9 + }, + 0x06, // Hardware reset value + 0, 0, 0, // Reserved + 0, // XFirmwareCtrl + 0, // XDsdt + // + // X_PM1a Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x20, + 0x00, + EFI_ACPI_3_0_DWORD, + PM1a_EVT_BLK, + + // + // X_PM1b Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + PM1b_EVT_BLK, + + // + // X_PM1a Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x10, + 0x00, + EFI_ACPI_3_0_WORD, + PM1a_CNT_BLK, + + // + // X_PM1b Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + PM1b_CNT_BLK, + + // + // X_PM2 Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_3_0_BYTE, + PM2_CNT_BLK, + + // + // X_PM Timer Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x20, + 0x00, + EFI_ACPI_3_0_DWORD, + PM_TMR_BLK, + + // + // X_General Purpose Event 0 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x80, + 0x00, + EFI_ACPI_RESERVED_BYTE, + GPE0_BLK, + + // + // X_General Purpose Event 1 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + GPE1_BLK, + + // + // Sleep Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_RESERVED_BYTE, + 0, + + // + // Sleep Status Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_RESERVED_BYTE, + 0, +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACP; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc new file mode 100644 index 0000000000..45050f0d3e --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc @@ -0,0 +1,90 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Ea815acpiFACS.c + + +Abstract: + + This file contains the FACS structure definition. + +--*/ + +// +// Statements that include other files +// +#ifdef ECP_FLAG +#include "EDKIIGlueDxe.h" +#else +#include +#endif +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), + + // + // Hardware Signature will be updated at runtime + // + 0x00000000, //HardwareSignature + 0x00000000, //FirmwareWakingVector + 0x00000000, //GlobalLock + 0x00000000, //Flags + 0x0000000000000000, //XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, + EFI_ACPI_RESERVED_BYTE, //Reserved0[3] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + 0x00000000, //OspmFlags + EFI_ACPI_RESERVED_BYTE, //Reserved1[24] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACS; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl new file mode 100644 index 0000000000..fffc8297c0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl @@ -0,0 +1,352 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + + +// Define a Global region of ACPI NVS Region that may be used for any +// type of implementation. The starting offset and size will be fixed +// up by the System BIOS during POST. Note that the Size must be a word +// in size to be fixed up correctly. + +OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) +Field(GNVS,AnyAcc,Lock,Preserve) +{ + Offset(0), // Miscellaneous Dynamic Registers: + OSYS, 16, // (00) Operating System + , 8, // (02) + , 8, // (03) + , 8, // (04) + , 8, // (05) + , 8, // (06) + , 8, // (07) + , 8, // (08) + , 8, // (09) + , 8, // (10) + P80D, 32, // (11) Port 80 Debug Port Value + LIDS, 8, // (15) Lid State (Lid Open = 1) + , 8, // (16) + , 8, // (17) + Offset(18), // Thermal Policy Registers: + , 8, // (18) + , 8, // (19) + ACTT, 8, // (20) Active Trip Point + PSVT, 8, // (21) Passive Trip Point + TC1V, 8, // (22) Passive Trip Point TC1 Value + TC2V, 8, // (23) Passive Trip Point TC2 Value + TSPV, 8, // (24) Passive Trip Point TSP Value + CRTT, 8, // (25) Critical Trip Point + DTSE, 8, // (26) Digital Thermal Sensor Enable + DTS1, 8, // (27) Digital Thermal Sensor 1 Reading + DTS2, 8, // (28) Digital Thermal Sensor 2 Reading + DTSF, 8, // (29) DTS SMI Function Call + Offset(30), // Battery Support Registers: + , 8, // (30) + , 8, // (31) + , 8, // (32) + , 8, // (33) + , 8, // (34) + , 8, // (35) + , 8, // (36) + Offset(40), // CPU Identification Registers: + APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1) + MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0 + , 8, // (42) + , 8, // (43) + , 8, // (44) + , 32, // (45) + Offset(50), // SIO CMOS Configuration Registers: + , 8, // (50) + , 8, // (51) + , 8, // (52) + , 8, // (53) + , 8, // (54) + , 8, // (55) + , 8, // (56) + , 8, // (57) + , 8, // (58) + Offset(60), // Internal Graphics Registers: + , 8, // (60) + , 8, // (61) + CADL, 8, // (62) Current Attached Device List + , 8, // (63) + CSTE, 16, // (64) Current Display State + NSTE, 16, // (66) Next Display State + , 16, // (68) + NDID, 8, // (70) Number of Valid Device IDs + DID1, 32, // (71) Device ID 1 + DID2, 32, // (75) Device ID 2 + DID3, 32, // (79) Device ID 3 + DID4, 32, // (83) Device ID 4 + DID5, 32, // (87) Device ID 5 + , 32, // (91) + , 8, // (95) Fifth byte of AKSV (mannufacturing mode) + Offset(103), // Backlight Control Registers: + , 8, // (103) + BRTL, 8, // (104) Brightness Level Percentage + Offset(105), // Ambiant Light Sensor Registers: + , 8, // (105) + , 8, // (106) + LLOW, 8, // (107) LUX Low Value + , 8, // (108) + Offset(110), // EMA Registers: + , 8, // (110) + , 16, // (111) + , 16, // (113) + Offset(116), // MEF Registers: + , 8, // (116) MEF Enable + Offset(117), // PCIe Dock: + , 8, // (117) + Offset(120), // TPM Registers: + , 8, // (120) + , 8, // (121) + , 8, // (122) + , 8, // (123) + , 32, // (124) + , 8, // (125) + , 8, // (129) + Offset(130), // + , 56, // (130) + , 56, // (137) + , 8, // (144) + , 56, // (145) + Offset(170), // IGD OpRegion/Software SCI base address + ASLB, 32, // (170) IGD OpRegion base address + Offset(174), // IGD OpRegion/Software SCI shared data + IBTT, 8, // (174) IGD Boot Display Device + IPAT, 8, // (175) IGD Panel Type CMOs option + ITVF, 8, // (176) IGD TV Format CMOS option + ITVM, 8, // (177) IGD TV Minor Format CMOS option + IPSC, 8, // (178) IGD Panel Scaling + IBLC, 8, // (179) IGD BLC Configuration + IBIA, 8, // (180) IGD BIA Configuration + ISSC, 8, // (181) IGD SSC Configuration + I409, 8, // (182) IGD 0409 Modified Settings Flag + I509, 8, // (183) IGD 0509 Modified Settings Flag + I609, 8, // (184) IGD 0609 Modified Settings Flag + I709, 8, // (185) IGD 0709 Modified Settings Flag + IDMM, 8, // (186) IGD DVMT Mode + IDMS, 8, // (187) IGD DVMT Memory Size + IF1E, 8, // (188) IGD Function 1 Enable + HVCO, 8, // (189) HPLL VCO + NXD1, 32, // (190) Next state DID1 for _DGS + NXD2, 32, // (194) Next state DID2 for _DGS + NXD3, 32, // (198) Next state DID3 for _DGS + NXD4, 32, // (202) Next state DID4 for _DGS + NXD5, 32, // (206) Next state DID5 for _DGS + NXD6, 32, // (210) Next state DID6 for _DGS + NXD7, 32, // (214) Next state DID7 for _DGS + NXD8, 32, // (218) Next state DID8 for _DGS + GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, // (223) IGD PAVP data + Offset(225), + OSCC, 8, // (225) PCIE OSC Control + NEXP, 8, // (226) Native PCIE Setup Value + Offset(235), // Global Variables + DSEN, 8, // (235) _DOS Display Support Flag. + ECON, 8, // (236) Embedded Controller Availability Flag. + GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag. + CTYP, 8, // (238) Global Cooling Type Flag. + L01C, 8, // (239) Global L01 Counter. + VFN0, 8, // (240) Virtual Fan0 Status. + VFN1, 8, // (241) Virtual Fan1 Status. + Offset(256), + NVGA, 32, // (256) NVIG opregion address + NVHA, 32, // (260) NVHM opregion address + AMDA, 32, // (264) AMDA opregion address + DID6, 32, // (268) Device ID 6 + DID7, 32, // (272) Device ID 7 + DID8, 32, // (276) Device ID 8 + Offset(332), + USEL, 8, // (332) UART Selection + PU1E, 8, // (333) PCU UART 1 Enabled + PU2E, 8, // (334) PCU UART 2 Enabled + + LPE0, 32, // (335) LPE Bar0 + LPE1, 32, // (339) LPE Bar1 + LPE2, 32, // (343) LPE Bar2 + + Offset(347), + , 8, // (347) + , 8, // (348) + PFLV, 8, // (349) Platform Flavor + + Offset(351), + ICNF, 8, // (351) ISCT / AOAC Configuration + XHCI, 8, // (352) xHCI controller mode + PMEN, 8, // (353) PMIC enable/disable + + LPEE, 8, // (354) LPE enable/disable + ISPA, 32, // (355) ISP Base Addr + ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3 + + offset(360), // ((4+8+6)*4+2)*4=296 + // + // Lpss controllers + // + PCIB, 32, + PCIT, 32, + D10A, 32, //DMA1 + D10L, 32, + D11A, 32, + D11L, 32, + P10A, 32, // PWM1 + P10L, 32, + P11A, 32, + P11L, 32, + P20A, 32, // PWM2 + P20L, 32, + P21A, 32, + P21L, 32, + U10A, 32, // UART1 + U10L, 32, + U11A, 32, + U11L, 32, + U20A, 32, // UART2 + U20L, 32, + U21A, 32, + U21L, 32, + SP0A, 32, // SPI + SP0L, 32, + SP1A, 32, + SP1L, 32, + + D20A, 32, //DMA2 + D20L, 32, + D21A, 32, + D21L, 32, + I10A, 32, // I2C1 + I10L, 32, + I11A, 32, + I11L, 32, + I20A, 32, // I2C2 + I20L, 32, + I21A, 32, + I21L, 32, + I30A, 32, // I2C3 + I30L, 32, + I31A, 32, + I31L, 32, + I40A, 32, // I2C4 + I40L, 32, + I41A, 32, + I41L, 32, + I50A, 32, // I2C5 + I50L, 32, + I51A, 32, + I51L, 32, + I60A, 32, // I2C6 + I60L, 32, + I61A, 32, + I61L, 32, + I70A, 32, // I2C7 + I70L, 32, + I71A, 32, + I71L, 32, + // + // Scc controllers + // + eM0A, 32, // EMMC + eM0L, 32, + eM1A, 32, + eM1L, 32, + SI0A, 32, // SDIO + SI0L, 32, + SI1A, 32, + SI1L, 32, + SD0A, 32, // SDCard + SD0L, 32, + SD1A, 32, + SD1L, 32, + MH0A, 32, // + MH0L, 32, + MH1A, 32, + MH1L, 32, + + offset(656), + SDRM, 8, + offset(657), + HLPS, 8, //(657) Hide Devices + offset(658), + OSEL, 8, //(658) OS Seletion - Windows/Android + + offset(659), // VLV1 DPTF + SDP1, 8, //(659) An enumerated value corresponding to SKU + DPTE, 8, //(660) DPTF Enable + THM0, 8, //(661) System Thermal 0 + THM1, 8, //(662) System Thermal 1 + THM2, 8, //(663) System Thermal 2 + THM3, 8, //(664) System Thermal 3 + THM4, 8, //(665) System Thermal 3 + CHGR, 8, //(666) DPTF Changer Device + DDSP, 8, //(667) DPTF Display Device + DSOC, 8, //(668) DPTF SoC device + DPSR, 8, //(669) DPTF Processor device + DPCT, 32, //(670) DPTF Processor participant critical temperature + DPPT, 32, //(674) DPTF Processor participant passive temperature + DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature + DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature + DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature + DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature + DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature + DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature + DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature + DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature + DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature + DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature + DLPM, 8, //(718) DPTF Current low power mode setting + DSC0, 32, //(719) DPTF Critical threshold0 for SCU + DSC1, 32, //(723) DPTF Critical threshold1 for SCU + DSC2, 32, //(727) DPTF Critical threshold2 for SCU + DSC3, 32, //(731) DPTF Critical threshold3 for SCU + DSC4, 32, //(735) DPTF Critical threshold3 for SCU + DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled + LPOE, 32, //(740) DPTF LPO Enable + LPPS, 32, //(744) P-State start index + LPST, 32, //(748) Step size + LPPC, 32, //(752) Power control setting + LPPF, 32, //(756) Performance control setting + DPME, 8, //(760) DPTF DPPM enable/disable + BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC + NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2 + PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode + TPMA, 32, //(764) + TPML, 32, //(768) + ITSA, 8, //(772) I2C Touch Screen Address + S0IX, 8, //(773) S0ix status + SDMD, 8, //(774) SDIO Mode + EMVR, 8, //(775) eMMC controller version + BMBD, 32, //(776) BM Bound + FSAS, 8, //(780) FSA Status + BDID, 8, //(781) Board ID + FBID, 8, //(782) FAB ID + OTGM, 8, //(783) OTG mode + STEP, 8, //(784) Stepping ID + WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test. + SOCS, 8, //(786) provide the SoC stepping infomation + AMTE, 8, //(787) Ambient Trip point change + UTS, 8, //(788) Enable Test Device connected to URT for WHCK test. + SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable + Offset(792), + EDPV, 8, //(792) Check for eDP display device + DIDX, 32, //(793) Device ID for eDP device + IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project. +} + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl new file mode 100644 index 0000000000..17535401fe --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl @@ -0,0 +1,105 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +// General Purpose Events. This Scope handles the Run-time and +// Wake-time SCIs. The specific method called will be determined by +// the _Lxx value, where xx equals the bit location in the General +// Purpose Event register(s). + +Scope(\_GPE) +{ + // + // Software GPE caused the event. + // + Method(_L02) + { + // Clear GPE status bit. + Store(0,GPEC) + // + // Handle DTS Thermal Events. + // + External(DTSE, IntObj) + If(CondRefOf(DTSE)) + { + If(LGreaterEqual(DTSE, 0x01)) + { + Notify(\_TZ.TZ01,0x80) + } + } + } + + // + // PUNIT SCI event. + // + Method(_L04) + { + // Clear the PUNIT Status Bit. + Store(1, PSCI) + } + + + // + // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC). + // + Method(_L05) + { + If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event? + { + \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI + } + } + + // + // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities + // on bus 0 asserts the equivalent of the PME# signal. + // + Method(_L0D, 0) + { + If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES)) + { + If(LNotEqual(OSEL, 1)) + { + Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status + Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME + } + Notify(\_SB.PCI0.EHC1, 0x02) + } + If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES)) + { + If(LNotEqual(OSEL, 1)) + { + Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status + Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME + } + Notify(\_SB.PCI0.XHC1, 0x02) + } + If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES)) + { + If(LNotEqual(OSEL, 1)) + { + Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status + Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME + } + Notify(\_SB.PCI0.HDEF, 0x02) + } + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL new file mode 100644 index 0000000000..587909b1e6 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL @@ -0,0 +1,353 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + HOST_BUS.ASL + +Abstract: + + Baytrail PCI configuration space definition. + +---*/ +Device(VLVC) +{ + Name(_ADR, 0x00000000) // Device 0, Function 0 + + // Define various MCH Controller PCI Configuration Space + // registers which will be used to dynamically produce all + // resources in the Host Bus _CRS. + OperationRegion(HBUS, PCI_Config, 0x00, 0xFF) + Field(HBUS, DWordAcc, NoLock, Preserve) + { + Offset(0xD0), + SMCR, 32, // VLV Message Control Register (0xD0) + Offset(0xD4), + SMDR, 32, // VLV Message Data Register (0xD4) + Offset(0xD8), + MCRX, 32, // VLV Message Control Register Extension (0xD8) + } + + // Define a method to read a 32-bit register on the VLV Message bus. + // Arg0 = Port + // Arg1 = Register + // + // Returns 32-bit register value + + Method(RMBR, 2, Serialized) + { + + // Initiate regsiter read message on VLV Message Bus MCR + + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(0x100000F0, Local0, SMCR) + + // Read register value from Message Data Register + + Return(SMDR) + } + + + // Define a method to write a 32-bit register on the VLV Message bus MDR. + // Arg0 = Port + // Arg1 = Register + // Arg2 = 32-bit value + + Method(WMBR, 3, Serialized) + { + + // Write register value to Message Data Register + + Store(Arg2, SMDR) + + // Initiate register write message on VLV Message Bus + + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(0x110000F0, Local0, SMCR) + } +} + +// +// BUS, I/O, and MMIO resources +// +Method(_CRS,0,Serialized) +{ + //Update ISP0 reserved memory + CreateDwordField(RES0, ^ISP0._MIN,ISMN) + CreateDwordField(RES0, ^ISP0._MAX,ISMX) + CreateDwordField(RES0, ^ISP0._LEN,ISLN) + If (LEqual(ISPD,1)) + { + Store (ISPA, ISMN) + Add (ISMN, ISLN, ISMX) + Subtract(ISMX, 1, ISMX) + } Else + { + Store (0, ISMN) + Store (0, ISMX) + Store (0, ISLN) + } + + //PCI MMIO SPACE + CreateDwordField(RES0, ^PM01._MIN,M1MN) + CreateDwordField(RES0, ^PM01._MAX,M1MX) + CreateDwordField(RES0, ^PM01._LEN,M1LN) + + //Get dBMBOUND Base + And(BMBD, 0xFF000000, M1MN) + + //Get ECBASE + Store(PCIT, M1MX) + Add(Subtract(M1MX, M1MN), 1, M1LN) + Subtract(M1MX, 1, M1MX) + + // Create pointers to Gfx Stolen Memory Sizing values. + CreateDwordField(RES0, ^STOM._MIN,GSMN) + CreateDwordField(RES0, ^STOM._MAX,GSMX) + CreateDwordField(RES0, ^STOM._LEN,GSLN) + + If (LNotEqual (\_SB.PCI0.GFX0.GSTM, 0xFFFFFFFF)) + { + Store(0x00, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C + } else + { + Store(\_SB.PCI0.GFX0.GSTM, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C + } + If (LNotEqual (\_SB.PCI0.GFX0.GUMA, 0xFFFFFFFF)) + { + Store(0x00, GSLN) //Read the Stolen memory base from B0:D2:F0:R5C + } else + { + ShiftLeft(\_SB.PCI0.GFX0.GUMA, 25, GSLN) //Read Stolen memory base form B0:D2:F0:R50 + } + Add(GSMN, GSLN, GSMX) //Store the Stolen Memory Size + Subtract(GSMX, 1, GSMX) + + Return(RES0) +} + +Name( RES0,ResourceTemplate() +{ + WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x00FF, // Max + 0x0000, // Translation + 0x0100 // Range Length = Max-Min+1 + ) + + IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + + WORDIO ( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x006F, // Max + 0x0000, // Translation + 0x0070 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0078, // Min + 0x0CF7, // Max + 0x0000, // Translation + 0x0C80 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0D00, // Min + 0xFFFF, // Max + 0x0000, // Translation + 0xF300 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy VGA video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Min + 0x000BFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy OptionRom + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000C0000, // Min + 0x000DFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for BIOS Area + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000E0000, // Min + 0x000FFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for ISP0 reserved Mem + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x7A000000, // Min + 0x7A3FFFFF, // Max + 0x00000000, // Translation + 0x00400000 // Range Length + ,,, + ISP0 + ) + + DWORDMEMORY ( // Descriptor for VGA Stolen Mem + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x7C000000, // Min + 0x7FFFFFFF, // Max + 0x00000000, // Translation + 0x04000000 // Range Length + ,,, + STOM + ) + + DWORDMEMORY ( // Descriptor for PCI MMIO + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min + 0xDFFFFFFF, // Max + 0x00000000, // Translation + 0x60000000 // Range Length + ,,, + PM01 + ) +}) + +//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) +Name(GUID,Buffer() +{ + 0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66 +}) + + +Name(SUPP,0) // PCI _OSC Support Field value +Name(CTRL,0) // PCI _OSC Control Field value + +Method(_OSC,4,Serialized) +{ + // Check for proper UUID + // Save the capabilities buffer + Store(Arg3,Local0) + + // Create DWord-adressable fields from the Capabilties Buffer + CreateDWordField(Local0,0,CDW1) + CreateDWordField(Local0,4,CDW2) + CreateDWordField(Local0,8,CDW3) + + // Check for proper UUID + If(LAnd(LEqual(Arg0,GUID),NEXP)) + { + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + If(Not(And(CDW1,1))) // Query flag clear? + { + // Disable GPEs for features granted native control. + If(And(CTRL,0x02)) + { + NHPG() + } + If(And(CTRL,0x04)) // PME control granted? + { + NPME() + } + } + + If(LNotEqual(Arg1,One)) + { + // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) + { + // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + And(CTRL,0xfe,CTRL) + Store(CTRL,CDW3) + Store(CTRL,OSCC) + Return(Local0) + } Else + { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc new file mode 100644 index 0000000000..d3988cadf5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc @@ -0,0 +1,69 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Hpet.c + +Abstract: + + This file contains a structure definition for the ACPI HPET Table. +--*/ + +// +// Statements that include other files +// +#ifdef ECP_FLAG +#include +#endif +#include +#include "AcpiTablePlatform.h" + +// Hpet Table +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = { + { + EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0x0, // EventTimerBlockId + { + 0x00, // Address_Space_ID = System Memory + 0x40, // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS + 0x00, // Register_Bit_offset + 0x00, // Dword access + HPET_BASE_ADDRESS, // Base addresse of HPET + }, + 0x0, // Only HPET's _UID in Namespace + MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS, + 0x0 +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&HPET; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL new file mode 100644 index 0000000000..c8f663a847 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL @@ -0,0 +1,885 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + INTELGFX.ASL + +Abstract: + + IGD OpRegion/Software ACPI Reference Code for the Baytrail Family. + +--*/ + +// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will +// get called during initialization to prepare for an ACPI Display +// Switch Event. During an ACPI Display Switch, the OS will call +// _DOS = 2 immediately after a Notify=0x80 to temporarily disable +// all Display Switching. After ACPI Display Switching is complete, +// the OS will call _DOS = 0 to re-enable ACPI Display Switching. + +Method(_DOS,1) +{ + // Store Display Switching and LCD brightness BIOS control bit + Store(And(Arg0,7),DSEN) +} + +// Enumerate the Display Environment. This method will return +// valid addresses for all display device encoders present in the +// system. The Miniport Driver will reject the addresses for every +// encoder that does not have an attached display device. After +// enumeration is complete, the OS will call the _DGS methods +// during a display switch only for the addresses accepted by the +// Miniport Driver. For hot-insertion and removal of display +// devices, a re-enumeration notification will be required so the +// address of the newly present display device will be accepted by +// the Miniport Driver. + +Method(_DOD, 0, Serialized) +{ + Store(0, NDID) + If(LNotEqual(DIDL, Zero)) + { + Store(SDDL(DIDL),DID1) + } + If(LNotEqual(DDL2, Zero)) + { + Store(SDDL(DDL2),DID2) + } + If(LNotEqual(DDL3, Zero)) + { + Store(SDDL(DDL3),DID3) + } + If(LNotEqual(DDL4, Zero)) + { + Store(SDDL(DDL4),DID4) + } + If(LNotEqual(DDL5, Zero)) + { + Store(SDDL(DDL5),DID5) + } + + // TODO - This level of flexibility is not needed for a true + // OEM design. Simply determine the greatest number of + // encoders the platform will suppport then remove all + // return packages beyond that value. Note that for + // current silicon, the maximum number of encoders + // possible is 5. + + If(LEqual(NDID,1)) + { + If (LNOTEqual (ISPD, 0)) + { + Name(TMP0,Package() {0xFFFFFFFF,0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP0,0)) + //Add ISP device to GFX0 + Store(0x00020F38, Index(TMP0,1)) + Return(TMP0) + } Else + { + Name(TMP1,Package() {0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP1,0)) + Return(TMP1) + } + } + + If(LEqual(NDID,2)) + { + If (LNOTEqual (ISPD, 0)) + { + Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP2,0)) + Store(Or(0x10000,DID2),Index(TMP2,1)) + //Add ISP device to GFX0 + Store(0x00020F38, Index(TMP2,2)) + Return(TMP2) + } Else + { + Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + Return(TMP3) + } + } + + If(LEqual(NDID,3)) + { + If (LNOTEqual (ISPD, 0)) + { + Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + //Add ISP device to GFX0 + Store(0x00020F38, Index(TMP4,3)) + Return(TMP4) + } Else + { + Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Return(TMP5) + } + } + + If(LEqual(NDID,4)) + { + If (LNOTEqual (ISPD, 0)) + { + Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + //Add ISP device to GFX0 + Store(0x00020F38, Index(TMP6,4)) + Return(TMP6) + } Else + { + Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Return(TMP7) + } + } + + If(LGreater(NDID,4)) + { + If (LNOTEqual (ISPD, 0)) + { + Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + //Add ISP device to GFX0 + Store(0x00020F38, Index(TMP8,5)) + Return(TMP8) + } Else + { + Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP9,0)) + Store(Or(0x10000,DID2),Index(TMP9,1)) + Store(Or(0x10000,DID3),Index(TMP9,2)) + Store(Or(0x10000,DID4),Index(TMP9,3)) + Store(Or(0x10000,DID5),Index(TMP9,4)) + Return(TMP9) + } + } + + // If nothing else, return Unknown LFP. + // (Prevents compiler warning.) + + //Add ISP device to GFX0 + If (LNOTEqual (ISPD, 0)) + { + Return(Package() {0x00000400, 0x00020F38}) + } Else + { + Return(Package() {0x00000400}) + } +} + +Device(DD01) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID1),0x400)) + { + Store(0x1, EDPV) + Store(DID1, DIDX) + Return(1) + } + If(LEqual(DID1,0)) + { + Return(1) + } + Else + { + Return(And(0xFFFF,DID1)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID1)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID1)) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + +Device(DD02) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID2),0x400)) + { + Store(0x2, EDPV) + Store(DID2, DIDX) + Return(2) + } + If(LEqual(DID2,0)) + { + Return(2) + } + Else + { + Return(And(0xFFFF,DID2)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID2)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + // Return the Next State. + Return(NDDS(DID2)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + +Device(DD03) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID3),0x400)) + { + Store(0x3, EDPV) + Store(DID3, DIDX) + Return(3) + } + If(LEqual(DID3,0)) + { + Return(3) + } + Else + { + Return(And(0xFFFF,DID3)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID3,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID3)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID3)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + +Device(DD04) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID4),0x400)) + { + Store(0x4, EDPV) + Store(DID4, DIDX) + Return(4) + } + If(LEqual(DID4,0)) + { + Return(4) + } + Else + { + Return(And(0xFFFF,DID4)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID4,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID4)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID4)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + + +Device(DD05) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID5),0x400)) + { + Store(0x5, EDPV) + Store(DID5, DIDX) + Return(5) + } + If(LEqual(DID5,0)) + { + Return(5) + } + Else + { + Return(And(0xFFFF,DID5)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID5,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID5)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID5)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + + +Device(DD06) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID6),0x400)) + { + Store(0x6, EDPV) + Store(DID6, DIDX) + Return(6) + } + If(LEqual(DID6,0)) + { + Return(6) + } + Else + { + Return(And(0xFFFF,DID6)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID6,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID6)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID6)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + + +Device(DD07) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID7),0x400)) + { + Store(0x7, EDPV) + Store(DID7, DIDX) + Return(7) + } + If(LEqual(DID7,0)) + { + Return(7) + } + Else + { + Return(And(0xFFFF,DID7)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID7,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID7)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID7)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + + +Device(DD08) +{ + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID8),0x400)) + { + Store(0x8, EDPV) + Store(DID8, DIDX) + Return(8) + } + If(LEqual(DID8,0)) + { + Return(8) + } + Else + { + Return(And(0xFFFF,DID8)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID8,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID8)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID8)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } +} + +//device for eDP +Device(DD1F) +{ + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x1F) + } + Else + { + Return(And(0xFFFF,DIDX)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x00) + } + Else + { + Return(CDDS(DIDX)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DIDX)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + // Query List of Brightness Control Levels Supported. + + Method(_BCL,0) + { + // List of supported brightness levels in the following sequence. + + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + Return(Package() {80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) + } + + // Set the Brightness Level. + + Method (_BCM,1) + { + // Set the requested level if it is between 0 and 100%. + + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) + { + \_SB.PCI0.GFX0.AINT(1, Arg0) + Store(Arg0,BRTL) // Store Brightness Level. + } + } + + // Brightness Query Current level. + + Method (_BQC,0) + { + Return(BRTL) + } +} + +Method(SDDL,1) +{ + Increment(NDID) + Store(And(Arg0,0xF0F),Local0) + Or(0x80000000,Local0, Local1) + If(LEqual(DIDL,Local0)) + { + Return(Local1) + } + If(LEqual(DDL2,Local0)) + { + Return(Local1) + } + If(LEqual(DDL3,Local0)) + { + Return(Local1) + } + If(LEqual(DDL4,Local0)) + { + Return(Local1) + } + If(LEqual(DDL5,Local0)) + { + Return(Local1) + } + If(LEqual(DDL6,Local0)) + { + Return(Local1) + } + If(LEqual(DDL7,Local0)) + { + Return(Local1) + } + If(LEqual(DDL8,Local0)) + { + Return(Local1) + } + Return(0) +} + +Method(CDDS,1) +{ + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0x1D) + } + If(LEqual(CADL, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL2, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL3, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL4, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL5, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL6, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL7, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL8, Local0)) + { + Return(0x1F) + } + Return(0x1D) +} + +Method(NDDS,1) +{ + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0) + } + If(LEqual(NADL, Local0)) + { + Return(1) + } + If(LEqual(NDL2, Local0)) + { + Return(1) + } + If(LEqual(NDL3, Local0)) + { + Return(1) + } + If(LEqual(NDL4, Local0)) + { + Return(1) + } + If(LEqual(NDL5, Local0)) + { + Return(1) + } + If(LEqual(NDL6, Local0)) + { + Return(1) + } + If(LEqual(NDL7, Local0)) + { + Return(1) + } + If(LEqual(NDL8, Local0)) + { + Return(1) + } + Return(0) +} + +// +// Include IGD OpRegion/Software SCI interrupt handler which is use by +// the graphics drivers to request data from system BIOS. +// +include("IgdOpRn.ASL") diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL new file mode 100644 index 0000000000..280d6cb3d3 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL @@ -0,0 +1,77 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + INTELISPDev2.ASL + +Abstract: + + ISP Exist as B0D2F0 Software ACPI Reference Code for the Baytrail Family. + +--*/ +////Device ISP0 +Device(ISP0) +{ + Name(_ADR, 0x0F38) + //Name (_HID, "80860F38") + //Name (_CID, "80860F38") + Name(_DDN, "VLV2 ISP - 80860F38") + Name(_UID, 0x01) + + Method (_STA, 0, NotSerialized) + { + If(LEqual(ISPD,1)) //Dev2 need report ISP0 as GFX0 child + { + Return (0xF) + } + Else + { + Return (0x0) + } + } + Name(SBUF,ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0) + }) + Method(_CRS, 0x0, NotSerialized) + { + Return (SBUF) + } + Method (_SRS, 0x1, NotSerialized) + { + } + Method (_DIS, 0x0, NotSerialized) + { + } + Method(_DSM, 0x4, NotSerialized) + { + If (LEqual (Arg0, 0x01)) + { + ///Switch ISP to D3H + Return (0x01) + } + Elseif (LEqual (Arg0, 0x02)) + { + //Switch ISP to D0 + Return (0x02) + } + Else + { + //Do nothing + Return (0x0F) + } + } +} ///End ISP0 + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL new file mode 100644 index 0000000000..d4e735e3e6 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL @@ -0,0 +1,161 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + IgdOGBDA.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code for the Baytrail Family. + This file contains Get BIOS Data Area funciton support for + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +Method (GBDA, 0, Serialized) +{ + + // Supported calls: Sub-function 0 + + If (LEqual(GESF, 0)) + { + // Update implementation specific supported calls. Reference + // code is set to Intel's validated implementation. + + Store(0x0000279, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Requested callbacks: Sub-function 1 + + If (LEqual(GESF, 1)) + { + + // Update implementation specific system BIOS requested call + // back functions. Call back functions are where the driver calls the + // system BIOS at function indicated event. + + Store(0x00000240, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Get Boot display Preferences: Sub-function 4 + + If (LEqual(GESF, 4)) + { + + // Update the implementation specific Get Boot Display + // Preferences function. + + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) + Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Panel details: Sub-function 5 + + If (LEqual(GESF, 5)) + { + + // Update the implementation specific Get Panel Details + // function. + + Store(IPSC, PARM) // Report the scaling setting + Or(PARM, ShiftLeft(IPAT, 8), PARM) + Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown + Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting + Store(Zero, GESF) + Return(SUCC) + } + + // TV-standard/Video-connector: Sub-function 6 + + If (LEqual(GESF, 6)) + { + + // Update the implementation specific Get + // TV-standard/Video-connectorPanel function. + + Store(ITVF, PARM) + Or(PARM, ShiftLeft(ITVM, 4), PARM) + Store(Zero, GESF) + Return(SUCC) + } + + // Internal graphics: Sub-function 7 + + If (LEqual(GESF, 7)) + { + Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA) + Xor(PARM, 1, PARM) // Invert the VGA mode polarity + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1 + // PARM[3:2] - Reserved + // PARM[4] - IGD D3 support(0=cold) + // PARM[10:5] - Reserved + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size + + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This means + // that the flag must be set to indicate that system BIOS requests + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent calls to + // this function. + + // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING [MMADR+0x20C8] + + Or(ShiftLeft(Derefof(Index(CDCT, \_SB.PCI0.GFX0.MCHK.DCFE)), 21),PARM, PARM) + + Store(1, GESF) // Set the modified settings flag + Return(SUCC) + } + + // Spread spectrum clocks: Sub-function 10 + + If (LEqual(GESF, 10)) + { + + Store(0, PARM) // Assume SSC is disabled + + If(ISSC) + { + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled + } + + Store(0, GESF) // Set the modified settings flag + Return(SUCC) // Success + } + + + // A call to a reserved "Get BIOS data" function was received. + + Store(Zero, GESF) // Clear the exit parameter + Return(CRIT) // Reserved, "Critical failure" +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL new file mode 100644 index 0000000000..927e43d585 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL @@ -0,0 +1,491 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + IgdOMOBF.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code for the Baytrail Family. + This file contains ASL code with the purpose of handling events + i.e. hotkeys and other system interrupts. + +--*/ + + +// Notes: +// 1. The following routines are to be called from the appropriate event +// handlers. +// 2. This code cannot comprehend the exact implementation in the OEM's BIOS. +// Therefore, an OEM must call these methods from the existing event +// handler infrastructure. Details on when/why to call each method is +// included in the method header under the "usage" section. + + +/************************************************************************; +;* ACPI Notification Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PDRD +;* +;* Description: Check if the graphics driver is ready to process +;* notifications and video extensions. +;* +;* Usage: This method is to be called prior to performing any +;* notifications or handling video extensions. +;* Ex: If (PDRD()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: DRDY (Driver ready status), ASLP (Driver recommended +;* sleep timeout value). +;* +;************************************************************************/ + +Method(PDRD) +{ + If(LNot(DRDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If DRDY is clear, the driver is not ready. If the return value is + // !=0, do not perform any notifications or video extension handling. + + Return(LNot(DRDY)) +} + + +/************************************************************************; +;* +;* Name: PSTS +;* +;* Description: Check if the graphics driver has completed the previous +;* "notify" command. +;* +;* Usage: This method is called before every "notify" command. A +;* "notify" should only be set if the driver has completed the +;* previous command. Else, ignore the event and exit the parent +;* method. +;* Ex: If (PSTS()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: CSTS (Notification status), ASLP (Driver recommended sleep +;* timeout value). +;* +;************************************************************************/ + +Method(PSTS) +{ + If(LGreater(CSTS, 2)) + { + // Sleep for ASLP milliseconds if the status is not "success, + // failure, or pending" + // + Sleep(ASLP) + } + + Return(LEqual(CSTS, 3)) // Return True if still Dispatched +} + + +/************************************************************************; +;* +;* Name: GNOT +;* +;* Description: Call the appropriate methods to query the graphics driver +;* status. If all methods return success, do a notification of +;* the graphics device. +;* +;* Usage: This method is to be called when a graphics device +;* notification is required (display switch hotkey, etc). +;* +;* Input: Arg0 = Current event type: +;* 1 = display switch +;* 2 = lid +;* 3 = dock +;* Arg1 = Notification type: +;* 0 = Re-enumeration +;* 0x80 = Display switch +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PDRD and PSTS methods. OSYS (OS version) +;* +;************************************************************************/ + +Method(GNOT, 2) +{ + // Check for 1. Driver loaded, 2. Driver ready. + // If any of these cases is not met, skip this event and return failure. + // + If(PDRD()) + { + Return(0x1) // Return failure if driver not loaded. + } + + Store(Arg0, CEVT) // Set up the current event value + Store(3, CSTS) // CSTS=BIOS dispatched an event + + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug + { + If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006))) + { + // + // WINXP requires that the entire PCI Bridge be re-enumerated. + // + Notify(\_SB.PCI0, Arg1) + } + Else + { + // + // Re-enumerate the Graphics Device for non-XP operating systems. + // + Notify(\_SB.PCI0.GFX0, Arg1) + } + } + + Notify(\_SB.PCI0.GFX0,0x80) + + + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: GHDS +;* +;* Description: Handle a hotkey display switching event (performs a +;* Notify(GFX0, 0). +;* +;* Usage: This method must be called when a hotkey event occurs and the +;* purpose of that hotkey is to do a display switch. +;* +;* Input: Arg0 = Toggle table number. +;* +;* Output: Returns 0 = success, 1 = failure. +;* CEVT and TIDX are indirect outputs. +;* +;* References: TIDX, GNOT +;* +;************************************************************************/ + +Method(GHDS, 1) +{ + Store(Arg0, TIDX) // Store the table number + + // Call GNOT for CEVT = 1 = hotkey, notify value = 0 + + Return(GNOT(1, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GLID +;* +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the +;* lid notify). +;* +;* Usage: This method must be called when a lid event occurs. A +;* Notify(LID0, 0x80) must follow the call to this method. +;* +;* Input: Arg0 = Lid state: +;* 0 = All closed +;* 1 = internal LFP lid open +;* 2 = external lid open +;* 3 = both external and internal open +;* +;* Output: Returns 0=success, 1=failure. +;* CLID and CEVT are indirect outputs. +;* +;* References: CLID, GNOT +;* +;************************************************************************/ + +Method(GLID, 1) +{ + Store(Arg0, CLID) // Store the current lid state + + // Call GNOT for CEVT=2=Lid, notify value = 0 + + Return(GNOT(2, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GDCK +;* +;* Description: Handle a docking event by updating the current docking status +;* and doing a notification. +;* +;* Usage: This method must be called when a docking event occurs. +;* +;* Input: Arg0 = Docking state: +;* 0 = Undocked +;* 1 = Docked +;* +;* Output: Returns 0=success, 1=failure. +;* CDCK and CEVT are indirect outputs. +;* +;* References: CDCK, GNOT +;* +;************************************************************************/ + +Method(GDCK, 1) +{ + Store(Arg0, CDCK) // Store the current dock state + + // Call GNOT for CEVT=4=Dock, notify value = 0 + + Return(GNOT(4, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* ASLE Interrupt Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PARD +;* +;* Description: Check if the driver is ready to handle ASLE interrupts +;* generate by the system BIOS. +;* +;* Usage: This method must be called before generating each ASLE +;* interrupt. +;* +;* Input: None +;* +;* Output: Returns 0 = success, 1 = failure. +;* +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep +;* timeout value) +;* +;************************************************************************/ + +Method(PARD) +{ + If(LNot(ARDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If ARDY is clear, the driver is not ready. If the return value is + // !=0, do not generate the ASLE interrupt. + + Return(LNot(ARDY)) +} + + +/************************************************************************; +;* +;* Name: AINT +;* +;* Description: Call the appropriate methods to generate an ASLE interrupt. +;* This process includes ensuring the graphics driver is ready +;* to process the interrupt, ensuring the driver supports the +;* interrupt of interest, and passing information about the event +;* to the graphics driver. +;* +;* Usage: This method must called to generate an ASLE interrupt. +;* +;* Input: Arg0 = ASLE command function code: +;* 0 = Set ALS illuminance +;* 1 = Set backlight brightness +;* 2 = Do Panel Fitting +;* Arg1 = If Arg0 = 0, current ALS reading: +;* 0 = Reading below sensor range +;* 1-0xFFFE = Current sensor reading +;* 0xFFFF = Reading above sensor range +;* Arg1 = If Arg0 = 1, requested backlight percentage +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PARD method. +;* +;************************************************************************/ + +Method(AINT, 2) +{ + + // Return failure if the requested feature is not supported by the + // driver. + + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) + { + Return(0x1) + } + + // Return failure if the driver is not ready to handle an ASLE + // interrupt. + + If(PARD()) + { + Return(0x1) + } + + // Evaluate the first argument (Panel fitting, backlight brightness, or ALS). + + If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change. + { + If(CPFM) // If current mode field is non-zero use it. + { + And(CPFM, 0x0F, Local0) // Create variables without reserved + And(EPFM, 0x0F, Local1) // or valid bits. + + If(LEqual(Local0, 1)) // If current mode is centered, + { + If(And(Local1, 6)) // and if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Otherwise, + { + If(And(Local1, 8)) // if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Only centered mode is enabled + { + Store(1, PFIT) // so request centered. (No change.) + } + } + } + If(LEqual(Local0, 6)) // If current mode is stretched, + { + If(And(Local1, 8)) // and if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Otherwise, + { + If(And(Local1, 1)) // if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Only stretched mode is enabled + { + Store(6, PFIT) // so request stretched. (No change.) + } + } + } + If(LEqual(Local0, 8)) // If current mode is aspect ratio, + { + If(And(Local1, 1)) // and if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Otherwise, + { + If(And(Local1, 6)) // if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Only aspect ratio mode is enabled + { + Store(8, PFIT) // so request aspect ratio. (No change.) + } + } + } + } + + // The following code for panel fitting (within the Else condition) is retained for backward compatiblity. + + Else // If CFPM field is zero use PFIT and toggle the + { + Xor(PFIT,7,PFIT) // mode setting between stretched and centered only. + } + + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. + + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness. + { + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255. + + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. + + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace + { + Store(Arg1, ALSI) + + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] + } + Else + { + Return(0x1) // Unsupported function + } + } + } + + Store(0x01, ASLE) // Generate ASLE interrupt + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: SCIP +;* +;* Description: Checks the presence of the OpRegion and SCI +;* +;* Usage: This method is called before other OpRegion methods. The +;* former "GSMI True/False is not always valid. This method +;* checks if the OpRegion Version is non-zero and if non-zero, +;* (present and readable) then checks the GSMI flag. +;* +;* Input: None +;* +;* Output: Boolean True = SCI present. +;* +;* References: None +;* +;************************************************************************/ + +Method(SCIP) +{ + If(LNotEqual(OVER,0)) // If OpRegion Version not 0. + { + Return(LNot(GSMI)) // Return True if SCI. + } + + Return(0) // Else Return False. +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL new file mode 100644 index 0000000000..418329dce0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL @@ -0,0 +1,280 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + IgdOSBCB.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code for the Baytrail Family. + This file contains the system BIOS call back functionality for the + OpRegion/Software SCI mechanism. + +--*/ + + +Method (SBCB, 0, Serialized) +{ + + // Supported Callbacks: Sub-function 0 + + If (LEqual(GESF, 0x0)) + { + + // An OEM may support the driver->SBIOS status callbacks, but + // the supported callbacks value must be modified. The code that is + // executed upon reception of the callbacks must be also be updated + // to perform the desired functionality. + + Store(0x00000000, PARM) // No callbacks supported + + If(LEqual(PFLV,FMBL)) + { + Store(0x000F87FD, PARM) // Mobile + } + If(LEqual(PFLV,FDTP)) + { + Store(0x000F87BD, PARM) // Desktop + } + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // "Success" + } + + // BIOS POST Completion: Sub-function 1 + + If (LEqual(GESF, 1)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Pre-Hires Set Mode: Sub-function 3 + + If (LEqual(GESF, 3)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Post-Hires Set Mode: Sub-function 4 + + If (LEqual(GESF, 4)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Switch: Sub-function 5 + + If (LEqual(GESF, 5)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set TV format: Sub-function 6 + + If (LEqual(GESF, 6)) + { + + // If implemented, the input values must be saved into + // non-volatile storage for parsing during the next boot. The + // following Sample code is Intel validated implementation. + + Store(And(PARM, 0x0F), ITVF) + Store(ShiftRight(And(PARM, 0xF0), 4), ITVM) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) + } + + // Adapter Power State: Sub-function 7 + + If (LEqual(GESF, 7)) + { + + // Upon notification from driver that the Adapter Power State = D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + If(LEqual(PARM, 0)) + { + Store(CLID, Local0) + If(And(0x80000000,Local0)) + { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Power State: Sub-function 8 + + If (LEqual(GESF, 8)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set Boot Display: Sub-function 9 + + If (LEqual(GESF, 9)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(PARM, 0xFF, IBTT) // Save the boot display to NVS + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Reserved, "Critical failure" + } + + // Set Panel Details: Sub-function 10 (0Ah) + + If (LEqual(GESF, 10)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + // Set the panel-related NVRAM variables based the input from the driver. + + And(PARM, 0xFF, IPSC) + + // Change panel type if a change is requested by the driver (Change if + // panel type input is non-zero). Zero=No change requested. + + If(And(ShiftRight(PARM, 8), 0xFF)) + { + And(ShiftRight(PARM, 8), 0xFF, IPAT) + Decrement(IPAT) // 0 = no change, so fit to CMOS map + } + And(ShiftRight(PARM, 18), 0x3, IBLC) + And(ShiftRight(PARM, 20), 0x7, IBIA) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Set Internal Graphics: Sub-function 11 (0Bh) + + If (LEqual(GESF, 11)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option + + // Fixed memory/DVMT memory + + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program DVMT/fixed memory size + + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post-Hires to DOS FS: Sub-function 16 (10h) + + If (LEqual(GESF, 16)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // APM Complete: Sub-function 17 (11h) + + If (LEqual(GESF, 17)) + { + + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Not supported, but no failure + } + + // Set Spread Spectrum Clocks: Sub-function 18 (12h) + + If (LEqual(GESF, 18)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + If(And(PARM, 1)) + { + If(LEqual(ShiftRight(PARM, 1), 1)) + { + Store(1, ISSC) // Enable HW SSC, only for clock 1 + } + Else + { + Store(Zero, GESF) + Return(CRIT) // Failure, as the SSC clock must be 1 + } + } + Else + { + Store(0, ISSC) // Disable SSC + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post VBE/PM Callback: Sub-function 19 (13h) + + If (LEqual(GESF, 19)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set PAVP Data: Sub-function 20 (14h) + + If (LEqual(GESF, 20)) + { + And(PARM, 0xF, PAVP) // Store PAVP info + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // A call to a reserved "System BIOS callbacks" function was received + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Reserved, "Critical failure" +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL new file mode 100644 index 0000000000..65190af2c5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL @@ -0,0 +1,305 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + IgdOpRn.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code for the Baytrail Family. + This file contains the interrupt handler code for the Integrated + Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +//NOTES: +// +// (1) The code contained in this file inherits the scope in which it +// was included. So BIOS developers must be sure to include this +// file in the scope associated with the graphics device +// (ex. \_SB.PCI0.GFX0). +// (2) Create a _L06 method under the GPE scope to handle the event +// generated by the graphics driver. The _L06 method must call +// the GSCI method in this file. +// (3) The MCHP operation region assumes that _ADR and _BBN names +// corresponding to bus 0, device0, function 0 have been declared +// under the PCI0 scope. +// (4) Before the first execution of the GSCI method, the base address +// of the GMCH SCI OpRegion must be programmed where the driver can +// access it. A 32bit scratch register at 0xFC in the IGD PCI +// configuration space (B0/D2/F0/R0FCh) is used for this purpose. + +// Define an OperationRegion to cover the GMCH PCI configuration space as +// described in the IGD OpRegion specificiation. + +// Define an OperationRegion to cover the IGD PCI configuration space as +// described in the IGD OpRegion specificiation. + +OperationRegion(IGDP, PCI_Config,0x00,0x100) +Field(IGDP, AnyAcc, NoLock, Preserve) +{ + Offset(0x10), // GTTMMADR + MADR, 32, + Offset(0x50), // GMCH Graphics Control Register + , 1, + GIVD, 1, // IGD VGA disable bit + , 1, + GUMA, 5, // Stolen memory size + , 8, + Offset(0x54), + , 4, + GMFN, 1, // Gfx function 1 enable + , 27, + Offset(0x5C), // Stolen Memory Base Address + GSTM, 32, + Offset(0xE0), // Reg 0xE8, SWSCI control register + GSSE, 1, // Graphics SCI event (1=event pending) + GSSB, 14, // Graphics SCI scratchpad bits + GSES, 1, // Graphics event select (1=SCI) + Offset(0xE4), + ASLE, 8, // Reg 0xE4, ASLE interrupt register + , 24, // Only use first byte of ASLE reg + Offset(0xFC), + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion +} + +Method (MCHK, 0, Serialized) +{ + + If (LNotEqual (MADR, 0xFFFFFFFF)) + { + OperationRegion(IGMM,SystemMemory,MADR,0x3000) + Field(IGMM,AnyAcc, NoLock, Preserve) + { + Offset(0X20C8), + , 4, + DCFE, 4, // DISPLAY_CLOCK_FREQUENCY_ENCODING + } + } +} + + +// Define an OperationRegion to cover the IGD OpRegion layout. + +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) +Field(IGDM, AnyAcc, NoLock, Preserve) +{ + + // OpRegion Header + + SIGN, 128, // Signature-"IntelGraphicsMem" + SIZE, 32, // OpRegion Size + OVER, 32, // OpRegion Version + SVER, 256, // System BIOS Version + VVER, 128, // VBIOS Version + GVER, 128, // Driver version + MBOX, 32, // Mailboxes supported + DMOD, 32, // Driver Model + PCON, 32, // 96, Platform Configuration + + // OpRegion Mailbox 1 (Public ACPI Methods) + // Note: Mailbox 1 is normally reserved for desktop platforms. + + Offset(0x100), + DRDY, 32, // Driver readiness (ACPI notification) + CSTS, 32, // Notification status + CEVT, 32, // Current event + Offset(0x120), + DIDL, 32, // Supported display device ID list + DDL2, 32, // Allows for 8 devices + DDL3, 32, + DDL4, 32, + DDL5, 32, + DDL6, 32, + DDL7, 32, + DDL8, 32, + CPDL, 32, // Currently present display list + CPL2, 32, // Allows for 8 devices + CPL3, 32, + CPL4, 32, + CPL5, 32, + CPL6, 32, + CPL7, 32, + CPL8, 32, + CAD1, 32, // Currently active display list + CAL2, 32, // Allows for 8 devices + CAL3, 32, + CAL4, 32, + CAL5, 32, + CAL6, 32, + CAL7, 32, + CAL8, 32, + NADL, 32, // Next active display list + NDL2, 32, // Allows for 8 devices + NDL3, 32, + NDL4, 32, + NDL5, 32, + NDL6, 32, + NDL7, 32, + NDL8, 32, + ASLP, 32, // ASL sleep timeout + TIDX, 32, // Toggle table index + CHPD, 32, // Current hot plug enable indicator + CLID, 32, // Current lid state indicator + CDCK, 32, // Current docking state indicator + SXSW, 32, // Display switch notify on resume + EVTS, 32, // Events supported by ASL (diag only) + CNOT, 32, // Current OS notifications (diag only) + NRDY, 32, + + // OpRegion Mailbox 2 (Software SCI Interface) + + Offset(0x200), // SCIC + SCIE, 1, // SCI entry bit (1=call unserviced) + GEFC, 4, // Entry function code + GXFC, 3, // Exit result + GESF, 8, // Entry/exit sub-function/parameter + , 16, // SCIC[31:16] reserved + Offset(0x204), // PARM + PARM, 32, // PARM register (extra parameters) + DSLP, 32, // Driver sleep time out + + // OpRegion Mailbox 3 (BIOS to Driver Notification) + // Note: Mailbox 3 is normally reserved for desktop platforms. + + Offset(0x300), + ARDY, 32, // Driver readiness (power conservation) + ASLC, 32, // ASLE interrupt command/status + TCHE, 32, // Technology enabled indicator + ALSI, 32, // Current ALS illuminance reading + BCLP, 32, // Backlight brightness + PFIT, 32, // Panel fitting state or request + CBLV, 32, // Current brightness level + BCLM, 320, // Backlight brightness level duty cycle mapping table + CPFM, 32, // Current panel fitting mode + EPFM, 32, // Enabled panel fitting modes + PLUT, 592, // Optional. 74-byte Panel LUT Table + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. + PCFT, 32, // Optional. Power Conservation Features + + Offset(0x3B6), + STAT, 32, // Status register + + // OpRegion Mailbox 4 (VBT) + + Offset(0x400), + GVD1, 0xC000, // 6K bytes maximum VBT image + + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) + + Offset(0x1C00), + PHED, 32, // Panel Header + BDDC, 2048, // Panel EDID (Max 256 bytes) + +} + + + +// Convert boot display type into a port mask. + +Name (DBTB, Package() +{ + 0x0000, // Automatic + 0x0007, // Port-0 : Integrated CRT + 0x0038, // Port-1 : DVO-A, or Integrated LVDS + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C + 0x0E00, // Port-3 : SDVO-C + 0x003F, // [CRT + DVO-A / Integrated LVDS] + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] + 0x0E07, // [CRT + SDVO-C] + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] + 0x0FC0, // [SDVO-B + SDVO-C] + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x7000, // Port-4: Integrated TV + 0x7007, // [Integrated TV + CRT] + 0x7038, // [Integrated TV + LVDS] + 0x71C0, // [Integrated TV + DVOB] + 0x7E00 // [Integrated TV + DVOC] +}) + +// Core display clock value table. + +Name (CDCT, Package() +{ + Package() {160}, + Package() {200}, + Package() {267}, + Package() {320}, + Package() {356}, + Package() {400}, +}) + +// Defined exit result values: + +Name (SUCC, 1) // Exit result: Success +Name (NVLD, 2) // Exit result: Invalid parameter +Name (CRIT, 4) // Exit result: Critical failure +Name (NCRT, 6) // Exit result: Non-critical failure + + +/************************************************************************; +;* +;* Name: GSCI +;* +;* Description: Handles an SCI generated by the graphics driver. The +;* PARM and SCIC input fields are parsed to determine the +;* functionality requested by the driver. GBDA or SBCB +;* is called based on the input data in SCIC. +;* +;* Usage: The method must be called in response to a GPE 06 event +;* which will be generated by the graphics driver. +;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())} +;* +;* Input: PARM and SCIC are indirect inputs +;* +;* Output: PARM and SIC are indirect outputs +;* +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback +;* method) +;* +;************************************************************************/ + +Method (GSCI, 0, Serialized) +{ + Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions + Include("IgdOSBCB.ASL") // "System BIOS CallBacks" + + If (LEqual(GEFC, 4)) + { + Store(GBDA(), GXFC) // Process Get BIOS Data functions + } + + If (LEqual(GEFC, 6)) + { + Store(SBCB(), GXFC) // Process BIOS Callback functions + } + + Store(0, GEFC) // Wipe out the entry function code + Store(1, SCIS) // Clear the GUNIT SCI status bit in PCH ACPI I/O space. + Store(0, GSSE) // Clear the SCI generation bit in PCI space. + Store(0, SCIE) // Clr SCI serviced bit to signal completion + + Return(Zero) +} + +// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop. +Include("IgdOMOBF.ASL") // IGD SCI mobile features diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl new file mode 100644 index 0000000000..ef1383b9c1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl @@ -0,0 +1,177 @@ +/** @file +Copyright (c) 2014, Intel Corporation. All rights reserved.
+This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(IOTD) { + Name(_HID, "MSFT8000") + Name(_CID, "MSFT8000") + + Name(_CRS, ResourceTemplate() { + // Index 0 + SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI + 1, // Device selection + PolarityLow, // Device selection polarity + FourWireMode, // wiremode + 8, // databit len + ControllerInitiated, // slave mode + 8000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseSecond, // clock phase + "\\_SB.SPI1", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + ResourceConsumer, // Resource usage + JSPI, // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + + // Index 1 + I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal) + 0x00, // SlaveAddress: bus address (TBD) + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based)) + , + , + JI2C, // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + + // Index 2 + UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2 + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + , // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.URT2", // ResourceSource: UART bus controller name + , + , + UAR2, // DescriptorName: creates name for offset of resource descriptor + ) + + // Index 3 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00]) + // Index 4 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} + + // Index 5 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01]) + // Index 6 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1} + + // Index 7 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02]) + // Index 8 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} + + // Index 9 + UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1 + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.URT1", // ResourceSource: UART bus controller name + , + , + UAR1, // DescriptorName: creates name for offset of resource descriptor + ) + + // Index 10 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62]) + // Index 11 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} + + // Index 12 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63]) + // Index 13 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} + + // Index 14 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65]) + // Index 15 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} + + // Index 16 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64]) + // Index 17 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} + + // Index 18 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94]) + // Index 19 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} + + // Index 20 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95]) + // Index 21 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} + + // Index 22 + GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54]) + // Index 23 + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54} + }) + + Name(_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package(1) { // Just one Property for IOT (at this time) + Package(2) { //The “symbolic-identifiers” property + "symbolic-identifiers", + Package() { //Contains all the pairs + 0, "SPI0", + 1, "I2C5", + 2, "UART2", + 3, 21, // Pin 21 of JP1 (GPIO_S5[00]) + 4, 21, // Pin 21 for separate resource. + 5, 23, // Pin 23 of JP1 (GPIO_S5[01]) + 6, 23, + 7, 25, // Pin 25 of JP1 (GPIO_S5[02]) + 8, 25, + 9, "UART1", + 10, 14, // Pin 14 of JP1 (GPIO_SC[62]) + 11, 14, + 12, 16, // Pin 16 of JP1 (GPIO_SC[63]) + 13, 16, + 14, 18, // Pin 18 of JP1 (GPIO_SC[65]) + 15, 18, + 16, 20, // Pin 20 of JP1 (GPIO_SC[64]) + 17, 20, + 18, 22, // Pin 22 of JP1 (GPIO_SC[94]) + 19, 22, + 20, 24, // Pin 24 of JP1 (GPIO_SC[95]) + 21, 24, + 22, 26, // Pin 26 of JP1 (GPIO_SC[54]) + 23, 26 + } + } + } + }) + + Method(_STA,0,Serialized) { + + // + // Only report IoT virtual device when all pins' configuration follows MSFT's datasheet. + // + If (LEqual(IOT, 1)) { + Return (0xF) + } + + Return (0x0) + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL new file mode 100644 index 0000000000..31b4050a3a --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL @@ -0,0 +1,157 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + +Device(FWHD) // Firmware Hub Device +{ + Name(_HID,EISAID("INT0800")) + + Name(_CRS,ResourceTemplate() + { + Memory32Fixed(ReadOnly,0xFF000000,0x1000000) + }) +} + +Device(IPIC) // 8259 PIC +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x20,0x20,0x01,0x02) + IO(Decode16,0x24,0x24,0x01,0x02) + IO(Decode16,0x28,0x28,0x01,0x02) + IO(Decode16,0x2C,0x2C,0x01,0x02) + IO(Decode16,0x30,0x30,0x01,0x02) + IO(Decode16,0x34,0x34,0x01,0x02) + IO(Decode16,0x38,0x38,0x01,0x02) + IO(Decode16,0x3C,0x3C,0x01,0x02) + IO(Decode16,0xA0,0xA0,0x01,0x02) + IO(Decode16,0xA4,0xA4,0x01,0x02) + IO(Decode16,0xA8,0xA8,0x01,0x02) + IO(Decode16,0xAC,0xAC,0x01,0x02) + IO(Decode16,0xB0,0xB0,0x01,0x02) + IO(Decode16,0xB4,0xB4,0x01,0x02) + IO(Decode16,0xB8,0xB8,0x01,0x02) + IO(Decode16,0xBC,0xBC,0x01,0x02) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + IRQNoFlags() {2} + }) +} + +Device(LDRC) // LPC Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,2) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x10) // Postcode. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0x400,0x400,0x1,0x80) // ACPI Base. + IO(Decode16,0x500,0x500,0x1,0xFF) // GPIO Base. + }) +} + +Device(TIMR) // 8254 Timer +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x10,0x04) + IRQNoFlags() {0} + }) +} + +Device(IUR3) // Internal UART +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,1) + + // Status Method for internal UART + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if internal UART is + // not set to Disabled in BIOS Setup. + + If(LEqual(USEL,0)) + { + If(LEqual(PU1E,1)) + { + Store(1,UI3E) // Enable IRQ3 for UART + Store(1,UI4E) // Enable IRQ4 for UART + Store(1,C1EN) // Enable UART + Return(0x000F) + } + } + + Return(0x0000) + } + + // Disable Method for internal UART + + Method(_DIS,0,Serialized) + { + Store(0,UI3E) + Store(0,UI4E) + Store(0,C1EN) + } + + // Current Resource Setting Method for internal UART + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags() {3} + }) + + Name(BUF1,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags() {4} + }) + + If (LLessEqual(SRID, 0x04)) + { + Return(BUF0) + } Else + { + Return(BUF1) + } + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl new file mode 100644 index 0000000000..afa6a53a4d --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl @@ -0,0 +1,65 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +// LPC Bridge - Device 31, Function 0 +// Define the needed LPC registers used by ASL. + +scope(\_SB) +{ + OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C) + Field(ILBR, AnyAcc, NoLock, Preserve) + { + Offset(0x08), // 0x08 + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0x88), // 0x88 + , 3, + UI3E, 1, + UI4E, 1 + } + + Include ("98_LINK.ASL") +} + +OperationRegion(LPC0, PCI_Config, 0x00, 0xC0) +Field(LPC0, AnyAcc, NoLock, Preserve) +{ + Offset(0x08), // 0x08 + SRID, 8, // Revision ID + Offset(0x080), // 0x80 + C1EN, 1, // COM1 Enable + , 31 +} + + +Include ("LPC_DEV.ASL") + + + + + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc new file mode 100644 index 0000000000..ae81b2f4b1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc @@ -0,0 +1,229 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +--*/ + +// +// Include files +// + +#include +#include + + + +// +// LPIT Definitions +// + +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef union _EFI_ACPI_LPI_STATE_FLAGS { + struct { + UINT32 Disabled :1; + UINT32 CounterUnavailable :1; + UINT32 Reserved :30; + }; + UINT32 AsUlong; +} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS; + +// Only Mwait LPI here: + +typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR { + UINT32 Type; // offset: 0 + UINT32 Length; // offset: 4 + UINT16 UniqueId; // offset: 8 + UINT8 Reserved[2]; // offset: 9 + EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16 + UINT32 Residency; // offset: 28 + UINT32 Latency; // offset: 32 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36 + UINT64 ResidencyCounterFrequency; //offset: 48 +} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR; + + +// +// Defines for LPIT table, some are VLV specific +// + + +// signature "LPIT" +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c + +#define EFI_ACPI_OEM_LPIT_REVISION 0x00000000 + +#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K 0x8000 // 32768 + +// +// LPI state count (4 on VLV: S0ir, S0i1, S0i2, S0i3) +// + +#define EFI_ACPI_VLV_LPI_STATE_COUNT 0x4 + +// +// LPI TRIGGER (HW C7 on VLV), +// TOFIX!!! +// +#define EFI_ACPI_VLV_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x64} + +// +// LPI residency counter (MMIO) +// +#define EFI_ACPI_VLV_LPI_RES_COUNTER0 {0x0,32,0x0,0x03,0xFED03080} +#define EFI_ACPI_VLV_LPI_RES_COUNTER1 {0x0,32,0x0,0x03,0xFED03084} +#define EFI_ACPI_VLV_LPI_RES_COUNTER2 {0x0,32,0x0,0x03,0xFED03088} +#define EFI_ACPI_VLV_LPI_RES_COUNTER3 {0x0,32,0x0,0x03,0xFED0308C} + +// +// LPI break-even residency in us - all match S0i3 residency +// Residency estimate: Latency x 3 +// +#define EFI_ACPI_VLV_LPI_MIN_RES0 15000 +#define EFI_ACPI_VLV_LPI_MIN_RES1 15000 +#define EFI_ACPI_VLV_LPI_MIN_RES2 15000 +#define EFI_ACPI_VLV_LPI_MIN_RES3 15000 + +// +// LPI latency in us - all match S0i3 latency +// +#define EFI_ACPI_VLV_LPI_LATENCY0 5000 +#define EFI_ACPI_VLV_LPI_LATENCY1 5000 +#define EFI_ACPI_VLV_LPI_LATENCY2 5000 +#define EFI_ACPI_VLV_LPI_LATENCY3 5000 + + +// +// LPI ID +// +#define EFI_ACPI_VLV_LPI_UNIQUE_ID0 0 +#define EFI_ACPI_VLV_LPI_UNIQUE_ID1 1 +#define EFI_ACPI_VLV_LPI_UNIQUE_ID2 2 +#define EFI_ACPI_VLV_LPI_UNIQUE_ID3 3 + +// +// LPI ACPI table header +// + + +typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[EFI_ACPI_VLV_LPI_STATE_COUNT]; +} EFI_ACPI_LOW_POWER_IDLE_TABLE; + +#pragma pack() + +EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = { + + // + // Header + // + + + EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE), + EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION , + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be updated at runtime + // + ' ', ' ', ' ', ' ', ' ', ' ', + + 0, + EFI_ACPI_OEM_LPIT_REVISION, + 0, + 0, + + + + // + // Descriptor + // + { + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_VLV_LPI_UNIQUE_ID0, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_VLV_LPI_MIN_RES0, //Residency + EFI_ACPI_VLV_LPI_LATENCY0, //Latency + EFI_ACPI_VLV_LPI_RES_COUNTER0, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency + }, + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_VLV_LPI_UNIQUE_ID1, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_VLV_LPI_MIN_RES1, //Residency + EFI_ACPI_VLV_LPI_LATENCY1, //Latency + EFI_ACPI_VLV_LPI_RES_COUNTER1, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency + }, + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_VLV_LPI_UNIQUE_ID2, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_VLV_LPI_MIN_RES2, //Residency + EFI_ACPI_VLV_LPI_LATENCY2, //Latency + EFI_ACPI_VLV_LPI_RES_COUNTER2, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency + }, + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_VLV_LPI_UNIQUE_ID3, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_VLV_LPI_MIN_RES3, //Residency + EFI_ACPI_VLV_LPI_LATENCY3, //Latency + EFI_ACPI_VLV_LPI_RES_COUNTER3, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency + } + } + +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Lpit; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h new file mode 100644 index 0000000000..7a01d6487f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h @@ -0,0 +1,195 @@ +/*++ + +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Madt.h + +Abstract: + + This file describes the contents of the ACPI Multiple APIC Description + Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + To make changes to the MADT, it is necessary to update the count for the + APIC structure being updated, and to modify table found in Madt.c. + +--*/ + +#ifndef _MADT_H +#define _MADT_H + +// +// Statements that include other files +// +#include "AcpiTablePlatform.h" +#include +#include +#include +#include "Platform.h" + +// +// MADT Definitions +// +#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) +#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT) +#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_3_0_PCAT_COMPAT) +#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_4_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT MAX_CPU_NUM +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT MAX_CPU_NUM +#define EFI_ACPI_IO_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +// +// MADT structure +// +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI 1.0 Table structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 2.0 Table structure +// +typedef struct { + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 3.0 Table structure +// +typedef struct { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x00 + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01 + EFI_ACPI_3_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02 + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03 + EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x04 + EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05 + EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06 + EFI_ACPI_3_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0 + EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08 + EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack() + +#endif diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc new file mode 100644 index 0000000000..7b16120234 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc @@ -0,0 +1,184 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Madt3.0.c + +Abstract: + + This file contains a structure definition for the ACPI 2.0 Multiple APIC + Description Table (MADT). Any changes to the MADT table require updating the + respective structure count in Madt.h and then adding the structure to the + MADT defined in this file. The table layout is defined in Madt.h and the + table contents are defined in Acpi3_0.h and Madt.h. + +--*/ + +// +// Statements that include other files +// +#include "Madt.h" +#include + +// +// Multiple APIC Description Table +// +EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC". + sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE), // **Length + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + // + // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // **Table Revision must be 2.0 for ACPI 3.0 + // Checksum will be updated at runtime + // + 0x00, // **Check sum + // + // It is expected that these values will be programmed at runtime + // + ' ', // OEMID + ' ', // Creative way to + ' ', // make six bytes + ' ', // of space in + ' ', // a table for + ' ', // **OEMID + 0, // **OEM Table ID + EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision + 0, // **Creator ID + 0, // **Creator Revision + // + // MADT specific fields + // + LOCAL_APIC_ADDRESS, // **Local APIC Address + EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags + // + // Processor Local APIC Structure + // Correct processor order, Primary threads first then Hyper threads + // And correct APIC-ids + // This text below is included as a reference until Thurley is 100%: + // According to EDS the Local APIC ID is determined based of a bit structure + // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved + // 4 Sockets and 4 Cores per Socket. + // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 + // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33 + // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries. + // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)] + // So if BSP LAPIC ID is 21 then table rotated 6 times. + // End of Reference Text. + // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core. + // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs) + // Rhyme & reason of the ordering below. This is a best guess ordering for now, + // Thurley EPS may give better info on LAPIC numbers. + // Ordering was established to help dissipate heat across two sockets evenly. + // Since logical processor number only has to be unique, I followed + // a similar approach to high end servers and have the first digit of the LAPIC + // id the socket number. + // + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type 0x00 + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor ID + 0x00, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x02, // Processor ID + 0x02, // Local APIC ID //Todo: Temp change APIC ID order for fixing VLV X0 not enable 2 CPU in Windows. + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x03, // Processor ID + 0x04, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x04, // Processor ID + 0x06, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + // + // *************** IO APIC Structure ****************** + // + // + // + // ************************** I/O APIC ************** + // + EFI_ACPI_3_0_IO_APIC, // Type 0x01 + sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE), // Length + ICH_IOAPIC_ID, // IO APIC ID + EFI_ACPI_RESERVED_BYTE, // Reserved EFI_ACPI_RESERVED_BYTE + IO_APIC_ADDRESS, // IO APIC Address (physical) 0xFEC00000 + 0x18 * 0, // Global System Interrupt Base + + // + // Interrupt Source Override Structure: Sample + // + // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + // 0x00, // Bus + // 0x00, // Source + // 0x00000000, // Global System Interrupt + // 0x0000, // Flags + // + // IRQ0=>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x00, // Source - IRQ0 + 0x00000002, // Global System Interrupt - IRQ2 + 0x0000, // Flags - Conforms to specifications of the bus + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x09, // Source - IRQ0 + 0x00000009, // Global System Interrupt - IRQ2 + 0x000D, // Flags - Level-tiggered, Active High + + + + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x01, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x02, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x03, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x04, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Madt; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc new file mode 100644 index 0000000000..0683ca459e --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc @@ -0,0 +1,92 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Mcfg.c + +Abstract: + + This file contains a structure definition for the ACPI Memory mapped + configuration space base address Description Table (MCFG). Any changes + to the MCFG table require updating the respective structure count in + Mcfg.h and then adding the structure to the MCFG defined in this file. + The table layout is defined in Mcfg.h and the table contents are defined + in McfgTable.h and Mcfg.h. + +--*/ + +// +// Statements that include other files +// +#include + +// +// MCFG Table definition +// +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = { + EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + + 0, + EFI_ACPI_OEM_MCFG_REVISION, + 0, + 0, + // + // Beginning of MCFG specific fields + // + EFI_ACPI_RESERVED_QWORD, + // + // Sample Memory Mapped Configuration Space Base Address Structure + // + // 0x0, // Base Address + // 0x0, // PCI Segment Group Number + // 0x0, // Start Bus Number + // 0x0, // End Bus Number + // EFI_ACPI_RESERVED_DWORD, // Reserved + // + // Memory Mapped Configuration Space Base Address Structure + // + 0x0, // Base Address, will be updated by AcpiPlatform + 0x0, // PCI Segment Group Number + 0x0, // Start Bus Number + PLATFORM_MAX_BUS_NUM, // End Bus Number + EFI_ACPI_RESERVED_DWORD, // Reserved +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&MCFG; +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL new file mode 100644 index 0000000000..73b3d4db3d --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL @@ -0,0 +1,96 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + + +Scope (\_SB.PCI0) +{ + + Device(PDRC) // PCI Device Resource Consumption + { + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,1) + + Name(BUF0,ResourceTemplate() + { + // + // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h + // Forced hard code at the moment. + // + //Memory32Fixed(ReadWrite,0,0,PCIX) // PCIEX BAR + Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX) + + // + // SPI BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR + + // + // PMC BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR + + // + // SMB BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR + + // + // IO BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR + + // + // ILB BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR + + // + // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h + // + Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH) + + // + // MPHY BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB) // MPHY BAR + }) + + Method(_CRS,0,Serialized) + { + + Return(BUF0) + } + + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl new file mode 100644 index 0000000000..38dac87bcd --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl @@ -0,0 +1,685 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +Scope(\) +{ + // + // Define VLV ABASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Registers 40-43h. + // + OperationRegion(PMIO, SystemIo, \PMBS, 0x46) + Field(PMIO, ByteAcc, NoLock, Preserve) + { + , 8, + PWBS, 1, // Power Button Status + Offset(0x20), + , 13, + PMEB, 1, // PME_B0_STS + Offset(0x42), // General Purpose Control + , 1, + GPEC, 1 + } + Field(PMIO, ByteAcc, NoLock, WriteAsZeros) + { + Offset(0x20), // GPE0 Status + , 4, + PSCI, 1, // PUNIT SCI Status + SCIS, 1 // GUNIT SCI Status + } + + + + // + // Define a Memory Region that will allow access to the PMC + // Register Block. Note that in the Intel Reference Solution, the PMC + // will get fixed up dynamically during POST. + // + OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register + Field(PMCR,DWordAcc,Lock,Preserve) + { + Offset(0x00), // Function Disable Register + L10D, 1, // (0) LPIO1 DMA Disable + L11D, 1, // (1) LPIO1 PWM #1 Disable + L12D, 1, // (2) LPIO1 PWM #2 Disable + L13D, 1, // (3) LPIO1 HS-UART #1 Disable + L14D, 1, // (4) LPIO1 HS-UART #2 Disable + L15D, 1, // (5) LPIO1 SPI Disable + , 2, // (6:7) Reserved + SD1D, 1, // (8) SCC SDIO #1 Disable + SD2D, 1, // (9) SCC SDIO #2 Disable + SD3D, 1, // (10) SCC SDIO #3 Disable + HSID, 1, // (11) + HDAD, 1, // (12) Azalia Disable + LPED, 1, // (13) LPE Disable + OTGD, 1, // (14) USB OTG Disable + , 1, // (15) USH Disable + , 1, // (16) + , 1, // (17) + , 1, // (18) USB Disable + , 1, // (19) SEC Disable + RP1D, 1, // (20) Root Port 0 Disable + RP2D, 1, // (21) Root Port 1 Disable + RP3D, 1, // (22) Root Port 2 Disable + RP4D, 1, // (23) Root Port 3 Disable + L20D, 1, // (24) LPIO2 DMA Disable + L21D, 1, // (25) LPIO2 I2C #1 Disable + L22D, 1, // (26) LPIO2 I2C #2 Disable + L23D, 1, // (27) LPIO2 I2C #3 Disable + L24D, 1, // (28) LPIO2 I2C #4 Disable + L25D, 1, // (29) LPIO2 I2C #5 Disable + L26D, 1, // (30) LPIO2 I2C #6 Disable + L27D, 1 // (31) LPIO2 I2C #7 Disable + } + + + OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers + Field(CLKC,DWordAcc,Lock,Preserve) + { + Offset(0x00), // PLT_CLK_CTL_0 + CKC0, 2, + CKF0, 1, + , 29, + Offset(0x04), // PLT_CLK_CTL_1 + CKC1, 2, + CKF1, 1, + , 29, + Offset(0x08), // PLT_CLK_CTL_2 + CKC2, 2, + CKF2, 1, + , 29, + Offset(0x0C), // PLT_CLK_CTL_3 + CKC3, 2, + CKF3, 1, + , 29, + Offset(0x10), // PLT_CLK_CTL_4 + CKC4, 2, + CKF4, 1, + , 29, + Offset(0x14), // PLT_CLK_CTL_5 + CKC5, 2, + CKF5, 1, + , 29, + } +} //end Scope(\) + +scope (\_SB) +{ + Device(LPEA) + { + Name (_ADR, 0) + Name (_HID, "80860F28") + Name (_CID, "80860F28") + //Name (_CLS, Package (3) {0x04, 0x01, 0x00}) + Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28") + Name (_SUB, "80867270") + Name (_UID, 1) + Name (_DEP, Package() {\_SB.I2C2.RTEK}) + Name(_PR0,Package() {PLPE}) + + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0))) + { + Return (0xF) + } + Return (0x0) + } + + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO + Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24} + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25} + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26} + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27} + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28} + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29} + GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt + } + ) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + Store(LPE0, B0BA) + CreateDwordField(^RBUF, ^BAR1._BAS, B1BA) + Store(LPE1, B1BA) + CreateDwordField(^RBUF, ^BAR2._BAS, B2BA) + Store(LPE2, B2BA) + Return (RBUF) + } + + OperationRegion (KEYS, SystemMemory, LPE1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + PowerResource(PLPE, 0, 0) // Power Resource for LPEA + { + Method (_STA) + { + Return (1) // Power Resource is always available. + } + + Method (_ON) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_OFF) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + } // End PLPE + } // End "Low Power Engine Audio" + + Device(LPA2) + { + Name (_ADR, 0) + Name (_HID, "LPE0F28") // _HID: Hardware ID + Name (_CID, "LPE0F28") // _CID: Compatible ID + Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name + Name (_SUB, "80867270") + Name (_UID, 1) + Name (_DEP, Package() {\_SB.I2C2.RTEK}) + Name(_PR0,Package() {PLPE}) + + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1))) + { + Return (0xF) + } + Return (0x0) + } + + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM) + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX) + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM) + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29} + Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space + } + ) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^SHIM._BAS, SHBA) + Add(LPE0, 0x140000, SHBA) + CreateDwordField(^RBUF, ^MBOX._BAS, MBBA) + Add(LPE0, 0x144000, MBBA) + CreateDwordField(^RBUF, ^IRAM._BAS, IRBA) + Add(LPE0, 0xC0000, IRBA) + CreateDwordField(^RBUF, ^DRAM._BAS, DRBA) + Add(LPE0, 0x100000, DRBA) + CreateDwordField(^RBUF, ^BAR1._BAS, B1BA) + Store(LPE1, B1BA) + CreateDwordField(^RBUF, ^BAR2._BAS, B2BA) + Store(LPE2, B2BA) + Return (RBUF) + } + + OperationRegion (KEYS, SystemMemory, LPE1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + PowerResource(PLPE, 0, 0) // Power Resource for LPEA + { + Method (_STA) + { + Return (1) // Power Resource is always available. + } + + Method (_ON) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_OFF) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + } // End PLPE + + Device (ADMA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "DMA0F28") // _HID: Hardware ID + Name (_CID, "DMA0F28") // _CID: Compatible ID + Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset + Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24} + }) + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateDwordField(^RBUF, ^DMA0._BAS, D0BA) + Add(LPE0, 0x98000, D0BA) + CreateDwordField(^RBUF, ^SHIM._BAS, SHBA) + Add(LPE0, 0x140000, SHBA) + Return (RBUF) + } + } + } // End "Low Power Engine Audio" for Android +} + +scope (\_SB.PCI0) +{ + + // + // Serial ATA Host Controller - Device 19, Function 0 + // + + Device(SATA) + { + Name(_ADR,0x00130000) + // + // SATA Methods pulled in via SSDT. + // + + OperationRegion(SATR, PCI_Config, 0x74,0x4) + Field(SATR,WordAcc,NoLock,Preserve) + { + Offset(0x00), // 0x74, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + + Method(_DSW, 3) + { + } // End _DSW + } + + // + // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment + // + Device(EM41) + { + Name(_ADR,0x00100000) + OperationRegion(SDIO, PCI_Config, 0x84,0x4) + Field(SDIO,WordAcc,NoLock,Preserve) + { + Offset(0x00), // 0x84, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0))) + { + Return(0xF) + } + Else + { + Return(0x0) + } + } + + Method(_DSW, 3) + { + } // End _DSW + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method(_RMV, 0x0, NotSerialized) + { + Return (0) + } // End _DSW + } + } + + // + // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment + // + Device(EM45) + { + Name(_ADR,0x00170000) + OperationRegion(SDIO, PCI_Config, 0x84,0x4) + Field(SDIO,WordAcc,NoLock,Preserve) + { + Offset(0x00), // 0x84, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0))) + { + Return(0xF) + } + Else + { + Return(0x0) + } + } + + Method(_DSW, 3) + { + } // End _DSW + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method(_RMV, 0x0, NotSerialized) + { + Return (0) + } // End _DSW + } + } + // + // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment + // + Device(SD12) + { + Name(_ADR,0x00120000) + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 0)) { + Return (0x0) + } + + // + // If device is disabled. + // + If (LEqual(SD3D, 1)) + { + Return (0x0) + } + + Return (0xF) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method(_RMV, 0x0, NotSerialized) + { + // SDRM = 0 non-removable; + If (LEqual(SDRM, 0)) + { + Return (0) + } + + Return (1) + } + } + } + + // xHCI Controller - Device 20, Function 0 + include("PchXhci.asl") + + // + // High Definition Audio Controller - Device 27, Function 0 + // + Device(HDEF) + { + Name(_ADR, 0x001B0000) + include("PchAudio.asl") + + Method (_STA, 0x0, NotSerialized) + { + If (LEqual(HDAD, 0)) + { + Return(0xf) + } + Return(0x0) + } + + Method(_DSW, 3) + { + } // End _DSW + } // end "High Definition Audio Controller" + + + + // + // PCIE Root Port #1 + // + Device(RP01) + { + Name(_ADR, 0x001C0000) + include("PchPcie.asl") + Name(_PRW, Package() {9, 4}) + + Method(_PRT,0) + { + If(PICM) { Return(AR04) }// APIC mode + Return (PR04) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #1" + + // + // PCIE Root Port #2 + // + Device(RP02) + { + Name(_ADR, 0x001C0001) + include("PchPcie.asl") + Name(_PRW, Package() {9, 4}) + + Method(_PRT,0) + { + If(PICM) { Return(AR05) }// APIC mode + Return (PR05) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #2" + + // + // PCIE Root Port #3 + // + Device(RP03) + { + Name(_ADR, 0x001C0002) + include("PchPcie.asl") + Name(_PRW, Package() {9, 4}) + Method(_PRT,0) + { + If(PICM) { Return(AR06) }// APIC mode + Return (PR06) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #3" + + // + // PCIE Root Port #4 + // + Device(RP04) + { + Name(_ADR, 0x001C0003) + include("PchPcie.asl") + Name(_PRW, Package() {9, 4}) + Method(_PRT,0) + { + If(PICM) { Return(AR07) }// APIC mode + Return (PR07) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #4" + + + Scope(\_SB) + { + // + // Dummy power resource for USB D3 cold support + // + PowerResource(USBC, 0, 0) + { + Method(_STA) { Return (0xF) } + Method(_ON) {} + Method(_OFF) {} + } + } + // + // EHCI Controller - Device 29, Function 0 + // + Device(EHC1) + { + Name(_ADR, 0x001D0000) + Name(_DEP, Package(0x1) + { + PEPD + }) + include("PchEhci.asl") + Name(_PRW, Package() {0x0D, 4}) + + OperationRegion(USBR, PCI_Config, 0x54,0x4) + Field(USBR,WordAcc,NoLock,Preserve) + { + Offset(0x00), // 0x54, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there + { + Return (0xF) + } Else + { + Return (0x0) + } + } + + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + // + // Create a dummy PR3 method to indicate to the PCI driver + // that the device is capable of D3 cold + // + Method(_PR3, 0x0, NotSerialized) + { + return (Package() {\_SB.USBC}) + } + + } // end "EHCI Controller" + + // + // SMBus Controller - Device 31, Function 3 + // + Device(SBUS) + { + Name(_ADR,0x001F0003) + Include("PchSmb.asl") + } + + Device(SEC0) + { + Name (_ADR, 0x001a0000) // Device 0x1a, Function 0 + Name(_DEP, Package(0x1) + { + PEPD + }) + + + OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, //bit8 PMEENABLE + , 6, + PMES, 1 //bit15 PMESTATUS + } + + // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable) + // Arg1 -- integer that contains target system state (0-4) + // Arg2 -- integer that contains the target device state + Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake + { + } + + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000) + }) + + If (LEqual(PAVP, 2)) + { + Return (RBUF) + } + Return (ResourceTemplate() {}) + } + + Method (_STA) + { + If (LNotEqual(PAVP, 0)) + { + Return (0xF) + } + Return (0x0) + } + } // Device(SEC0) + +} // End scope (\_SB.PCI0) diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl new file mode 100644 index 0000000000..7c93c3af41 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl @@ -0,0 +1,42 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ +// +// High Definition Audio - Device 27, Function 0 +// +OperationRegion(HDAR, PCI_Config, 0x4C,0x10) +Field(HDAR,WordAcc,NoLock,Preserve) +{ + Offset(0x00), // 0x4C, Dock Control Register + DCKA, 1, // Dock Attach + , 7, + Offset(0x01), // 04Dh, Dock Status Register + DCKM, 1, // Dock Mated + , 6, + DCKS, 1, // Docking Supported + Offset(0x08), // 0x54, Power Management Control and Status Register + , 8, + PMEE, 1, // PME_EN + , 6, + PMES, 1 // PME Status +} + + + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl new file mode 100644 index 0000000000..84626e353b --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl @@ -0,0 +1,275 @@ +/***************************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved *; +;* *; +;* This program and the accompanying materials are licensed and made available under *; +;* the terms and conditions of the BSD License that accompanies this distribution. *; +;* The full text of the license may be found at *; +;* http://opensource.org/licenses/bsd-license.php. *; +;* *; +;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, *; +;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. *; +;* *; +;* *; +;* *; +;***************************************************************************************/ + +OperationRegion(PWKE,PCI_Config,0x62,0x04) + +Field(PWKE,DWordAcc,NoLock,Preserve) +{ + , 1, + PWUC, 8 // Port Wake Up Capability Mask +} + +Method(_PSW,1) +{ + If(Arg0) + { + Store(Ones,PWUC) + } + Else + { + Store(0,PWUC) + } +} + +// Leaves the USB ports on in S3/S4 to allow +// the ability to Wake from USB. Therefore, define +// the below control methods to state D2 entry during +// the given S-State. + +Method(_S3D,0) +{ + Return(2) +} + +Method(_S4D,0) +{ + Return(2) +} + +Device(HUBN) +{ + Name(_ADR, Zero) + Device(PR01) + { + Name(_ADR, One) + + // + // There will have "Generic USB Hub" existed at Port 1 of each EHCI controller + // in Windows "Device Manager" while RMH is enabled, so need to add _UPC + // and _PLD to report OS that it's not user visible to pass WHQL: Single Computer + // Display Object test in Win7 + // + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0x00, // Connector type - Type "A" + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0x30, 0x1C, 0x00, 0x00, // Panel Unknown, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + + Device(PR11) + { + Name(_ADR, One) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xE1, 0x1C, 0x00, 0x00, // Front Panel, Vertical Upper, Horz. Left, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + } + + Device(PR12) + { + Name(_ADR, 0x02) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xE1, 0x1D, 0x00, 0x00, // Front Panel, Vertical Center, Horz. Left, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + } + + Device(PR13) + { + Name(_ADR, 0x03) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xE1, 0x1D, 0x00, 0x00, // Front Panel, Vertical Center, Horz. Left, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + } + + Device(PR14) + { + Name(_ADR, 0x04) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xE1, 0x1E, 0x00, 0x00, // Front Panel, Vertical Lower, Horz. Left, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + + // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method + Include("UsbSbd.asl") + } + + Device(PR15) + { + Name(_ADR, 0x05) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xB1, 0x1E, 0x00, 0x00, // Panel Unknown, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method + Include("UsbSbd.asl") + } + + Device(PR16) + { + Name(_ADR, 0x06) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xB1, 0x1E, 0x00, 0x00, // Panel Unknown, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method + Include("UsbSbd.asl") + } + + Device(PR17) + { + Name(_ADR, 0x07) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xB1, 0x1E, 0x00, 0x00, // Panel Unknown, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method + Include("UsbSbd.asl") + } + + Device(PR18) + { + Name(_ADR, 0x08) + Name(_UPC, Package() + { + 0xFF, // Port is connectable + 0xFF, // Proprietary connector + 0x00000000, // Reserved 0 - must be zero + 0x00000000 + }) // Reserved 1 - must be zero + Name(_PLD, Package() + { + Buffer (0x10) + { + 0x81, 0x00, 0x00, 0x00, // Revision 1, Ignore color + 0x00, 0x00, 0x00, 0x00, + 0xB1, 0x1E, 0x00, 0x00, // Panel Unknown, Shape Unknown + 0x00, 0x00, 0x00, 0x00 + } + }) + } + } // End of PR01 +} // End of HUBN diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl new file mode 100644 index 0000000000..3e61e7925b --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl @@ -0,0 +1,1096 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ +// +// LPIO1 DMA#1 (Synopsis GP DMA) +// +Device (GDM1) +{ + Name (_HID, "INTL9C60") + Name (_DDN, "Intel(R) DMA Controller #1 - INTL9C60") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {42} // DMA #1 IRQ + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(D10A, B0BA) + Store(D10L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(D10A, 0), LEqual(L10D, 1))) + { + Return (0x0) + } + Return (0xF) + } +} + +// +// LPIO1 DMA#2 (Synopsis GP DMA) +// +Device (GDM2) +{ + Name (_HID, "INTL9C60") + Name (_DDN, "Intel(R) DMA Controller #2 - INTL9C60") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {43} // DMA #2 IRQ + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(D20A, B0BA) + Store(D20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(D20A, 0), LEqual(L20D, 1))) + { + Return (0x0) + } + Return (0xF) + } +} + +// +// LPIO1 PWM #1 +// +Device(PWM1) +{ + Name (_ADR, 0) + Name (_HID, "80860F09") + Name (_CID, "80860F09") + Name (_DDN, "Intel(R) PWM Controller #1 - 80860F08") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(P10A, B0BA) + Store(P10L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(P10A, 0), LEqual(L11D, 1))) + { + Return (0x0) + } + Return (0xF) + } +} + +// +// LPIO1 PWM #2 +// +Device(PWM2) +{ + Name (_ADR, 0) + Name (_HID, "80860F09") + Name (_CID, "80860F09") + Name (_DDN, "Intel(R) PWM Controller #2 - 80860F09") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(P20A, B0BA) + Store(P20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(P20A, 0), LEqual(L12D, 1))) + { + Return (0x0) + } + Return (0xF) + } +} + +// +// LPIO1 HS-UART #1 +// +Device(URT1) +{ + Name (_ADR, 0) + Name (_HID, "80860F0A") + Name (_CID, "80860F0A") + Name (_DDN, "Intel(R) HS-UART Controller #1 - 80860F0A") + Name (_UID, 1) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {39} // HS-UART #1 IRQ + + FixedDMA(0x2, 0x2, Width32Bit, ) + FixedDMA(0x3, 0x3, Width32Bit, ) + }) + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(U10A, B0BA) + Store(U10L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(U10A, 0), LEqual(L13D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + OperationRegion (KEYS, SystemMemory, U11A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } +}// Device (URT1) + +// +// LPIO1 HS-UART #2 +// +Device(URT2) +{ + Name (_ADR, 0) + Name (_HID, "80860F0A") + Name (_CID, "80860F0A") + Name (_DDN, "Intel(R) HS-UART Controller #2 - 80860F0C") + Name (_UID, 2) + + Name(_DEP, Package(0x1) + { + PEPD + }) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {40} // HS-UART #2 IRQ + + FixedDMA(0x4, 0x4, Width32Bit, ) + FixedDMA(0x5, 0x5, Width32Bit, ) + }) + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(U20A, B0BA) + Store(U20L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(U20A, 0), LEqual(L14D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + OperationRegion (KEYS, SystemMemory, U21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } +}// Device (URT2) + +// +// LPIO1 SPI +// +Device(SPI1) +{ + Name (_ADR, 0) + Name (_HID, "80860F0E") + Name (_CID, "80860F0E") + Name (_UID, "0") // Static bus number assignment + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (_DDN, "Intel(R) SPI Controller - 80860F0E") + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {41} // SPI IRQ + + FixedDMA(0x0, 0x0, Width32Bit, ) + FixedDMA(0x1, 0x1, Width32Bit, ) + }) + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(SP0A, B0BA) + Store(SP0L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(SP0A, 0), LEqual(L15D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + OperationRegion (KEYS, SystemMemory, SP1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } +}// Device (SPI1) + +// +// LPIO2 I2C #1 +// +Device(I2C1) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (_DDN, "Intel(R) I2C Controller #1 - 80860F41") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {32} // I2C #1 IRQ + + FixedDMA(0x10, 0x0, Width32Bit, ) + FixedDMA(0x11, 0x1, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I10A, B0BA) + Store(I10L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I10A, 0), LEqual(L21D, 1))) + { + Return (0x0) + } + Return (0xF) + + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I11A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + +} + +// +// LPIO2 I2C #2 +// +Device(I2C2) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (_DDN, "Intel(R) I2C Controller #2 - 80860F42") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {33} // I2C #2 IRQ + + FixedDMA(0x12, 0x2, Width32Bit, ) + FixedDMA(0x13, 0x3, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I20A, B0BA) + Store(I20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I20A, 0), LEqual(L22D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + + // + // Realtek Audio Codec + // + Device (RTEK) //Audio Codec driver I2C + { + Name (_ADR, 0) + Name (_HID, "10EC5640") + Name (_CID, "10EC5640") + Name (_DDN, "RTEK Codec Controller " ) + Name (_UID, 1) + + + Method(_CRS, 0x0, Serialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus(0x1C, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.I2C2", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {4} // AUD_INT + }) + Return (SBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + + If (LEqual(LPEE, 2)) { // LPE enable/disable + Return(0xF) + } + Return(0) + } + + Method (_DIS, 0x0, NotSerialized) + { + + } + } // Device (RTEK) +} // Device (I2C2) + +// +// LPIO2 I2C #3 +// +Device(I2C3) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name (_DDN, "Intel(R) I2C Controller #3 - 80860F43") + Name (_UID, 3) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {34} // I2C #3 IRQ + + FixedDMA(0x14, 0x4, Width32Bit, ) + FixedDMA(0x15, 0x5, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I30A, B0BA) + Store(I30L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I30A, 0), LEqual(L23D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I31A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + +} + +// +// LPIO2 I2C #4 +// +Device(I2C4) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name (_DDN, "Intel(R) I2C Controller #4 - 80860F44") + Name (_UID, 4) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {35} // I2C #4 IRQ + + FixedDMA(0x16, 0x6, Width32Bit, ) + FixedDMA(0x17, 0x7, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I40A, B0BA) + Store(I40L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I40A, 0), LEqual(L24D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I41A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + PowerResource (CLK0, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CKC0) + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + Store (One, CKC0) + Store (One, CKF0) + Sleep (0x20) + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + Store (0x02, CKC0) + } + } + PowerResource (CLK1, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CKC1) + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + Store (One, CKC1) + Store (One, CKF1) + Sleep (0x20) + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + Store (0x02, CKC1) + } + } +} + +// +// LPIO2 I2C #5 +// +Device(I2C5) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name (_DDN, "Intel(R) I2C Controller #5 - 80860F45") + Name (_UID, 5) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {36} // I2C #5 IRQ + + FixedDMA(0x18, 0x0, Width32Bit, ) + FixedDMA(0x19, 0x1, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I50A, B0BA) + Store(I50L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I50A, 0), LEqual(L25D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I51A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } +} + +// +// LPIO2 I2C #6 +// +Device(I2C6) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + Name (_DDN, "Intel(R) I2C Controller #6 - 80860F46") + Name (_UID, 6) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {37} // I2C #6 IRQ + + FixedDMA(0x1A, 0x02, Width32Bit, ) + FixedDMA(0x1B, 0x03, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I60A, B0BA) + Store(I60L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I60A, 0), LEqual(L26D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, I61A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } +} + +// +// LPIO2 I2C #7 +// +Device(I2C7) +{ + Name (_ADR, 0) + Name (_HID, "80860F41") + Name (_CID, "80860F41") + //Name (_CLS, Package (3) {0x0C, 0x80, 0x00}) + Name (_DDN, "Intel(R) I2C Controller #7 - 80860F47") + Name (_UID, 7) + Name(_DEP, Package(0x1) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {38} // I2C #7 IRQ + + FixedDMA(0x1C, 0x4, Width32Bit, ) + FixedDMA(0x1D, 0x5, Width32Bit, ) + }) + + Method (SSCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x200, 0x200, 0x06 }) + Return (PKG) + } + Method (FMCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x55, 0x99, 0x06 }) + Return (PKG) + } + Method (FPCN, 0x0, NotSerialized) + { + Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 }) + Return (PKG) + } + + Method (_HRV, 0x0, NotSerialized) + { + Return (SOCS) + } + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I70A, B0BA) + Store(I70L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(I70A, 0), LEqual(L27D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + + OperationRegion (KEYS, SystemMemory, I71A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + +} + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl new file mode 100644 index 0000000000..bfd73e4f13 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl @@ -0,0 +1,56 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +OperationRegion(PXCS,PCI_Config,0x40,0xC0) +Field(PXCS,AnyAcc, NoLock, Preserve) +{ + Offset(0x10), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 7, + Offset(0x12), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status + Offset(0x1A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x20), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status +} + + +Device(PXSX) +{ + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + + Name(_PRW, Package() {9,4}) +} + + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl new file mode 100644 index 0000000000..60ff48d013 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl @@ -0,0 +1,616 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ +Device (PEPD) +{ + Name (_HID, "INT3396") + Name(_CID, 0x800dd041) + Name (_UID, 0x1) + + // Indicates if the platform PEP has loaded + Name(PEPP, Zero) + + // Devices score-boarded by the PEP, Rev0 format + Name (DEVS, Package() {0}) + + // Devices score-boarded by the PEP, Rev1 format + Name(DEVX, Package() + { + Package () {"\\_SB.PCI0.XHC1", 0x1}, + Package () {"\\_SB.PCI0.EHC1", 0x1}, + Package () {"\\_SB.PCI0.GFX0", 0x1}, + Package () {"\\_SB.PCI0.GFX0.ISP0", 0x1}, + Package () {"\\_SB.PCI0.SEC0", 0x1}, + Package () {"\\_SB.I2C1", 0x1}, + Package () {"\\_SB.I2C2", 0x1}, + Package () {"\\_SB.I2C3", 0x1}, + Package () {"\\_SB.I2C4", 0x1}, + Package () {"\\_SB.I2C5", 0x1}, + Package () {"\\_SB.I2C6", 0x1}, + Package () {"\\_SB.I2C7", 0x1}, + Package () {"\\_SB.SDHA", 0x1}, + Package () {"\\_SB.SDHB", 0x1}, + Package () {"\\_SB.SDHC", 0x1}, + Package () {"\\_SB.SPI1", 0x1}, + Package () {"\\_SB.URT1", 0x1}, + Package () {"\\_SB.URT2", 0x1}, + }) + // Crashdump device package + Name(CDMP, Package(2) {}) + // Device dependency for uPEP + Name(DEVY, Package() + { + Package() {"\\_PR.CPU0", 0x1, Package() {Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU1", 0x1, Package() {Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU2", 0x1, Package() {Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU3", 0x1, Package() {Package() {0xFF, 0}}}, + Package() {"\\_SB.I2C1", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C2", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C3", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C4", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C5", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C6", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.I2C7", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.PCI0.SEC0", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.PCI0.XHC1", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.PCI0.GFX0.ISP0", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.LPEA", 0x1, Package() {Package() {0x0,3}, Package() {0x1,0}, Package() {0x2,3}, Package() {0x3,3}}}, + Package() {"\\_SB.SDHA", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.SDHB", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.SDHC", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.SPI1", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.URT1", 0x1, Package() {Package() {0xFF,3}}}, + Package() {"\\_SB.URT2", 0x1, Package() {Package() {0xFF,3}}} + }) + // BCCD crashdump information + Name(BCCD, Package() + { + Package() + { + "\\_SB.SDHA", + Package() + { + Package() { Package() {0, 32, 0, 3, 0xFFFFFFFFFFFFFFFF}, Package() {0xFFFFFFFC, 0x0, 0x4}, 0} + } + } + }) + + Method(_STA, 0x0, NotSerialized) + { + Return(0xf) + } + + Method(_DSM, 0x4, Serialized) + { + If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21"))) + { + + // Number of fn IDs supported + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One) + { + 0xf + }) + } + + // Pep presence + If(LEqual(Arg2, One)) + { + Store(0x1, PEPP) + Return(0xf) + } + + // Mitigation devices + If(LEqual(Arg2, 0x2)) + { + If(LEqual(Arg1, 0x0)) + { + // Rev0 + Return(DEVS) + } + If(LEqual(Arg1, 0x1)) + { + // Rev1 + Return(DEVX) + } + } + + // Crashdump device data + If(LEqual(Arg2, 0x3)) + { + Store("\\_SB.SDHA", Index(CDMP,0)) + Store(EM1A, Index(CDMP,1)) + Return(CDMP) + } + } + // New UUID for built-in uPEP + If(LEqual(Arg0,ToUUID("C4EB40A0-6CD2-11E2-BCFD-0800200C9A66"))) + { + + // Number of fn IDs supported + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One) + { + 0x7 + }) + } + // LPI device dependencies + If(LEqual(Arg2, 0x1)) + { + Return(DEVY) + } + // Crashdump device data + If(LEqual(Arg2, 0x2)) + { + Store(EM1A, Local0) + Add(Local0, 0x84, Local0) + Store(Local0, Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(BCCD, Zero, )), One, )), Zero, )), Zero, )), 0x4, )) + Return(BCCD) + } + } + + Return(One) + } +} + +// +// eMMC 4.41 +// +Device(SDHA) +{ + Name (_ADR, 0) + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) eMMC Controller - 80860F14") + Name (_UID, 1) + Name(_DEP, Package(0x1) + { + PEPD + }) + + Name (RBF1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {45} // eMMC 4.41 IRQ + }) + + Method (_CRS, 0x0, NotSerialized) + { + // Update the Base address for BAR0 of eMMC 4.41 + CreateDwordField(^RBF1, ^BAR0._BAS, B0B1) + CreateDwordField(^RBF1, ^BAR0._LEN, B0L1) + Store(eM0A, B0B1) + Store(eM0L, B0L1) + Return (RBF1) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // SD1D>> 0:eMMC 4.41 enable 1:eMMC 4.41 disable + // + If (LAnd(LEqual(PCIM, 0), LEqual(SD1D, 0))) + { + Return (0xF) + } + Else + { + Return (0x0) + } + } + + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + // + // If not B1, still keep 2 ms w/a + // + If(LLess(SOCS, 0x03)) + { + Sleep(2) + } + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + // + // If not B1, still keep 2 ms w/a + // + If(LLess(SOCS, 0x03)) + { + Sleep(2) + } + } + + OperationRegion (KEYS, SystemMemory, eM1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Method (_DIS, 0x0, NotSerialized) + { + //Adding dummy disable methods for device EMM0 + } + + Device (EMMD) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } +} + + +// +// eMMC 4.5 +// +Device(SDHD) +{ + Name (_ADR, 0) + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) eMMC Controller - 80860F14") + Name (_UID, 1) + Name(_DEP, Package(0x1) + { + PEPD + }) + + Name (RBF1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {44} // eMMC 4.5 IRQ + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBF1, ^BAR0._BAS, B0B1) + CreateDwordField(^RBF1, ^BAR0._LEN, B0L1) + Store(eM0A, B0B1) + Store(eM0L, B0L1) + Return (RBF1) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // HSID>> 0:eMMC 4.5 enable 1:eMMC 4.5 disable + // + If (LAnd(LEqual(PCIM, 0), LEqual(HSID, 0))) + { + Return (0xF) + } + Else + { + Return (0x0) + } + } + + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + // + // If not B1, still keep 2 ms w/a + // + If(LLess(SOCS, 0x03)) + { + Sleep(2) + } + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + // + // If not B1, still keep 2 ms w/a + // + If(LLess(SOCS, 0x03)) + { + Sleep(2) + } + } + + OperationRegion (KEYS, SystemMemory, eM1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Method (_DIS, 0x0, NotSerialized) + { + //Adding dummy disable methods for device EMM0 + } + + Device (EM45) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } +} + + +// +// SDIO +// +Device(SDHB) +{ + Name (_ADR, 0) + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) SDIO Controller - 80860F15") + Name (_UID, 2) + Name (_HRV, 2) + Name(_DEP, Package(0x01) + { + PEPD + }) + Name (PSTS, 0x0) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {46} // SDIO IRQ + }) + + Method (_CRS, 0x0, NotSerialized) + { + + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(SI0A, B0BA) + Store(SI0L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LLessEqual(STEP, 0x04)) + { + //A stepping + Store(SDMD, _HRV) + } + + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(SI0A, 0), LEqual(SD2D, 1))) + { + Return (0x0) + } + Return (0xF) + } + Method (_DIS, 0x0, NotSerialized) + { + //Adding dummy disable methods for device EMM0 + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + + if(LEqual(\_SB.SDHB.PSTS,0x0)) + { + if(LEqual (\_SB.GPO2.AVBL, 1)) + { + Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state + Store( 0x01, \_SB.SDHB.PSTS) // indicates that the device powered ON + } + } + + + } + OperationRegion (KEYS, SystemMemory, SI1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + + Device (BRCM) + { + Name (_ADR, 0x01) //SlotNumber + Function + Name (_DEP, Package() {\_SB.GPO2}) + + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + Name (_PRW, Package() {0, 0}) + Name (_S4W, 2) + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {73} + }) + Return (RBUF) + } + + Method (_PS3, 0, NotSerialized) + { + if(LEqual (\_SB.GPO2.AVBL, 1)) + { + Store( 0x00, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 0 puts the device in reset state + Store( 0x00, \_SB.SDHB.PSTS) //Indicates that the device is powered off + } + + } + Method (_PS0, 0, NotSerialized) + { + if(LEqual(\_SB.SDHB.PSTS,0x0)) + { + if(LEqual (\_SB.GPO2.AVBL, 1)) + { + Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state + Store( 0x01, \_SB.SDHB.PSTS) // indicates that the device powered ON + } + } + } + } // Device (BRCM) + // + // Secondary Broadcom WIFI function + // + Device(BRC2) + { + Name(_ADR, 0x2) // function 2 + Name(_STA, 0xf) + // + // The device is not removable. This must be a method. + // + Method(_RMV, 0x0, NotSerialized) + { + Return(0x0) + } + + // + // Describe a vendor-defined connection between this device and the + // primary wifi device + // + + Method(_CRS) + { + Name(NAM, Buffer() {"\\_SB.SDHB.BRCM"}) + Name(SPB, Buffer() + { + 0x8E, // SPB Descriptor + 0x18, 0x00, // Length including NAM above + 0x01, // +0x00 SPB Descriptor Revision + 0x00, // +0x01 Resource Source Index + 0xc0, // +0x02 Bus type - vendor defined + 0x02, // +0x03 Consumer + controller initiated + 0x00, 0x00, // +0x04 Type specific flags + 0x01, // +0x06 Type specific revision + 0x00, 0x00 // +0x07 type specific data length + // +0x09 - 0xf bytes for NULL-terminated NAM + // Length = 0x18 + }) + + Name(END, Buffer() {0x79, 0x00}) + Concatenate(SPB, NAM, Local0) + Concatenate(Local0, END, Local1) + Return(Local1) + } + } + +} + +// +// SD Card +// +Device(SDHC) +{ + Name (_ADR, 0) + Name (_HID, "80860F16") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) SD Card Controller - 80860F16") + Name (_UID, 3) + Name(_DEP, Package(0x01) + { + PEPD + }) + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {47} // SD Card IRQ + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(SD0A, B0BA) + Store(SD0L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + // + // PCIM>> 0:ACPI mode 1:PCI mode + // + If (LEqual(PCIM, 1)) { + Return (0x0) + } + + If (LOr(LEqual(SD0A, 0), LEqual(SD3D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xfffffffC, PSAT) + OR(PSAT, 0X00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, SD1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method(_RMV, 0x0, NotSerialized) + { + // SDRM = 0 non-removable; + If (LEqual(SDRM, 0)) + { + Return (0) + } + + Return (1) + } + } + +} + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl new file mode 100644 index 0000000000..42ecbe296f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl @@ -0,0 +1,839 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +// Define various SMBus PCI Configuration Space Registers. + +OperationRegion(SMBP,PCI_Config,0x40,0xC0) +Field(SMBP,DWordAcc,NoLock,Preserve) +{ + , 2, + I2CE, 1 +} + +// SMBus Send Byte - This function will write a single byte of +// data to a specific Slave Device per SMBus Send Byte Protocol. +// Arg0 = Address +// Arg1 = Data +// Return: Success = 1 +// Failure = 0 + + Method(SSXB,2,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Send Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Data in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) +} + +// SMBus Receive Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Receive Byte +// Protocol. +// Arg0 = Address +// Return: Success = Byte-Size Value +// Failure = Word-Size Value = FFFFh. + +Method(SRXB,1,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Receive Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x44,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Write Byte +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SWRB,3,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Arg2,DAT0) // Data in DAT0. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Byte - This function will read a single byte of data +// from a specific slave device per SMBus Read Byte Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Byte-Size Value +// Failure = Word-Size Value + +Method(SRDB,2,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Word - This function will write a single word +// of data to a specific Slave Device per SMBus Write Word +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data (16 bits in size) +// Return: Success = 1 +// Failure = 0 + +Method(SWRW,3,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + And(Arg2,0xFF,DAT1) // Low byte Data in DAT1. + And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Word - This function will read a single byte of data +// from a specific slave device per SMBus Read Word Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Word-Size Value +// Failure = Dword-Size Value + +Method(SRDW,2,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success. + } + + Return(0xFFFFFFFF) // Return Failure. +} + +// SMBus Block Write - This function will write an entire block of data +// to a specific slave device per SMBus Block Write Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Buffer of Data to Write +// Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = 1 +// Failure = 0 + +Method(SBLW,4,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Write. + + Store(Arg3,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Sizeof(Arg2),DAT0) // Count in DAT0. + Store(0,Local1) // Init Pointer to Buffer. + Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Send the entire Block of Data. + + While(LGreater(Sizeof(Arg2),Local1)) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) // Point to Next Byte. + + // Place next byte in HBDR if last byte has not been sent. + + If(LGreater(Sizeof(Arg2),Local1)) + { + Store(DerefOf(Index(Arg2,Local1)),HBDR) + } + } + + // Step 4: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear all status bits. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Block Read - This function will read a block of data from +// a specific slave device per SMBus Block Read Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = Data Buffer (First Byte = length) +// Failure = 0 + +Method(SBLR,3,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + Name(TBUF, Buffer(256) {}) + + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Read. + + Store(Arg2,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Wait up to 200ms to get the Data Count. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(DAT0,Index(TBUF,0)) // Get the Data Count. + Store(0x80,HSTS) // Clear Host Status. + Store(1,Local1) // Local1 = Buffer Pointer. + + // Step 4: Get the Block Data and store it. + + While(LLess(Local1,DerefOf(Index(TBUF,0)))) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(HBDR,Index(TBUF,Local1)) // Place into Buffer. + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) + } + + // Step 5: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(TBUF) // Return Success. + } + + Return(0) // Return Failure. +} + + +// SMBus Start Check +// Return: Success = 0 +// Failure = 1 + +Method(STRT,0,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Wait up to 200ms to confirm the SMBus Semaphore has been + // released (In Use Status = 0). Note that the Sleep time may take + // longer as the This function will yield the Processor such that it + // may perform different tasks during the delay. + + Store(200,Local0) // 200 * 1ms = 200ms. + + While(Local0) + { + If(And(HSTS,0x40)) // In Use Set? + { + Decrement(Local0) // Yes. Decrement Count. + Sleep(1) // Delay = 1ms. + If(LEqual(Local0,0)) // Count = 0? + { + Return(1) // Return failure. + } + } + Else + { + Store(0,Local0) // In Use Clear. Continue. + } + } + + // In Use Status = 0 during last read, which will make subsequent + // reads return In Use Status = 1 until software clears it. All + // software using ICHx SMBus should check this bit before initiating + // any SMBus communication. + + // Wait up to 200ms to confirm the Host Interface is + // not processing a command. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x01)) // Host Busy Set? + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + Else + { + Return(0) + } + } + + Return(1) // Timeout. Return failure. +} + +// SMBus Completion Check +// Return: Success = 1 +// Failure = 0 + +Method(COMP,0,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + // Wait for up to 200ms for the Completion Command + // Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x02)) // Completion Status Set? + { + Return(1) // Yes. We are done. + } + Else + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + } + + Return(0) // Timeout. Return Failure. +} + +// SMBus Kill Command + +Method(KILL,0,Serialized) +{ + OperationRegion(SMPB,PCI_Config,0x20,4) + Field(SMPB,DWordAcc,NoLock,Preserve) + { + , 5, + SBAR, 11 + } + + // Define various SMBus IO Mapped Registers. + + OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) + Field(SMBI,ByteAcc,NoLock,Preserve) + { + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data + } + Or(HCON,0x02,HCON) // Yes. Send Kill command. + Or(HSTS,0xFF,HSTS) // Clear all status. +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl new file mode 100644 index 0000000000..696a5411d5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl @@ -0,0 +1,385 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + +//scope is \_SB.PCI0.XHC +Device(XHC1) +{ + Name(_ADR, 0x00140000) //Device 20, Function 0 + + //When it is in Host mode, USH core is connected to USB3 microAB(USB3 P1 and USB2 P0) + Name (_DDN, "Baytrail XHCI controller (CCG core/Host only)" ) + + Method(XDEP, 0) + { + If(LEqual(OSYS,2013)) + { + Name(_DEP, Package(0x1) + { + PEPD + }) + } + } + + Name (_STR, Unicode ("Baytrail XHCI controller (CCG core/Host only)")) + Name(_PRW, Package() {0xD,4}) + + Method(_PSW,1) + { + If (LAnd (PMES, PMEE)) { + Store (0, PMEE) + Store (1, PMES) + } + } + + OperationRegion (PMEB, PCI_Config, 0x74, 0x04) // Power Management Control/Status + Field (PMEB, WordAcc, NoLock, Preserve) + { + , 8, + PMEE, 1, //bit8 PME_En + , 6, + PMES, 1 //bit15 PME_Status + } + + Method(_STA, 0) + { + If(LNotEqual(XHCI, 0)) //NVS variable controls present of XHCI controller + { + Return (0xF) + } Else + { + Return (0x0) + } + } + + OperationRegion(XPRT,PCI_Config,0xD0,0x10) + Field(XPRT,DWordAcc,NoLock,Preserve) //usbx_top.doc.xml + { + PR2, 32, //bit[8:0] USB2HCSEL + PR2M, 32, //bit[8:0] USB2HCSELM + PR3, 32, //bit[3:0] USB3SSEN + PR3M, 32 //bit[3:0] USB3SSENM + } + + Device(RHUB) + { + Name(_ADR, Zero) //address 0 is reserved for root hub + + // + // Super Speed Ports - must match _UPC declarations of the coresponding Full Speed Ports. + // Paired with Port 1 + Device(SSP1) + { + Name(_ADR, 0x07) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, // Port is connectable if non-zero + 0x06, // USB3 uAB connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() //pls check ACPI 5.0 section 6.1.8 + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x4B, 0x19, 0x00, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x03, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Return (PLDP) + } + } + // + // High Speed Ports + // pair port with port 7 (SS) + // The UPC declarations for LS/FS/HS and SS ports that are paired to form a USB3.0 compatible connector. + // A "pair" is defined by two ports that declare _PLDs with identical Panel, Vertical Position, Horizontal Postion, Shape, Group Orientation + // and Group Token + Device(HS01) + { + Name(_ADR, 0x01) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() { 0xFF,0x06,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() //pls check ACPI 5.0 section 6.1.8 + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x4B, 0x19, 0x00, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x03, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Return (PLDP) + } + }//end of HS01 + + // USB2 Type-A/USB2 only + // EHCI debug capable + Device(HS02) + { + Name(_ADR, 0x02) // 0 is for root hub so physical port index starts from 1 (it is port1 in schematic) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, // connectable + 0xFF, // + 0x00, + 0x00 + }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 not visiable/no docking/no lid bit[69:67]=b'000 top bit[71:70]=b'01 Center bit[73:72]=b'00 Left + // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x40, 0x08, 0x00, 0x00, + //127:96 -bit[96]=0 not Ejectable bit[97]=0 no OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS02 + // high speed port 3 + Device(HS03) + { + Name(_ADR, 0x03) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, // connectable + 0xFF, + 0x00, + 0x00 + }) + + Return(UPCP) + } + + Method(_RMV, 0) // for XHCICV debug purpose + { + Return(0x0) + } + + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored) + // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore + // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x30, 0x08, 0x00, 0x00, + //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Return (PLDP) + } + } + + Device(HS04) + { + Name(_ADR, 0x04) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, //connectable + 0xFF, //Proprietary connector (FPC connector) + 0x00, + 0x00 + }) + + Return(UPCP) + } + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored) + // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore + // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x30, 0x08, 0x00, 0x00, + //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + } + + + Device(HSC1) // USB2 HSIC 01 + { + Name(_ADR, 0x05) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, //connectable + 0xFF, //Proprietary connector (FPC connector) + 0x00, + 0x00 + }) + + Return(UPCP) + } + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored) + // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore + // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x30, 0x08, 0x00, 0x00, + //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Return (PLDP) + } + } + + Device(HSC2) // USB2 HSIC 02 + { + Name(_ADR, 0x06) + + Method(_UPC,0,Serialized) + { + Name(UPCP, Package() + { + 0xFF, //connectable + 0xFF, //Proprietary connector (FPC connector) + 0x00, + 0x00 + }) + + Return(UPCP) + } + Method(_PLD,0,Serialized) + { + Name(PLDP, Package() + { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and Horizontal Position will be ignored) + // bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore + // bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + 0x30, 0x08, 0x00, 0x00, + //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Return (PLDP) + } + } + } //end of root hub + +} // end of XHC1 + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl new file mode 100644 index 0000000000..84a7ee21d0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl @@ -0,0 +1,373 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + +Scope(\_SB) +{ + +//RTC + Device(RTC) // RTC + { + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x70,0x70,0x01,0x08) + }) + } +//RTC + + Device(HPET) // High Performance Event Timer + { + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000008, //0xB HPET-2 + } + }) + Return (RBUF) + } + } +//HPET + + Name(PR00, Package() + { +// SD Host #0 - eMMC + Package() {0x0010FFFF, 0, LNKA, 0 }, +// SD Host #1 - SDIO + Package() {0x0011FFFF, 0, LNKB, 0 }, +// SD Host #2 - SD Card + Package() {0x0012FFFF, 0, LNKC, 0 }, +// SATA Controller + Package() {0x0013FFFF, 0, LNKD, 0 }, +// xHCI Host + Package() {0x0014FFFF, 0, LNKE, 0 }, +// Low Power Audio Engine + Package() {0x0015FFFF, 0, LNKF, 0 }, +// USB OTG + Package() {0x0016FFFF, 0, LNKG, 0 }, +// MIPI-HSI/eMMC4.5 + Package() {0x0017FFFF, 0, LNKH, 0 }, +// LPSS2 DMA +// LPSS2 I2C #4 + Package() {0x0018FFFF, 0, LNKB, 0 }, +// LPSS2 I2C #1 +// LPSS2 I2C #5 + Package() {0x0018FFFF, 2, LNKD, 0 }, +// LPSS2 I2C #2 +// LPSS2 I2C #6 + Package() {0x0018FFFF, 3, LNKC, 0 }, +// LPSS2 I2C #3 +// LPSS2 I2C #7 + Package() {0x0018FFFF, 1, LNKA, 0 }, +// SeC + Package() {0x001AFFFF, 0, LNKF, 0 }, +// +// High Definition Audio Controller + Package() {0x001BFFFF, 0, LNKG, 0 }, +// +// EHCI Controller + Package() {0x001DFFFF, 0, LNKH, 0 }, +// LPSS DMA + Package() {0x001EFFFF, 0, LNKD, 0 }, +// LPSS I2C #0 + Package() {0x001EFFFF, 3, LNKA, 0 }, +// LPSS I2C #1 + Package() {0x001EFFFF, 1, LNKB, 0 }, +// LPSS PCM + Package() {0x001EFFFF, 2, LNKC, 0 }, +// LPSS I2S +// LPSS HS-UART #0 +// LPSS HS-UART #1 +// LPSS SPI +// LPC Bridge +// +// SMBus Controller + Package() {0x001FFFFF, 1, LNKC, 0 }, +// +// PCIE Root Port #1 + Package() {0x001CFFFF, 0, LNKA, 0 }, +// PCIE Root Port #2 + Package() {0x001CFFFF, 1, LNKB, 0 }, +// PCIE Root Port #3 + Package() {0x001CFFFF, 2, LNKC, 0 }, +// PCIE Root Port #4 + Package() {0x001CFFFF, 3, LNKD, 0 }, + +// Host Bridge +// Mobile IGFX + Package() {0x0002FFFF, 0, LNKA, 0 }, + }) + + Name(AR00, Package() + { +// SD Host #0 - eMMC + Package() {0x0010FFFF, 0, 0, 16 }, +// SD Host #1 - SDIO + Package() {0x0011FFFF, 0, 0, 17 }, +// SD Host #2 - SD Card + Package() {0x0012FFFF, 0, 0, 18 }, +// SATA Controller + Package() {0x0013FFFF, 0, 0, 19 }, +// xHCI Host + Package() {0x0014FFFF, 0, 0, 20 }, +// Low Power Audio Engine + Package() {0x0015FFFF, 0, 0, 21 }, +// USB OTG + Package() {0x0016FFFF, 0, 0, 22 }, +// +// MIPI-HSI + Package() {0x0017FFFF, 0, 0, 23 }, +// +// LPSS2 DMA +// LPSS2 I2C #4 + Package() {0x0018FFFF, 0, 0, 17 }, +// LPSS2 I2C #1 +// LPSS2 I2C #5 + Package() {0x0018FFFF, 2, 0, 19 }, +// LPSS2 I2C #2 +// LPSS2 I2C #6 + Package() {0x0018FFFF, 3, 0, 18 }, +// LPSS2 I2C #3 +// LPSS2 I2C #7 + Package() {0x0018FFFF, 1, 0, 16 }, + +// SeC + Package() {0x001AFFFF, 0, 0, 21 }, +// +// High Definition Audio Controller + Package() {0x001BFFFF, 0, 0, 22 }, +// +// EHCI Controller + Package() {0x001DFFFF, 0, 0, 23 }, +// LPSS DMA + Package() {0x001EFFFF, 0, 0, 19 }, +// LPSS I2C #0 + Package() {0x001EFFFF, 3, 0, 16 }, +// LPSS I2C #1 + Package() {0x001EFFFF, 1, 0, 17 }, +// LPSS PCM + Package() {0x001EFFFF, 2, 0, 18 }, +// LPSS I2S +// LPSS HS-UART #0 +// LPSS HS-UART #1 +// LPSS SPI +// LPC Bridge +// +// SMBus Controller + Package() {0x001FFFFF, 1, 0, 18 }, +// +// PCIE Root Port #1 + Package() {0x001CFFFF, 0, 0, 16 }, +// PCIE Root Port #2 + Package() {0x001CFFFF, 1, 0, 17 }, +// PCIE Root Port #3 + Package() {0x001CFFFF, 2, 0, 18 }, +// PCIE Root Port #4 + Package() {0x001CFFFF, 3, 0, 19 }, +// Host Bridge +// Mobile IGFX + Package() {0x0002FFFF, 0, 0, 16 }, + }) + + Name(PR04, Package() + { +// PCIE Port #1 Slot + Package() {0x0000FFFF, 0, LNKA, 0 }, + Package() {0x0000FFFF, 1, LNKB, 0 }, + Package() {0x0000FFFF, 2, LNKC, 0 }, + Package() {0x0000FFFF, 3, LNKD, 0 }, + }) + + Name(AR04, Package() + { +// PCIE Port #1 Slot + Package() {0x0000FFFF, 0, 0, 16 }, + Package() {0x0000FFFF, 1, 0, 17 }, + Package() {0x0000FFFF, 2, 0, 18 }, + Package() {0x0000FFFF, 3, 0, 19 }, + }) + + Name(PR05, Package() + { +// PCIE Port #2 Slot + Package() {0x0000FFFF, 0, LNKB, 0 }, + Package() {0x0000FFFF, 1, LNKC, 0 }, + Package() {0x0000FFFF, 2, LNKD, 0 }, + Package() {0x0000FFFF, 3, LNKA, 0 }, + }) + + Name(AR05, Package() + { +// PCIE Port #2 Slot + Package() {0x0000FFFF, 0, 0, 17 }, + Package() {0x0000FFFF, 1, 0, 18 }, + Package() {0x0000FFFF, 2, 0, 19 }, + Package() {0x0000FFFF, 3, 0, 16 }, + }) + + Name(PR06, Package() + { +// PCIE Port #3 Slot + Package() {0x0000FFFF, 0, LNKC, 0 }, + Package() {0x0000FFFF, 1, LNKD, 0 }, + Package() {0x0000FFFF, 2, LNKA, 0 }, + Package() {0x0000FFFF, 3, LNKB, 0 }, + }) + + Name(AR06, Package() + { +// PCIE Port #3 Slot + Package() {0x0000FFFF, 0, 0, 18 }, + Package() {0x0000FFFF, 1, 0, 19 }, + Package() {0x0000FFFF, 2, 0, 16 }, + Package() {0x0000FFFF, 3, 0, 17 }, + }) + + Name(PR07, Package() + { +// PCIE Port #4 Slot + Package() {0x0000FFFF, 0, LNKD, 0 }, + Package() {0x0000FFFF, 1, LNKA, 0 }, + Package() {0x0000FFFF, 2, LNKB, 0 }, + Package() {0x0000FFFF, 3, LNKC, 0 }, + }) + + Name(AR07, Package() + { +// PCIE Port #4 Slot + Package() {0x0000FFFF, 0, 0, 19 }, + Package() {0x0000FFFF, 1, 0, 16 }, + Package() {0x0000FFFF, 2, 0, 17 }, + Package() {0x0000FFFF, 3, 0, 18 }, + }) + + Name(PR01, Package() + { +// PCI slot 1 + Package() {0x0000FFFF, 0, LNKF, 0 }, + Package() {0x0000FFFF, 1, LNKG, 0 }, + Package() {0x0000FFFF, 2, LNKH, 0 }, + Package() {0x0000FFFF, 3, LNKE, 0 }, +// PCI slot 2 + Package() {0x0001FFFF, 0, LNKG, 0 }, + Package() {0x0001FFFF, 1, LNKF, 0 }, + Package() {0x0001FFFF, 2, LNKE, 0 }, + Package() {0x0001FFFF, 3, LNKH, 0 }, +// PCI slot 3 + Package() {0x0002FFFF, 0, LNKC, 0 }, + Package() {0x0002FFFF, 1, LNKD, 0 }, + Package() {0x0002FFFF, 2, LNKB, 0 }, + Package() {0x0002FFFF, 3, LNKA, 0 }, +// PCI slot 4 + Package() {0x0003FFFF, 0, LNKD, 0 }, + Package() {0x0003FFFF, 1, LNKC, 0 }, + Package() {0x0003FFFF, 2, LNKF, 0 }, + Package() {0x0003FFFF, 3, LNKG, 0 }, + }) + + Name(AR01, Package() + { +// PCI slot 1 + Package() {0x0000FFFF, 0, 0, 21 }, + Package() {0x0000FFFF, 1, 0, 22 }, + Package() {0x0000FFFF, 2, 0, 23 }, + Package() {0x0000FFFF, 3, 0, 20 }, +// PCI slot 2 + Package() {0x0001FFFF, 0, 0, 22 }, + Package() {0x0001FFFF, 1, 0, 21 }, + Package() {0x0001FFFF, 2, 0, 20 }, + Package() {0x0001FFFF, 3, 0, 23 }, +// PCI slot 3 + Package() {0x0002FFFF, 0, 0, 18 }, + Package() {0x0002FFFF, 1, 0, 19 }, + Package() {0x0002FFFF, 2, 0, 17 }, + Package() {0x0002FFFF, 3, 0, 16 }, +// PCI slot 4 + Package() {0x0003FFFF, 0, 0, 19 }, + Package() {0x0003FFFF, 1, 0, 18 }, + Package() {0x0003FFFF, 2, 0, 21 }, + Package() {0x0003FFFF, 3, 0, 22 }, + }) +//--------------------------------------------------------------------------- +// List of IRQ resource buffers compatible with _PRS return format. +//--------------------------------------------------------------------------- +// Naming legend: +// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name. +// Note. PRSy name is generated if IRQ Link name starts from "LNK". +// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model. +//--------------------------------------------------------------------------- + Name(PRSA, ResourceTemplate() // Link name: LNKA + { + IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} + }) + Alias(PRSA,PRSB) // Link name: LNKB + Alias(PRSA,PRSC) // Link name: LNKC + Alias(PRSA,PRSD) // Link name: LNKD + Alias(PRSA,PRSE) // Link name: LNKE + Alias(PRSA,PRSF) // Link name: LNKF + Alias(PRSA,PRSG) // Link name: LNKG + Alias(PRSA,PRSH) // Link name: LNKH +//--------------------------------------------------------------------------- +// Begin PCI tree object scope +//--------------------------------------------------------------------------- + + Device(PCI0) // PCI Bridge "Host Bridge" + { + Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy + Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID + Name(_ADR, 0x00000000) + Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope + Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus + Name(_UID, 0x0000) // Unique Bus ID, optional + Name(_DEP, Package(0x1) + { + PEPD + }) + + Method(_PRT,0) + { + If(PICM) {Return(AR00)} // APIC mode + Return (PR00) // PIC Mode + } // end _PRT + + include("HOST_BUS.ASL") + Device(LPCB) // LPC Bridge + { + Name(_ADR, 0x001F0000) + include("LpcB.asl") + } // end "LPC Bridge" + + } // end PCI0 Bridge "Host Bridge" +} // end _SB scope diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl new file mode 100644 index 0000000000..5f269be615 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl @@ -0,0 +1,830 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +// Define the following External variables to prevent a WARNING when +// using ASL.EXE and an ERROR when using IASL.EXE. + +External(PDC0) +External(PDC1) +External(PDC2) +External(PDC3) +External(CFGD) +External(\_PR.CPU0._PPC, IntObj) +External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj) +External(\_SB.STR3, DeviceObj) +External(\_SB.I2C1.BATC, DeviceObj) +External(\_SB.DPTF, DeviceObj) +External(\_SB.TCHG, DeviceObj) +External(\_SB.IAOE.PTSL) +External(\_SB.IAOE.WKRS) + +// +// Create a Global MUTEX. +// +Mutex(MUTX,0) + + + +// Port 80h Update: +// Update 8 bits of the 32-bit Port 80h. +// +// Arguments: +// Arg0: 0 = Write Port 80h, Bits 7:0 Only. +// 1 = Write Port 80h, Bits 15:8 Only. +// 2 = Write Port 80h, Bits 23:16 Only. +// 3 = Write Port 80h, Bits 31:24 Only. +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Method(P8XH,2,Serialized) +{ + If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. + { + Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) + } + + If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. + { + Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) + } + + If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. + { + Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) + } + + If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. + { + Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) + } + +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. +// +OperationRegion (SPRT, SystemIO, 0xB2, 2) +Field (SPRT, ByteAcc, Lock, Preserve) +{ + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 = 8259 +// 1 = IOAPIC + +Method(\_PIC,1) +{ + Store(Arg0,GPIC) + Store(Arg0,PICM) +} + +OperationRegion(SWC0, SystemIO, 0x610, 0x0F) +Field(SWC0, ByteAcc, NoLock, Preserve) +{ + G1S, 8, //SWC GPE1_STS + Offset(0x4), + G1E, 8, + Offset(0xA), + G1S2, 8, //SWC GPE1_STS_2 + G1S3, 8 //SWC GPE1_STS_3 +} + +OperationRegion (SWC1, SystemIO, \PMBS, 0x2C) +Field(SWC1, DWordAcc, NoLock, Preserve) +{ + Offset(0x20), + G0S, 32, //GPE0_STS + Offset(0x28), + G0EN, 32 //GPE0_EN +} + +// Prepare to Sleep. The hook is called when the OS is about to +// enter a sleep state. The argument passed is the numeric value of +// the Sx state. + +Method(_PTS,1) +{ + Store(0,P80D) // Zero out the entire Port 80h DWord. + P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. + + //clear the 3 SWC status bits + Store(Ones, G1S3) + Store(Ones, G1S2) + Store(1, G1S) + + //set SWC GPE1_EN + Store(1,G1E) + + //clear GPE0_STS + Store(Ones, G0S) + + + If(LEqual(Arg0,3)) // If S3 Suspend + { + // + // Disable Digital Thermal Sensor function when doing S3 suspend + // + If(CondRefOf(DTSE)) + { + If(LGreaterEqual(DTSE, 0x01)) + { + Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI + Store(0xD0, SSMP) // DTS SW SMI + } + } + } +} + +// Wake. This hook is called when the OS is about to wake from a +// sleep state. The argument passed is the numeric value of the +// sleep state the system is waking from. +Method(_WAK,1,Serialized) +{ + P8XH(1,0xAB) // Beginning of _WAK. + + Notify(\_SB.PWRB,0x02) + + If(NEXP) + { + // Reinitialize the Native PCI Express after resume + If(And(OSCC,0x02)) + { + \_SB.PCI0.NHPG() + } + + If(And(OSCC,0x04)) // PME control granted? + { + \_SB.PCI0.NPME() + } + } + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + + + // If CMP is enabled, we may need to restore the C-State and/or + // P-State configuration, as it may have been saved before the + // configuration was finalized based on OS/driver support. + // + // CFGD[24] = Two or more cores enabled + // + If(And(CFGD,0x01000000)) + { + // + // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if + // C-States are enabled. + // + // CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled + // + // + } + + // Windows XP SP2 does not properly restore the P-State + // upon resume from S4 or S3 with degrade modes enabled. + // Use the existing _PPC methods to cycle the available + // P-States such that the processor ends up running at + // the proper P-State. + // + // Note: For S4, another possible W/A is to always boot + // the system in LFM. + // + If(LEqual(OSYS,2002)) + { + If(And(CFGD,0x01)) + { + If(LGreater(\_PR.CPU0._PPC,0)) + { + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + Else + { + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + } + } + } + Return(Package() {0,0}) +} + +// Power Notification: +// Perform all needed OS notifications during a +// Power Switch. +// +// Arguments: +// None +// +// Return Value: +// None + +Method(PNOT,0,Serialized) +{ + // If MP enabled and driver support is present, notify all + // processors. + + If(MPEN) + { + If(And(PDC0,0x0008)) + { + Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC. + + If(And(PDC0,0x0010)) + { + Sleep(100) + Notify(\_PR.CPU0,0x81) // Eval _CST. + } + } + + If(And(PDC1,0x0008)) + { + Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC. + + If(And(PDC1,0x0010)) + { + Sleep(100) + Notify(\_PR.CPU1,0x81) // Eval _CST. + } + } + + If(And(PDC2,0x0008)) + { + Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC. + + If(And(PDC2,0x0010)) + { + Sleep(100) + Notify(\_PR.CPU2,0x81) // Eval _CST. + } + } + + If(And(PDC3,0x0008)) + { + Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC. + + If(And(PDC3,0x0010)) + { + Sleep(100) + Notify(\_PR.CPU3,0x81) // Eval _CST. + } + } + } + Else + { + Notify(\_PR.CPU0,0x80) // Eval _PPC. + Sleep(100) + Notify(\_PR.CPU0,0x81) // Eval _CST + } +} + +// +// System Bus +// +Scope(\_SB) +{ + Name(CRTT, 110) // Processor critical temperature + Name(ACTT, 77) // Active temperature limit for processor participant + Name(GCR0, 70) // Critical temperature for Generic participant 0 in degree celsius + Name(GCR1, 70) // Critical temperature for Generic participant 1 in degree celsius + Name(GCR2, 70) // Critical temperature for Generic participant 2 in degree celsius + Name(GCR3, 70) // Critical temperature for Generic participant 3 in degree celsius + Name(GCR4, 70) // Critical temperature for Generic participant 4 in degree celsius + Name(GCR5, 70) // Critical temperature for Generic participant 5 in degree celsius + Name(GCR6, 70) // Critical temperature for Generic participant 6 in degree celsius + Name(PST0, 60) // Passive temperature limit for Generic Participant 0 in degree celsius + Name(PST1, 60) // Passive temperature limit for Generic Participant 1 in degree celsius + Name(PST2, 60) // Passive temperature limit for Generic Participant 2 in degree celsius + Name(PST3, 60) // Passive temperature limit for Generic Participant 3 in degree celsius + Name(PST4, 60) // Passive temperature limit for Generic Participant 4 in degree celsius + Name(PST5, 60) // Passive temperature limit for Generic Participant 5 in degree celsius + Name(PST6, 60) // Passive temperature limit for Generic Participant 6 in degree celsius + Name(LPMV, 3) + Name(PDBG, 0) // DPTF Super debug option + Name(PDPM, 1) // DPTF DPPM enable + Name(PDBP, 1) // DPTF DBPT enable (dynamic battery protection technology) + Name(DLPO, Package() + { + 0x1, // Revision + 0x1, // LPO Enable + 0x1, // LPO StartPState + 25, // LPO StepSize + 0x1, // + 0x1, // + }) + Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change + // or it is from Graphics driver. Value of 1 is for DPTF else it is 0 + + Method(_INI,0) + { + // NVS has stale DTS data. Get and update the values + // with current temperatures. Note that this will also + // re-arm any AP Thermal Interrupts. + // Read temperature settings from global NVS + Store(DPCT, CRTT) + Store(Subtract(DPPT, 8), ACTT) // Active Trip point = Passive trip point - 8 + Store(DGC0, GCR0) + Store(DGC0, GCR1) + Store(DGC1, GCR2) + Store(DGC1, GCR3) + Store(DGC1, GCR4) + Store(DGC2, GCR5) + Store(DGC2, GCR6) + Store(DGP0, PST0) + Store(DGP0, PST1) + Store(DGP1, PST2) + Store(DGP1, PST3) + Store(DGP1, PST4) + Store(DGP2, PST5) + Store(DGP2, PST6) + // Read Current low power mode setting from global NVS + Store(DLPM, LPMV) + + + // Update DPTF Super Debug option + Store(DDBG, PDBG) + + + // Update DPTF LPO Options + Store(LPOE, Index(DLPO,1)) + Store(LPPS, Index(DLPO,2)) + Store(LPST, Index(DLPO,3)) + Store(LPPC, Index(DLPO,4)) + Store(LPPF, Index(DLPO,5)) + Store(DPME, PDPM) + } + + // Define a (Control Method) Power Button. + Device(PWRB) + { + Name(_HID,EISAID("PNP0C0C")) + + // GPI_SUS0 = GPE16 = Waketime SCI. The PRW isn't working when + // placed in any of the logical locations ( PS2K, PS2M), + // so a Power Button Device was created specifically + // for the WAKETIME_SCI PRW. + + Name(_PRW, Package() {16,4}) + } + + Device(SLPB) + { + Name(_HID, EISAID("PNP0C0E")) + } // END SLPB + + Scope(PCI0) + { + Method(_INI,0) + { + // Determine the OS and store the value, where: + // + // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. + // OSYS = 2012 = Windows 8 and Windows Server 2012. + // + // Assume Windows 7 at a minimum. + + Store(2009,OSYS) + + // Check for a specific OS which supports _OSI. + + If(CondRefOf(\_OSI,Local0)) + { + // Linux returns _OSI = TRUE for numerous Windows + // strings so that it is fully compatible with + // BIOSes available in the market today. There are + // currently 2 known exceptions to this model: + // 1) Video Repost - Linux supports S3 without + // requireing a Driver, meaning a Video + // Repost will be required. + // 2) On-Screen Branding - a full CMT Logo + // is limited to the WIN2K and WINXP + // Operating Systems only. + + // Use OSYS for Windows Compatibility. + If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2 + { + Store(2009,OSYS) + } + If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012 + { + Store(2012,OSYS) + } + If(\_OSI("Windows 2013")) //Windows Blue + { + Store(2013,OSYS) + } + + // + // If CMP is enabled, enable SMM C-State + // coordination. SMM C-State coordination + // will be disabled in _PDC if driver support + // for independent C-States deeper than C1 + // is indicated. + } + } + + Method(NHPG,0,Serialized) + { + + } + + Method(NPME,0,Serialized) + { + + } + } // end Scope(PCI0) + + Device (GPED) //virtual GPIO device for ASL based AC/Battery/Expection notification + { + Name (_ADR, 0) + Name (_HID, "INT0002") + Name (_CID, "INT0002") + Name (_DDN, "Virtual GPIO controller" ) + Name (_UID, 1) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9 + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0x0) + } + + Method (_AEI, 0x0, Serialized) + { + Name(RBUF, ResourceTemplate() + { + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2 + }) + Return(RBUF) + } + + Method(_E02) // _Exx method will be called when interrupt is raised + { + If (LEqual (PWBS, 1)) + { + Store (1, PWBS) //Clear PowerButton Status + } + If (LEqual (PMEB, 1)) + { + Store (1, PMEB) //Clear PME_B0_STS + } + If (LEqual (\_SB.PCI0.SATA.PMES, 1)) + { + Store (1, \_SB.PCI0.SATA.PMES) + Notify (\_SB.PCI0.SATA, 0x02) + } + // + // eMMC 4.41 + // + If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1))) + { + Store (1, \_SB.PCI0.EM41.PMES) + Notify (\_SB.PCI0.EM41, 0x02) + } + + // + // eMMC 4.5 + // + If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1))) + { + Store (1, \_SB.PCI0.EM45.PMES) + Notify (\_SB.PCI0.EM45, 0x02) + } + + If (LEqual(HDAD, 0)) + { + If (LEqual (\_SB.PCI0.HDEF.PMES, 1)) + { + Store (1, \_SB.PCI0.HDEF.PMES) + Notify (\_SB.PCI0.HDEF, 0x02) + } + } + + If (LEqual (\_SB.PCI0.EHC1.PMES, 1)) + { + Store (1, \_SB.PCI0.EHC1.PMES) + Notify (\_SB.PCI0.EHC1, 0x02) + } + If (LEqual (\_SB.PCI0.XHC1.PMES, 1)) + { + Store (1, \_SB.PCI0.XHC1.PMES) + Notify (\_SB.PCI0.XHC1, 0x02) + } + If (LEqual (\_SB.PCI0.SEC0.PMES, 1)) + { + Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES) + Notify (\_SB.PCI0.SEC0, 0x02) + } + } + } // Device (GPED) + + //-------------------- + // GPIO + //-------------------- + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT33FC") + Name (_CID, "INT33B2") + Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" ) + Name (_UID, 1) + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49} + + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + // + // GPO driver will report present if any of below New IO bus exist + // + If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist + { Return(0xF) } + If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist + { Return(0xF) } + If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist + { Return(0xF) } + If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist + { Return(0xF) } + If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist + { Return(0xF) } + If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist + { Return(0xF) } + If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist + { Return(0xF) } + If (LEqual(L27D, 0)) // LPIO2 I2C #7 exist + { Return(0xF) } + + Return(0x0) + } + + // Track status of GPIO OpRegion availability for this controller + Name(AVBL, 0) + Method(_REG,2) + { + If (Lequal(Arg0, 8)) + { + Store(Arg1, ^AVBL) + } + } + + OperationRegion(GPOP, SystemIo, \GPBS, 0x50) + Field(GPOP, ByteAcc, NoLock, Preserve) { + Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h + , 21, + BTD3, 1, //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP + Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h + , 30, + SHD3, 1 //GPIO_S0_SC_95 - SENS_HUB_RST_N + } + + + + } // Device (GPO0) + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT33FC") + Name (_CID, "INT33B2") + Name (_DDN, "ValleyView2 GPNCORE controller" ) + Name (_UID, 2) + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48} + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(\_SB.GPO0._STA) + } + } // Device (GPO1) + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT33FC") + Name (_CID, "INT33B2") + Name (_DDN, "ValleyView2 GPSUS controller" ) + Name (_UID, 3) + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50} + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(^^GPO0._STA) + } + + // Track status of GPIO OpRegion availability for this controller + Name(AVBL, 0) + Method(_REG,2) + { + If (Lequal(Arg0, 8)) + { + Store(Arg1, ^AVBL) + } + } + //Manipulate GPIO line using GPIO operation regions. + Name (GMOD, ResourceTemplate () //One method of creating a Connection for OpRegion accesses in Field definitions + { + //is creating a named object that refers to the connection attributes + GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21} //sus 21+128 BT+WLAN_ENABLE + }) + + OperationRegion(GPOP, SystemIo, \GPBS, 0x100) + Field(GPOP, ByteAcc, NoLock, Preserve) { + Offset(0x88), // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h + , 20, + WFD3, 1 + } + + + } // Device (GPO2) + include ("PchScc.asl") + include ("PchLpss.asl") + + Scope(I2C7) + { + + } //End Scope(I2C7) + + // + // Device for Message Bus Interface + // + Device(MBID) + { + Name(_HID, "INT33BD") + Name(_CID, "INT33BD") + Name(_HRV, 2)//different from CLT's + Name(_UID, 1) + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed ( + ReadWrite, + 0xE00000D0, // Address Base + 0xC, // Address Length (MCR/MDR/MCRX) + ) + }) + Return (RBUF) + } + + + // + // custom opregion for MBI access + // + OperationRegion (REGS, 0x87, 0x0, 0x30) + Field (REGS, DWordAcc, NoLock, Preserve) + { + PORT, 32, // Message Port + REG, 32, // Message Target Register Address + DATA, 32, // Message Data + MASK, 32, // Mask bits for modify operation + BE, 32, // Message Write Byte enables: 0 - BYTE; 1 - WORD; 2 - DWORD + OP, 32 // Operations: 0 - read; 1 - write; 2 - modify + } + + // + // availability of the custom opregion + // + Name (AVBL, 0) + Method(_REG,2) + { + If (Lequal(Arg0, 0x87)) + { + Store(Arg1, ^AVBL) + } + } + + // + // Method Name: READ + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Return Value: + // DATA + // + Method(READ, 3, Serialized) + { + Store(0xFFFFFFFF , Local0) + If (Lequal (AVBL, 1)) + { + Store(0, OP) // must be set at first, do not change! + Store(Arg0, PORT) + Store(Arg1, REG) + Store(Arg2, BE) + Store(DATA, Local0) + } + return(Local0) + } + + // + // Method Name: WRIT + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Arg3: DATA + // Return Value: + // NONE + // + Method(WRIT, 4, Serialized) + { + If (Lequal (AVBL, 1)) + { + Store(1, OP) // must be set at first, do not change! + Store(Arg0, PORT) + Store(Arg1, REG) + Store(Arg2, BE) + Store(Arg3, DATA) + } + } + + // + // Method Name: MODI + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Arg3: DATA + // Arg4: MASK + // Return Value: + // NONE + // + Method(MODI, 5, Serialized) + { + If (Lequal (AVBL, 1)) + { + Store(2, OP) // must be set at first, do not change! + Store(Arg0, PORT) + Store(Arg1, REG) + Store(Arg2, BE) + Store(Arg3, DATA) + Store(Arg4, MASK) + } + } + } + + +} // end Scope(\_SB) + +Name(PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method + diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl new file mode 100644 index 0000000000..eb607c6b2e --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl @@ -0,0 +1,203 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "Msg_Rtd3", + 0x1000 +) +{ + External(RTD3) //flag if RTD3 is enabled + + If(LEqual(RTD3,1)) + { + Scope (\_SB) + { + Name(OSCI, 0) // \_SB._OSC DWORD2 input + Name(OSCO, 0) // \_SB._OSC DWORD2 output + + //Arg0 -- A buffer containing UUID + //Arg1 -- An Interger containing a Revision ID of the buffer format + //Arg2 -- An interger containing a count of entries in Arg3 + //Arg3 -- A buffer containing a list of DWORD capacities + Method(_OSC, 4, NotSerialized) + { + // Check for proper UUID + If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + CreateDWordField(Arg3,0,CDW1) //bit1,2 is always clear + CreateDWordField(Arg3,4,CDW2) //Table 6-147 from ACPI spec + + Store(CDW2, OSCI) // Save DWord2 + Or(OSCI, 0x4, OSCO) // Only allow _PR3 support + + If(LNotEqual(Arg1,One)) + { + Or(CDW1,0x08,CDW1) // Unknown revision + } + + If(LNotEqual(OSCI, OSCO)) + { + Or(CDW1,0x10,CDW1) // Capabilities bits were masked + } + + Store(OSCO, CDW2) // Replace DWord2 + Return(Arg3) + } Else + { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + }// End _OSC + } + }//end of RTD3 condition + + + //USB RTD3 code + If(LEqual(RTD3,1)) + { + Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR13) + { + Name(_PR0, Package() {\PR34}) + Name(_PR3, Package() {\PR34}) + + Method(_S0W, 0) + { + If(And(\_SB.OSCO, 0x04)) // PMEs can be genrated from D3cold + { + Return(4) // OS comprehends D3cold, as described via \_SB._OSC + } Else + { + Return(3) + } + } // End _S0W + } + + Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR14) + { + Name(_PR0, Package() {\PR34}) + Name(_PR3, Package() {\PR34}) + + Method(_S0W, 0) + { + If(And(\_SB.OSCO, 0x04)) + { + Return(4) + } Else + { + Return(3) + } + } // End _S0W + } + + + Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR15) + { + Name(_PR0, Package() {\PR56}) + Name(_PR3, Package() {\PR56}) + + Method(_S0W, 0) + { + If(And(\_SB.OSCO, 0x04)) + { + Return(4) + } Else + { + Return(3) + } + } // End _S0W + } + + Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR16) + { + Name(_PR0, Package() {\PR56}) + Name(_PR3, Package() {\PR56}) + + Method(_S0W, 0) + { + If(And(\_SB.OSCO, 0x04)) + { + Return(4) + } Else + { + Return(3) + } + } // End _S0W + } + + Scope(\_SB.PCI0.XHC1) // XHCI host only controller + { + + Method(_PS0,0,Serialized) // set device into D0 state + { + } + + Method(_PS3,0,Serialized) // place device into D3H state + { + //write to PMCSR + } + + Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system. + { + } + } + + Scope(\_SB.PCI0.XHC1.RHUB.HS01) + { + + } + + Scope(\_SB.PCI0.XHC1.RHUB.SSP1) + { + + } + + Scope(\_SB.PCI0.XHC2) // OTG + { + + Method(_PS0,0,Serialized) // set device into D0 state + { + } + + Method(_PS3,0,Serialized) // place device into D3H state + { + //write to PMCSR + } + + Method(_DSW, 3,Serialized) // enable or disable the device’s ability to wake a sleeping system. + { + } + } + + Scope(\_SB.PCI0.XHC2.RHUB.HS01) + { + + } + + Scope(\_SB.PCI0.XHC2.RHUB.SSP1) + { + + } + } //If(LEqual(RTD3,1)) USB + +}//end of SSDT diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL new file mode 100644 index 0000000000..e63f5bc69d --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL @@ -0,0 +1,138 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + +// THERMAL.ASL represents a Thermal Zone to be used for testing on the +// Customer Reference Boards. + +External(\_SB.DPTF.CTOK, MethodObj) + +Scope(\_TZ) +{ + + // Thermal Zone 1 = DTS Thermal Zone. + + ThermalZone(TZ01) + { + // Return the temperature at which the OS must perform a Critcal + // Shutdown. + + Method(_CRT,0,Serialized) + { + Return(Add(2732,Multiply(CRTT,10))) + } + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + + Method(_SCP,1,Serialized) + { + Store(Arg0,CTYP) + } + + // _TMP (Temperature) + // + // Return the highest of the CPU temperatures to the OS. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + If(DTSE) + { + If(LGreater(DTS2, DTS1)) + { + Store(DTS2,Local0) + } else + { + Store(DTS1,Local0) + } + Return(Add(2732,Multiply(Local0,10))) + // + // Else return a static value if both EC and DTS are unavailable. + // + } Else + { + Return(3000) // (3000-2732)/10 = 26.8 degree C + } + } + + // Return the Processor(s) used for Passive Cooling. + + Method(_PSL,0,Serialized) + { + If(LEqual(MPEN, 4)) + { + // CMP - Throttling controls all four logical CPUs. + Return(Package() {\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3}) + } + + If(MPEN) + { + // CMP - Throttling controls both CPUs. + + Return(Package() {\_PR.CPU0,\_PR.CPU1}) + } + + Return(Package() {\_PR.CPU0}) + } + + // Returns the temperature at which the OS initiates CPU throttling. + + Method(_PSV,0,Serialized) + { + Return(Add(2732,Multiply(PSVT,10))) + } + + // Returns TC1 value used in the passive cooling formula. + + Method(_TC1,0,Serialized) + { + Return(TC1V) + } + + // Returns TC2 value used in the passive cooling formula. + + Method(_TC2,0,Serialized) + { + Return(TC2V) + } + + // Returns the sampling period used in the passive cooling formula. + + Method(_TSP,0,Serialized) + { + Return(TSPV) + } + + // Returns Hot Temperature + + Method(_HOT,0,Serialized) + { + Subtract(CRTT, 5, Local0) + Return(Add(2732,Multiply(Local0,10))) + } + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl new file mode 100644 index 0000000000..020bc97131 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl @@ -0,0 +1,99 @@ +/************************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* MPG-MSAE *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. *; +;* *; +;* This program and the accompanying materials are licensed and made available under*; +;* the terms and conditions of the BSD License that accompanies this distribution. *; +;* The full text of the license may be found at *; +;* http://opensource.org/licenses/bsd-license.php. *; +;* *; +;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, *; +;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. *; +;* *; +;* *; +;* This program has been developed by Intel Corporation. *; +;* Licensee has Intel's permission to incorporate this source code *; +;* into their product, royalty free. This source code may NOT be *; +;* redistributed to anyone without Intel's written permission. *; +;* *; +;* Intel specifically disclaims all warranties, express or *; +;* implied, and all liability, including consequential and other *; +;* indirect damages, for the use of this code, including liability *; +;* for infringement of any proprietary rights, and including the *; +;* warranties of merchantability and fitness for a particular *; +;* purpose. Intel does not assume any responsibility for any *; +;* errors which may appear in this code nor any responsibility to *; +;* update it. *; +;* *; +;* Version: See README.TXT *; +;* *; +;************************************************************************************/ + +// +// _DSM : Device Specific Method supporting USB Sideband Deferring function +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index +// Arg3: Package Parameters +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) +{ + + If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8"))) + { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) + { + // + // Standard query - A bitmask of functions supported + // Supports function 0-2 + // + Case (0) + { + if (LEqual(Arg1, 1)) // test Arg1 for the revision + { + Return (Buffer () {0x07}) + } + else + { + Return (Buffer () {0}) + } + } + // + // USB Sideband Deferring Support + // 0: USB Sideband Deferring not supported on this device + // 1: USB Sideband Deferring supported + // + Case (1) + { + if (LEqual(SDGV,0xFF)) // check for valid GPE vector + { + Return (0) + } + else + { + Return (1) + } + } + // + // GPE Vector + // Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device + // + Case (2) + { + Return (SDGV) + } + } + } + + Return (0) +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl new file mode 100644 index 0000000000..46d0aba7a9 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl @@ -0,0 +1,40 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Baytrail *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + + + + +// Brightness Notification: +// Generate a brightness related notification +// to the LFP if its populated. +// +// Arguments: +// Arg0: Notification value. +// +// Return Value: +// None +Method(BRTN,1,Serialized) +{ + If(LEqual(And(DIDX,0x0F00),0x400)) + { + Notify(\_SB.PCI0.GFX0.DD1F,Arg0) + } +} diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl new file mode 100644 index 0000000000..66c741f9c4 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl @@ -0,0 +1,45 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + VLV.ASL + +Abstract: + + Baytrail PCI configuration space definition. + +--*/ +Scope (\_SB.PCI0) +{ + + Device(GFX0) // Mobile I.G.D + { + Name(_ADR, 0x00020000) + + Method(GDEP, 0) + { + If(LEqual(OSYS,2013)) + { + Name(_DEP, Package(0x1) + { + PEPD + }) + } + } + + include("INTELGFX.ASL") + include("INTELISPDev2.ASL") + } // end "Mobile I.G.D" +}//end scope diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl new file mode 100644 index 0000000000..8df5b315d5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl @@ -0,0 +1,45 @@ +/**************************************************************************; +;* *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *; +; +; This program and the accompanying materials are licensed and made available under +; the terms and conditions of the BSD License that accompanies this distribution. +; The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;* *; +;* *; +;**************************************************************************/ + +Name(PMBS, 0x400) // ASL alias for ACPI I/O base address. +Name(SMIP, 0xb2) // I/O port to trigger SMI +Name(GPBS, 0x500) // GPIO Register Block address +Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled +Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded +Name(PFDR, 0xfed03034) // PMC Function Disable Register +Name(PMCB, 0xfed03000) // PMC Base Address +Name(PCLK, 0xfed03060) // PMC Clock Control Register +Name(PUNB, 0xfed05000) // PUNIT Base Address +Name(IBAS, 0xfed08000) // ILB Base Address +Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address) +Name(SRCL, 0x1000) // RCBA length +Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use +Name(PEBS, 0xe0000000) // PCIe Base +Name(PELN, 0x10000000) // +Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code. +Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code. +Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31] +Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control +Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control +Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control +Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control +Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control + diff --git a/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h b/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h new file mode 100644 index 0000000000..24faf23c1e --- /dev/null +++ b/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h @@ -0,0 +1,30 @@ +/*++ + +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + Vlv2DeviceRefCodeTokenSpace.h + +Abstract: + + Interface definition details for GUID. + +--*/ +#ifndef __VLV2_REF_CODE__PKG_TOKEN_SPACE_GUID_H__ +#define __VLV2_REF_CODE__PKG_TOKEN_SPACE_GUID_H__ + +#define EFI_VLV_TOKEN_SPACE_GUID \ + { 0xca452c68, 0xdf0c, 0x45c9, {0x82, 0xfb, 0xea, 0xe4, 0x2b, 0x31, 0x29, 0x46}} +extern EFI_GUID gEfiVLVTokenSpaceGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h new file mode 100644 index 0000000000..535258f774 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h @@ -0,0 +1,33 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + PowerManagementAcpiTableStorage.h + +Abstract: + + GUID definition for the Power Management ACPI table storage file name + +--*/ + +#ifndef _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_ +#define _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_ + +#define POWER_MANAGEMENT_ACPI_TABLE_STORAGE_GUID \ + { 0x161be597, 0xe9c5, 0x49db, 0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda } + +extern EFI_GUID gPowerManagementAcpiTableStorageGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h new file mode 100644 index 0000000000..7b0c4193e6 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h @@ -0,0 +1,110 @@ + +/*++ + +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvPolicy.h + +Abstract: + + Interface definition details between ValleyView MRC and platform drivers during PEI phase. + +--*/ + +#ifndef _VLV_POLICY_PPI_H_ +#define _VLV_POLICY_PPI_H_ + +// +// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3} +// +#define VLV_POLICY_PPI_GUID \ + { \ + 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \ + } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gVlvPolicyPpiGuid; + +// +// PPI revision number +// Any backwards compatible changes to this PPI will result in an update in the revision number +// Major changes will require publication of a new PPI +// +#define MRC_PLATFORM_POLICY_PPI_REVISION 1 + +#ifndef MAX_SOCKETS +#define MAX_SOCKETS 4 +#endif + +#define S3_TIMING_DATA_LEN 9 +#define S3_READ_TRAINING_DATA_LEN 16 +#define S3_WRITE_TRAINING_DATA_LEN 12 + +#ifndef S3_RESTORE_DATA_LEN +#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN) +#endif // S3_RESTORE_DATA_LEN +#pragma pack(1) +// +// MRC Platform Data Structure +// +typedef struct { + UINT8 SpdAddressTable[MAX_SOCKETS]; + UINT8 TSonDimmSmbusAddress[MAX_SOCKETS]; + + UINT16 SmbusBar; + UINT32 IchRcba; + UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode) + UINT32 WdbRegionSize; + UINT32 SmBusAddress; + UINT8 UserBd; + UINT8 PlatformType; + UINT8 FastBoot; + UINT8 DynSR; +} VLV_PLATFORM_DATA; + + +typedef struct { + UINT16 MmioSize; + UINT16 GttSize; + UINT8 IgdDvmt50PreAlloc; + UINT8 PrimaryDisplay; + UINT8 PAVPMode; + UINT8 ApertureSize; +} GT_CONFIGURATION; + +typedef struct { + UINT8 EccSupport; + UINT16 DdrFreqLimit; + UINT8 MaxTolud; +} MEMORY_CONFIGURATION; + + +// +// MRC Platform Policiy PPI +// +typedef struct _VLV_POLICY_PPI { + UINT8 Revision; + VLV_PLATFORM_DATA PlatformData; + GT_CONFIGURATION GtConfig; + MEMORY_CONFIGURATION MemConfig; + VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE + UINT8 ISPEn; //ISP (IUNIT) Device Enabled + UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS +} VLV_POLICY_PPI; + +#pragma pack() + +#endif // _VLV_POLICY_PPI_H_ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h new file mode 100644 index 0000000000..4b9f9921a0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h @@ -0,0 +1,138 @@ +/** + Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +/*++ + +Module Name: + + PpmPlatformPolicy.h + +Abstract: + + Interface definition details between PPM and platform drivers during DXE phase. + +--*/ +#ifndef _PPM_PLATFORM_POLICY_H_ +#define _PPM_PLATFORM_POLICY_H_ + +// +// PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E} +// +#define PPM_PLATFORM_POLICY_PROTOCOL_GUID \ + {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e} + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPpmPlatformPolicyProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL; + +// +// Protocol revision number +// Any backwards compatible changes to this protocol will result in an update in the revision number +// Major changes will require publication of a new protocol +// +// Revision 1: Original version +// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable +// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn) +// Revision 4: Added support for extended C6 residency enabling +// +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION 1 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 + +// +// Define maximum number of custom VID states supported +// +#ifndef MAX_CUSTOM_VID_TABLE_STATES +#define MAX_CUSTOM_VID_TABLE_STATES 6 +#endif +// +// Custom VID table +// +typedef struct { + UINT8 VidNumber; + UINT32 VidCpuid; + UINT16 VidMaxRatio; + UINT16 VidMaxVid; + UINT16 StateRatio[MAX_CUSTOM_VID_TABLE_STATES]; + UINT16 StateVid[MAX_CUSTOM_VID_TABLE_STATES]; +} PPM_CUSTOM_VID_TABLE; + +// +// PPM functional enables +// +typedef struct { + UINT8 EnableGv :1; // 0: Disabled; 1: Enabled + UINT8 EnableCx :1; + UINT8 EnableCxe :1; + UINT8 EnableC4 :1; + UINT8 EnableC6 :1; + UINT8 EnableC7 :1; + UINT8 EnableTm :1; + UINT8 Reserve00 :1; + UINT8 Reserve01 :1; + UINT8 EnableTurboMode :1; + UINT8 PowerLimit2 :1; + UINT8 EnableProcHot :1; + UINT8 Reserve02 :1; + UINT8 EnableCMP :1; + UINT8 TStatesEnable :1; + UINT8 Reserve03 :1; + UINT8 Reserve04 ; + +} PPM_FUNCTION_ENABLES; + + +// +// PPM Turbo settings +// +typedef struct _PPM_TURBO_SETTINGS { + UINT16 PowerLimit1; + UINT32 PowerLimit1Time; + UINT16 PowerLimit2; + UINT8 TurboPowerLimitLock; +} PPM_TURBO_SETTINGS; + +// +// Platform Policy +// +typedef struct _PPM_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + PPM_FUNCTION_ENABLES FunctionEnables; + PPM_CUSTOM_VID_TABLE CustomVidTable; + PPM_TURBO_SETTINGS TurboSettings; + + UINT8 Reserve00; + UINT8 Reserve01; + UINT8 Reserve02; + UINT8 Reserve03; + UINT8 Reserve04; + UINT8 Reserve05; + UINT8 Reserve06; + + UINT8 S3RestoreMsrSwSmiNumber; + UINT8 Reserve07; + UINT32 Reserve08; + UINT8 Reserve09; + // + // Primary and Secondary Plane Current Limits + // + UINT16 Reserve10; + UINT8 Reserve11; +} PPM_PLATFORM_POLICY_PROTOCOL; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h new file mode 100644 index 0000000000..c8085014e1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h @@ -0,0 +1,61 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Types.h + +Abstract: + + This file include all the external data types. + +--*/ + +#ifndef _TYPES_H_ +#define _TYPES_H_ + + + +// +// Modifiers to abstract standard types to aid in debug of problems +// +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile + +// +// Constants. They may exist in other build structures, so #ifndef them. +// +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif + +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +#ifndef NULL +#define NULL ((VOID *) 0) +#endif + +typedef UINT32 STATUS; +#define SUCCESS 0 +#define FAILURE 0xFFFFFFFF + +#ifndef MRC_DEADLOOP +#define MRC_DEADLOOP() while (TRUE) +#endif + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf new file mode 100644 index 0000000000..72ed9c3199 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf @@ -0,0 +1,45 @@ +# +#/*++ +# +#Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#Module Name: +# +# PowerManagementAcpiTables.inf +# +#Abstract: +# +# Component description file for the ACPI tables +# +#--*/ + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = PowerManagementAcpiTables2 + FILE_GUID = 161BE597-E9C5-49DB-AE50-C462AB54EEDA + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + + +[sources.common] + Ssdt/Cpu0Cst.asl + Ssdt/Cpu0Ist.asl + Ssdt/Cpu0Tst.asl + Ssdt/ApCst.asl + Ssdt/ApIst.asl + Ssdt/ApTst.asl + Ssdt/CpuPm.asl + +[Packages] + MdePkg/MdePkg.dec diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl new file mode 100644 index 0000000000..185750ee24 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl @@ -0,0 +1,116 @@ +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: CPU1CST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + + +DefinitionBlock ( + "APCST.aml", + "SSDT", + 1, + "PmRef", + "ApCst", + 0x3000 + ) +{ +External(\_PR.CPU1, DeviceObj) +External(\_PR.CPU2, DeviceObj) +External(\_PR.CPU3, DeviceObj) +External(\_PR.CPU0._CST) + + Scope(\_PR.CPU1) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU2) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } + + Scope(\_PR.CPU3) + { + Method(_CST,0) + { + // + // Return P0's _CST object. + // + Return(\_PR.CPU0._CST) + } + } +} // End of Definition Block diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl new file mode 100644 index 0000000000..1c894c2613 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl @@ -0,0 +1,172 @@ +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: APIST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + + +DefinitionBlock ( + "APIST.aml", + "SSDT", + 1, + "PmRef", + "ApIst", + 0x3000 + ) +{ + External(\_PR.CPU0._PSS, MethodObj) + External(\_PR.CPU0._PCT, MethodObj) + External(\_PR.CPU0._PPC, IntObj) + External(\_PR.CPU0._PSD, MethodObj) + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External (CFGD) + External (PDC0) + + Scope(\_PR.CPU1) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return P0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return P0 _PCT. + } + + Method(_PSS,0) + { + //Return the same table as CPU0 for CMP cases. + Return(\_PR.CPU0._PSS) + } + + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + Return(\_PR.CPU0._PSD) // Return P0 _PSD. + } + } + + Scope(\_PR.CPU2) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return P0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return P0 _PCT. + } + + Method(_PSS,0) + { + //Return the same table as CPU0 for CMP cases. + Return(\_PR.CPU0._PSS) + } + + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + Return(\_PR.CPU0._PSD) // Return P0 _PSD. + } + } + + Scope(\_PR.CPU3) + { + Method(_PPC,0) + { + Return(\_PR.CPU0._PPC) // Return P0 _PPC value. + } + + Method(_PCT,0) + { + Return(\_PR.CPU0._PCT) // Return P0 _PCT. + } + + Method(_PSS,0) + { + //Return the same table as CPU0 for CMP cases. + Return(\_PR.CPU0._PSS) + } + + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + Return(\_PR.CPU0._PSD) // Return P0 _PSD. + } + } +} // End of Definition Block diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl new file mode 100644 index 0000000000..266f8465fe --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl @@ -0,0 +1,268 @@ +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Platform Processor Power Management BIOS Reference Code + + Copyright (c) 2007 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: APTST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + + +DefinitionBlock( + "APTST.aml", + "SSDT", + 0x01, + "PmRef", + "ApTst", + 0x3000 + ) +{ + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External(\_PR.CPU0._PTC) + External(\_PR.CPU0._TSS) + External(PDC0) + External(CFGD) + External(MPEN) + + Scope(\_PR.CPU1) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 1) + // + // CFGD[23] = Four cores enabled + // CFGD[24] = Two or more cores enabled + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + MPEN // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 1, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU1 + + Scope(\_PR.CPU2) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 1) + // + // CFGD[23] = Four cores enabled + // CFGD[24] = Two or more cores enabled + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + MPEN // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 1, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU2 + + Scope(\_PR.CPU3) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + Return(\_PR.CPU0._PTC) + } + + Method(_TSS, 0) + { + Return(\_PR.CPU0._TSS) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination + // IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type (domain 1) + // + // CFGD[23] = Four cores enabled + // CFGD[24] = Two or more cores enabled + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + + If(LNot(And(PDC0,4))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + MPEN // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 1, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } // End of CPU3 +} // End of Definition Block + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl new file mode 100644 index 0000000000..1267d98ec3 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl @@ -0,0 +1,280 @@ + +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: CPU0CST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + + +DefinitionBlock ( + "CPU0CST.aml", + "SSDT", + 1, + "PmRef", + "Cpu0Cst", + 0x3001 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(PWRS) + External(CFGD) + External(PDC0) + + Scope(\_PR.CPU0) + { + OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG + Field (DEB0, ByteAcc,NoLock,Preserve) //DBG + { DBG8, 8,} //DBG + + Method (_CST, 0) + { + Store(0x60,DBG8) //DBG + + // IF CMP is supported, but independent C-States beyond C1 are + // not supported; return C1 Halt and rely on BIOS based software + // coordination + // + // CFGD[24] = CMP support + // PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems + // + // Note: SMI will be generated when both processor enter the + // Halt state. + // + If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10)))) + { + Store(0x61,DBG8) //DBG + Return(Package() { + 1, + Package() + { // C1 halt, but with BIOS coordination + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + 1, + 157, + 1000 + } + }) + } + + // IF MWAIT extensions are supported, use them. + // + // IF C6 capable/enabled AND Battery + // Report MWAIT C1, C2, C6 w/ BM_STS avoidance + // ELSE IF C4 capable/enabled AND Battery + // Report MWAIT C1, C2, C4 w/ BM_STS avoidance + // ELSE IF C3 capable/enabled + // Report MWAIT C1, C2, C3 w/ BM_STS avoidance + // ELSE IF C2 capable/enabled + // Report MWAIT C1, C2 + // ELSE + // Report MWAIT C1 + // + // CFGD[21] = 1 - MWAIT extensions supported + // CFGD[13] = 1 - C7 Capable/Enabled + // CFGD[12] = 1 - C6S Capable/Enabled + // CFGD[11] = 1 - C6 Capable/Enabled + // CFGD[7] = 1 - C4 Capable/Enabled + // CFGD[5] = 1 - C3 Capable/Enabled + // PDCx[9] = 1 - OS supports MWAIT extensions + // PDCx[8] = 1 - OS supports MWAIT for C1 + // (Inferred from PDCx[9] = 1.) + // PDCx[4] = 1 - OS supports independent C2/C3 in MP systems + // or + // NOT CMP (Inferred from previous check.) + // + If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200))) + { + // + // The implementor may wish to only report C1-C2 + // when on AC power. In this case, the IF clause below can + // be modified to something like: + // + // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))" + // + // Which uses the power state of the system (PWRS) to + // determine whether to allow deepers states. + // + // IF C7 supported AND on battery + // report MWAIT C1, C6, C7 + // + // CFGD[13] = C7 Capable/Enabled + // CFGD[11] = C6 Capable/Enabled + // + If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000))) + { + Store(0x77,DBG8) //DBG + Return( Package() + { + 3, + Package() + { // C1, MWAIT + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { + // C6, MWAIT Extension with Incremental L2 Shrink + // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, + // C6, MWAIT Extension with No L2 Shrink + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, + 2, + 500, + 10 + }, + Package() + { + // C7, MWAIT Extension with Full L2 Shrink + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)}, + 3, + 1500, //PnP setting, 1.5 ms for worst-case exit latency + 10 + } + }) + } + + + If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000)))) + { + Store(0x67,DBG8) //DBG + Return( Package() + { + 3, + Package() + { // C1, MWAIT + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { + // C6, MWAIT Extension with Incremental L2 Shrink + // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, + // C6 = C6NS, MWAIT Extension with No L2 Shrink + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, + 2, + 500, + 10 + }, + Package() + { + + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)}, + 3, + 1500, //PnP setting, 1.5 ms for worst-case exit latency + 10 + } + }) + } + + If(And(CFGD,0x800)) // Setup Max C-State = C6 + { + Store(0x76,DBG8) //DBG + Return( Package() + { + 2, + Package() + { // C1, MWAIT + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + }, + Package() + { + // C6, MWAIT Extension with Incremental L2 Shrink + // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)}, + // C6, MWAIT Extension with No L2 Shrink + ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)}, + 2, + 500, + 10 + } + }) + } + // + // IF no deeper C-States are supported; report MWAIT C1. + // + Store(0x71,DBG8) //DBG + Return(Package() + { + 1, + Package() + { // C1, MWAIT + ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)}, + 1, + 1, + 1000 + } + }) + } + + + } + } +} + + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl new file mode 100644 index 0000000000..8bb45124d5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl @@ -0,0 +1,266 @@ +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: CPU0IST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + + +DefinitionBlock ( + "CPU0IST.aml", + "SSDT", + 0x01, + "PmRef", + "Cpu0Ist", + 0x3000 + ) +{ + External (\_PR.CPU0, DeviceObj) + External (PDC0) + External (CFGD) + + Scope(\_PR.CPU0) + { + //OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG + //Field (DEB0, ByteAcc,NoLock,Preserve) //DBG + //{ DBG8, 8,} //DBG + + Name(_PPC, 0) // Initialize as All States Available. + + // NOTE: For CMP systems; this table is not loaded unless + // the required driver support is present. + // So, we do not check for those cases here. + // + // CFGD[0] = GV3 Capable/Enabled + // PDCx[0] = OS Capable of Hardware P-State control + // + Method(_PCT,0) + { + If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001))) + { + //Store(0xA0,DBG8) //DBG + Return(Package() // Native Mode + { + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)} + }) + } + // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT + // For all other cases, report control through the + // SMI interface. (The port used for SMM control is fixed up + // by the initialization code.) + // + Return(Package() // SMM Mode + { + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FfixedHW, 0, 0, 0)} + }) + } + + + // NOTE: For CMP systems; this table is not loaded if MP + // driver support is not present or P-State are disabled. + // + Method(_PSS,0) + { + // + // Report NSPP if: + // (1) GV3 capable (Not checked, see above.) + // (2) Driver support direct hardware control + // (3) MP driver support present (Not checked, see above.) + // else; + // Report SPSS + // + // PDCx[0] = OS Capable of Hardware P-State control + // + If(And(PDC0,0x0001)){ + //Store(0xB0,DBG8) //DBG + Return(NPSS) + } + //Store(0xBF,DBG8) //DBG + // Otherwise, report SMM mode + // + Return(SPSS) + + } + + Name(SPSS,Package() + { + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000} + }) + + Name(NPSS,Package() + { + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, + Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000} + }) + + // The _PSD object provides information to the OSPM related + // to P-State coordination between processors in a multi-processor + // configurations. + // + Method(_PSD,0) + { + // + // IF CMP is supported/enabled + // IF quad core processor + // IF PDC[11] + // Report 4 processors and HW_ALL as the coordination type + // ELSE + // Report 4 processors and SW_ALL as the coordination type + // ELSE + // IF PDC[11] + // Report 2 processors and HW_ALL as the coordination type + // ELSE + // Report 2 processors and SW_ALL as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type + // (Domain 0) + // + // CFGD[24] = Two or more cores enabled + // CFGD[23] = Four cores enabled + // PDCx[11] = Hardware coordination with hardware feedback + // + + If(And(CFGD,0x1000000)) // CMP Enabled. + { + If(And(CFGD,0x800000)) // 2 or 4 process. + { + If(And(PDC0,0x0800)) + { + Return(Package(){ // HW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFE, // Coord Type- HW_ALL. + 4 // # processors. + } + }) + } // If(And(PDC0,0x0800)) + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL. + 4 // # processors. + } + }) + } else { + Return(Package(){ // HW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFE, // Coord Type- HW_ALL. + 2 // # processors. + } + }) + } + } // If(And(CFGD,0x1000000)) // CMP Enabled. + + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL. + 1 // # processors. + } + }) + } // Method(_PSD,0) + } // Scope(\_PR.CPU0) +} // End of Definition Block + + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl new file mode 100644 index 0000000000..e535c93c3a --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl @@ -0,0 +1,241 @@ +/*----------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: CPU0TST.ASL + + Revision: Refer to Readme + + Date: Refer to Readme + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, end user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- + +NOTES: + (1) - IF the trap range and port definitions do not match those + specified by this reference code, this file must be modified IAW the + individual implmentation. + +-------------------------------------------------------------------------------- +------------------------------------------------------------------------------*/ + +DefinitionBlock( + "CPU0TST.aml", + "SSDT", + 0x01, + "PmRef", + "Cpu0Tst", + 0x3000 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(PDC0) + External(CFGD) + External(_PSS) + + Scope(\_PR.CPU0) + { + Name(_TPC, 0) // All T-States are available + + // + // T-State Control/Status interface + // + Method(_PTC, 0) + { + // + // IF OSPM is capable of direct access to MSR + // Report MSR interface + // ELSE + // Report I/O interface + // + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + If(And(PDC0, 0x0004)) { + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + } + + } + + // _TSS package for I/O port based T-State control + // "Power" fields are replaced with real values by the first + // call of _TSS method. + // + Name(TSSI, Package() { + Package(){100, 1000, 0, 0x00, 0}, + Package(){ 88, 875, 0, 0x0F, 0}, + Package(){ 75, 750, 0, 0x0E, 0}, + Package(){ 63, 625, 0, 0x0D, 0}, + Package(){ 50, 500, 0, 0x0C, 0}, + Package(){ 38, 375, 0, 0x0B, 0}, + Package(){ 25, 250, 0, 0x0A, 0}, + Package(){ 13, 125, 0, 0x09, 0} + }) + + // _TSS package for MSR based T-State control + // "Power" fields are replaced with real values by the first + // call of _TSS method. + // + Name(TSSM, Package() { + Package(){100, 1000, 0, 0x00, 0}, + Package(){ 88, 875, 0, 0x1E, 0}, + Package(){ 75, 750, 0, 0x1C, 0}, + Package(){ 63, 625, 0, 0x1A, 0}, + Package(){ 50, 500, 0, 0x18, 0}, + Package(){ 38, 375, 0, 0x16, 0}, + Package(){ 25, 250, 0, 0x14, 0}, + Package(){ 13, 125, 0, 0x12, 0} + }) + + Name(TSSF, 0) // Flag for TSSI/TSSM initialization + + Method(_TSS, 0) + { + // Update "Power" fields of TSSI/TSSM with the LFM + // power data IF _PSS is available + // + IF (LAnd(LNot(TSSF),CondRefOf(_PSS))) + { + Store(_PSS, Local0) + Store(SizeOf(Local0), Local1) // _PSS size + Decrement(Local1) // Index of LFM + Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2) // LFM Power + + Store(0, Local3) + While(LLess(Local3, SizeOf(TSSI))) + { + Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8), + Local4) // Power for this TSSI/TSSM entry + Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1)) + Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1)) + Increment(Local3) + } + Store(Ones, TSSF) // TSSI/TSSM are updated + } + // + // IF OSPM is capable of direct access to MSR + // Report TSSM + // ELSE + // Report TSSI + // + If(And(PDC0, 0x0004)) + { + Return(TSSM) + } + Return(TSSI) + } + + Method(_TDL, 0) + { + Store ("Cpu0: _TDL Called", Debug) + Name ( LFMI, 0) + Store (SizeOf(TSSM), LFMI) + Decrement(LFMI) // Index of LFM entry in TSSM + Return(LFMI) + } + + // + // T-State Dependency + // + Method(_TSD, 0) + { + // + // IF four cores are supported/enabled && !(direct access to MSR) + // Report 4 processors and SW_ANY as the coordination type + // ELSE IF two cores are supported/enabled && !(direct access to MSR) + // Report 2 processors and SW_ANY as the coordination type + // ELSE + // Report 1 processor and SW_ALL as the coordination type + // + // CFGD[23] = Four cores enabled + // CFGD[24] = Two or more cores enabled + // PDCx[2] = OSPM is capable of direct access to On + // Demand throttling MSR + // + If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4)))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + 4 // # processors. + } + }) + } + If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4)))) + { + Return(Package(){ // SW_ANY + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFD, // Coord Type- SW_ANY + 2 // # processors. + } + }) + } + Return(Package(){ // SW_ALL + Package(){ + 5, // # entries. + 0, // Revision. + 0, // Domain #. + 0xFC, // Coord Type- SW_ALL + 1 // # processors. + } + }) + } + } +} // End of Definition Block + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl new file mode 100644 index 0000000000..32cdcd354f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl @@ -0,0 +1,799 @@ +/*----------------------------------------------------------------------------- + + + Intel Silvermont Processor Power Management BIOS Reference Code + + Copyright (c) 2006 - 2014, Intel Corporation + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + Filename: CPUPM.ASL + + Revision: Refer to Readme + + Date: Refer to Readme +------------------------------------------------------------------------------- + + This Processor Power Management BIOS Source Code is furnished under license + and may only be used or copied in accordance with the terms of the license. + The information in this document is furnished for informational use only, is + subject to change without notice, and should not be construed as a commitment + by Intel Corporation. Intel Corporation assumes no responsibility or liability + for any errors or inaccuracies that may appear in this document or any + software that may be provided in association with this document. + + Except as permitted by such license, no part of this document may be + reproduced, stored in a retrieval system, or transmitted in any form or by + any means without the express written consent of Intel Corporation. + + WARNING: You are authorized and licensed to install and use this BIOS code + ONLY on an IST PC. This utility may damage any system that does not + meet these requirements. + + An IST PC is a computer which + (1) Is capable of seamlessly and automatically transitioning among + multiple performance states (potentially operating at different + efficiency ratings) based upon power source changes, END user + preference, processor performance demand, and thermal conditions; and + (2) Includes an Intel Pentium II processors, Intel Pentium III + processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4 + Processor-M, Intel Pentium M Processor, or any other future Intel + processors that incorporates the capability to transition between + different performance states by altering some, or any combination of, + the following processor attributes: core voltage, core frequency, bus + frequency, number of processor cores available, or any other attribute + that changes the efficiency (instructions/unit time-power) at which the + processor operates. +------------------------------------------------------------------------------- + +NOTES: + (1) - Except for the SSDT package, the objects in this ASL code + may be moved to the DSDT. It is kept separate in this reference package + for ease of distribution only. +------------------------------------------------------------------------------*/ + +DefinitionBlock ( + "CPUPM.aml", + "SSDT", + 0x01, + "PmRef", + "CpuPm", + 0x3000 + ) +{ + External(\_PR.CPU0, DeviceObj) + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + External(SMIF) + + Scope(\) + { + + // Package of pointers to SSDT's + // + // First column is SSDT name, used for debug only. + // (First column must be EXACTLY eight characters.) + // Second column is physical address. + // Third column is table length. + // + // IF modifying this file, see warnings listed in ppminit.asm. + // + Name(SSDT,Package() + { + "CPU0IST ", 0x80000000, 0x80000000, + "APIST ", 0x80000000, 0x80000000, + "CPU0CST ", 0x80000000, 0x80000000, + "APCST ", 0x80000000, 0x80000000 + }) + + // + // Note: See PpmBiosInit in PPMINIT.ASM for a definition of + // the PpmFlags mirrored in CFGD. + // + Name(CFGD, 0x80000000) + + Name(\PDC0,0x80000000) // CPU0 _PDC Flags. + Name(\PDC1,0x80000000) // CPU1 _PDC Flags. + Name(\PDC2,0x80000000) // CPU2 _PDC Flags. + Name(\PDC3,0x80000000) // CPU3 _PDC Flags. + Name(\SDTL,0x00) // Loaded SSDT Flags. + } + + Scope(\_PR.CPU0) + { + // + // Define handles for opregions (used by load.) + // + Name(HI0,0) // Handle to CPU0IST + Name(HC0,0) // Handle to CPU0CST + + Method(_PDC,1) + { + // + // Check and extract the _PDC information. + // + Store(CPDC(Arg0), Local0) + // + // Save the capability information and load tables as needed. + // + GCAP(Local0) + // + // Return status. + // + //Return (Local0) + } + + Method(_OSC, 4) + { + // + // Check and extract the _OSC information. + // + Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0) + // + // Save the capability information and load tables as needed. + // + GCAP(Local0) + // + // Return status. + // + Return (Local0) + } + + // + // Implement a generic Method to check _PDC information which may be called + // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3. + // in favor of _OSC. However, for backwards compatibility, _PDC may be + // implemented using _OSC as follows:) + // + Method(CPDC,1) + { + CreateDwordField (Arg0, 0, REVS) + CreateDwordField (Arg0, 4, SIZE) + + // + // Local0 = Number of bytes for Arg0 + // + Store (SizeOf (Arg0), Local0) + + // + // Local1 = Number of Capabilities bytes in Arg0 + // + Store (Subtract (Local0, 8), Local1) + + // + // TEMP = Temporary field holding Capability DWORDs + // + CreateField (Arg0, 64, Multiply (Local1, 8), TEMP) + + // + // Create the Status (STAT) buffer with the first DWORD = 0 + // This is required as per ACPI 3.0 Spec which says the + // first DWORD is used to return errors defined by _OSC. + // + Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00}) + + // + // Concatenate the _PDC capabilities bytes to the STS0 Buffer + // and store them in a local variable for calling OSC + // + Concatenate (STS0, TEMP, Local2) + + Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2)) + } + + // + // Implement a generic Method to check _OSC information which may be called + // by any of the processor scopes. + // + Method(COSC, 4) + { + // + // Point to Status DWORD in the Arg3 buffer (STATUS) + // + CreateDWordField(Arg3, 0, STS0) + // + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + // + CreateDwordField(Arg3, 4, CAP0) + + // + // _OSC needs to validate the UUID and Revision. + // + // IF Unrecognized UUID + // Return Unrecognized UUID _OSC Failure + // IF Unsupported Revision + // Return Unsupported Revision _OSC Failure + // + // STS0[0] = Reserved + // STS0[1] = _OSC Failure + // STS0[2] = Unrecognized UUID + // STS0[3] = Unsupported Revision + // STS0[4] = Capabilities masked + // + // Note: The comparison method used is necessary due to + // limitations of certain OSes which cannot perform direct + // buffer comparisons. + // + // Create a set of "Input" UUID fields. + // + CreateDwordField(Arg0, 0x0, IID0) + CreateDwordField(Arg0, 0x4, IID1) + CreateDwordField(Arg0, 0x8, IID2) + CreateDwordField(Arg0, 0xC, IID3) + // + // Create a set of "Expected" UUID fields. + // + Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953")) + CreateDwordField(UID0, 0x0, EID0) + CreateDwordField(UID0, 0x4, EID1) + CreateDwordField(UID0, 0x8, EID2) + CreateDwordField(UID0, 0xC, EID3) + // + // Verify the input UUID matches the expected UUID. + // + If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3))))) + { + // + // Return Unrecognized UUID _OSC Failure + // + Store (0x6, STS0) + Return (Arg3) + } + + If(LNot(LEqual(Arg1,1))) + { + // + // Return Unsupported Revision _OSC Failure + // + Store (0xA, STS0) + Return (Arg3) + } + + Return (Arg3) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + + // Point to Status DWORD in the Arg0 buffer (STATUS) + CreateDWordField(Arg0, 0, STS0) + + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + CreateDwordField(Arg0, 4, CAP0) + + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS0, 1)) + { + And(CAP0, 0xBFF, CAP0) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0) + + // + // Check IF the IST SSDTs should be loaded. + // + // CFGD[0] = GV3 Capable/Enabled + // + If(And(CFGD,0x01)) + { + // + // Load the IST SSDTs if: + // (1) CMP capable and enabled. + // (2) Driver supports P-States in MP configurations + // (3) Driver supports direct HW P-State control + // (4) SSDT is not already loaded + // + // CFGD[24] = Two or more cores enabled + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // SDTL[0] = CPU0 IST SSDT Loaded + // + If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01)))) + { + // + // Flag the IST SSDT as loaded for CPU0 + // + Or(SDTL, 0x01, SDTL) + + OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2))) + Load(IST0, HI0) // Dynamically load the CPU0IST SSDT + } + } + + // + // Check IF the CST SSDTs should be loaded. + // + // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled + // + If(And(CFGD,0x82)) + { + // + // Load the CST SSDTs if: + // (1) CMP capable/enabled + // (2) Driver supports multi-processor configurations + // (3) CPU0 CST ISDT is not already loaded + // + // CFGD[24] = Two or more cores enabled + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // SDTL[1] = CPU0 CST SSDT Loaded + // + If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02)))) + { + // + // Flag the CST SSDT as loaded for CPU0 + // + Or(SDTL, 0x02, SDTL) + + OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8))) + Load(CST0, HC0) // Dynamically load the CPU0CST SSDT + } + } + + Return () + } + } + + + Scope(\_PR.CPU1) + { + // + // Define handles for opregions (used by load.) + // + Name(HI1,0) // Handle to APIST + Name(HC1,0) // Handle to APCST + + Method(_PDC,1) + { + // + // Refer to \_PR.CPU0._PDC for description. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + //Return (Local0) + } + + Method(_OSC, 4) + { + // + // Refer to \_PR.CPU0._OSC for description. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + // + // Point to Status DWORD in the Arg0 buffer (STATUS) + // + CreateDWordField(Arg0, 0, STS1) + // + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + // + CreateDwordField(Arg0, 4, CAP1) + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS1, 1)) + { + And(CAP1, 0xBFF, CAP1) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1) + + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC0, 0x0009), 0x0009)) + { + APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC0,0x0018)) + { + APCT() + } + + Return() + } + + // + // Dynamically load the CST SSDTs if: + // (1) C-States are enabled + // (2) SSDT is not already loaded + // + // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled + // SDTL[5] = AP CST SSDT Loaded + // + Method(APCT,0) + { + If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20)))) + { + // + // Flag the CST SSDT as loaded for the AP's + // + Or(SDTL, 0x20, SDTL) + // + // Dynamically load the APCST SSDT + // + OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11))) + Load(CST1, HC1) + } + } + + // + // Dynamically load the IST SSDTs if: + // (1) If GV3 capable and enabled + // (2) SSDT is not already loaded + // + // CFGD[0] = GV3 Capable/Enabled + // SDTL[4] = AP IST SSDT Loaded + // + Method(APPT,0) + { + If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10)))) + { + // + // Flag the IST SSDT as loaded for CPU0 + // + Or(SDTL, 0x10, SDTL) + + OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5))) + Load(IST1, HI1) // Dynamically load the CPU1IST SSDT + } + } + } // End CPU1 + + Scope(\_PR.CPU2) + { + // + // Define handles for opregions (used by load.) + // + Name(HI1,0) // Handle to APIST + Name(HC1,0) // Handle to APCST + + Method(_PDC,1) + { + // + // Refer to \_PR.CPU0._PDC for description. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + //Return (Local0) + } + + Method(_OSC, 4) + { + // + // Refer to \_PR.CPU0._OSC for description. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + // + // Point to Status DWORD in the Arg0 buffer (STATUS) + // + CreateDWordField(Arg0, 0, STS1) + // + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + // + CreateDwordField(Arg0, 4, CAP1) + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS1, 1)) + { + And(CAP1, 0xBFF, CAP1) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1) + + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC0, 0x0009), 0x0009)) + { + APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC0,0x0018)) + { + APCT() + } + + Return() + } + + // + // Dynamically load the CST SSDTs if: + // (1) C-States are enabled + // (2) SSDT is not already loaded + // + // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled + // SDTL[5] = AP CST SSDT Loaded + // + Method(APCT,0) + { + If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20)))) + { + // + // Flag the CST SSDT as loaded for the AP's + // + Or(SDTL, 0x20, SDTL) + // + // Dynamically load the APCST SSDT + // + OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11))) + Load(CST1, HC1) + } + } + + // + // Dynamically load the IST SSDTs if: + // (1) If GV3 capable and enabled + // (2) SSDT is not already loaded + // + // CFGD[0] = GV3 Capable/Enabled + // SDTL[4] = AP IST SSDT Loaded + // + Method(APPT,0) + { + If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10)))) + { + // + // Flag the IST SSDT as loaded for CPU0 + // + Or(SDTL, 0x10, SDTL) + + OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5))) + Load(IST1, HI1) // Dynamically load the CPU1IST SSDT + } + } + } // End CPU1 + + Scope(\_PR.CPU3) + { + // + // Define handles for opregions (used by load.) + // + Name(HI1,0) // Handle to APIST + Name(HC1,0) // Handle to APCST + + Method(_PDC,1) + { + // + // Refer to \_PR.CPU0._PDC for description. + // + Store(\_PR.CPU0.CPDC(Arg0), Local0) + GCAP(Local0) + //Return (Local0) + } + + Method(_OSC, 4) + { + // + // Refer to \_PR.CPU0._OSC for description. + // + Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0) + GCAP(Local0) + Return (Local0) + } + + // + // Get the capability information and load appropriate tables as needed. + // + Method(GCAP, 1) + { + // + // Point to Status DWORD in the Arg0 buffer (STATUS) + // + CreateDWordField(Arg0, 0, STS1) + // + // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES) + // + CreateDwordField(Arg0, 4, CAP1) + // + // If the UUID was unrecognized or the _OSC revision was unsupported, + // return without updating capabilities. + // + If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA))) + { + Return() + } + + // + // Check if this is a query (BIT0 of Status = 1). + // If so, mask off the bits we support and return. + // + if (And(STS1, 1)) + { + And(CAP1, 0xBFF, CAP1) + Return() + } + + // + // Store result of PDC. (We clear out the MSB, which was just + // used as a placeholder for the compiler; and then "OR" the + // value in case we get multiple calls, each of which only + // reports partial support.) + // + Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1) + + // + // Attempt to dynamically load the IST SSDTs if: + // (1) Driver supports P-States in MP configurations + // (2) Driver supports direct HW P-State control + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[0] = OS supports direct access of the perf MSR + // + If(LEqual(And(PDC0, 0x0009), 0x0009)) + { + APPT() + } + + // + // Load the CST SSDTs if: + // (1) Driver supports multi-processor configurations + // + // PDCx[3] = OS supports C1 and P-states in MP systems + // PDCx[4] = OS supports ind. C2/C3 in MP systems + // + If(And(PDC0,0x0018)) + { + APCT() + } + + Return() + } + + // + // Dynamically load the CST SSDTs if: + // (1) C-States are enabled + // (2) SSDT is not already loaded + // + // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled + // SDTL[5] = AP CST SSDT Loaded + // + Method(APCT,0) + { + If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20)))) + { + // + // Flag the CST SSDT as loaded for the AP's + // + Or(SDTL, 0x20, SDTL) + // + // Dynamically load the APCST SSDT + // + OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11))) + Load(CST1, HC1) + } + } + + // + // Dynamically load the IST SSDTs if: + // (1) If GV3 capable and enabled + // (2) SSDT is not already loaded + // + // CFGD[0] = GV3 Capable/Enabled + // SDTL[4] = AP IST SSDT Loaded + // + Method(APPT,0) + { + If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10)))) + { + // + // Flag the IST SSDT as loaded for CPU0 + // + Or(SDTL, 0x10, SDTL) + + OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5))) + Load(IST1, HI1) // Dynamically load the CPU1IST SSDT + } + } + } // End CPU3 +} // End of Definition Block + + + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h new file mode 100644 index 0000000000..43119b868a --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h @@ -0,0 +1,98 @@ +/*++ + + Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + + +Module Name: + + PlatformBaseAddresses.h + +Abstract: + + + +Revision History + +++*/ + + +#ifndef _PLATFORM_BASE_ADDRESSES_H +#define _PLATFORM_BASE_ADDRESSES_H + +// +// Define some fixed platform device location information +// + +// +// Define platform base +// + +// +// SIO +// +#define SIO_BASE_ADDRESS 0x0680 +#define SIO_MONITORING_BASE_ADDRESS 0x0290 +#define SIO_BASE_MASK 0xFFF0 +#define WINDBOND_ECIR_BASE_ADDRESS 0x0810 +#define SIO_MAILBOX_BASE_ADDRESS 0x0360 // Used by EC controller +#define SIO_EC_CHANNEL2 0x62 // Used by EC controller for offset 0x62 and 0x66 + + +// +// South Cluster +// +#define ACPI_BASE_ADDRESS 0x0400 +#define GPIO_BASE_ADDRESS 0x0500 +#define SMBUS_BUS_DEV_FUNC 0x1F0300 +#define SMBUS_BASE_ADDRESS 0xEFA0 // SMBus IO Base Address +#define SPI_BASE_ADDRESS 0xFED01000 // SPI Memory Base Address +#define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address +#define SMBM_BASE_ADDRESS 0xFED04000 // SMBus Memory Base Address +#define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address +#define ILB_BASE_ADDRESS 0xFED08000 // ILB Memory Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base Address +#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address +#define MPHY_BASE_ADDRESS 0xFEF00000 // MPHY Memory Base Address +#define PUNIT_BASE_ADDRESS 0xFED05000 // PUnit Memory Base Address + +// +// GPIO GROUP OFFSET +// +#define GPIO_SCORE_OFFSET 0x0000 +#define GPIO_NCORE_OFFSET 0x1000 +#define GPIO_SSUS_OFFSET 0x2000 + +// +// MCH/CPU +// +#define DMI_BASE_ADDRESS 0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10 +#define EP_BASE_ADDRESS 0xFED19000 +#define MC_MMIO_BASE 0xFED14000 // Base Address for MMIO registers + +// +// TPM +// +#define TPM_BASE_ADDRESS 0xFED40000 // Base address for TPM + +// +// Local and I/O APIC addresses. +// +#define IO_APIC_ADDRESS 0xFEC00000 +#define IIO_IOAPIC_ADDRESS 0xFEC90000 +#define LOCAL_APIC_ADDRESS 0xFEE00000 + + +#endif + + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h new file mode 100644 index 0000000000..618e3d35b1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h @@ -0,0 +1,66 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Capsule.h + +Abstract: + + Capsule PPI definitions. + +--*/ +// +// +#ifndef _PEI_CAPSULE_PPI_H_ +#define _PEI_CAPSULE_PPI_H_ + +#define PEI_CAPSULE_PPI_GUID \ + { \ + 0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \ + } + +EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_COALESCE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID **MemoryBase, + IN OUT UINTN *MemSize + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_CREATE_STATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN VOID *CapsuleBase, // returned from coalesce + IN UINTN CapsuleSize // returned from coalesce + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) ( + IN EFI_PEI_SERVICES **PeiServices + ); + +typedef struct _PEI_CAPSULE_PPI { + PEI_CAPSULE_COALESCE Coalesce; + PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate; + PEI_CAPSULE_CREATE_STATE CreateState; +} PEI_CAPSULE_PPI; + +extern EFI_GUID gPeiCapsulePpiGuid; + +#endif // #ifndef _PEI_CAPSULE_PPI_H_ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h new file mode 100644 index 0000000000..b2faf4c7f6 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h @@ -0,0 +1,150 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PlatformMemoryRange.h + +Abstract: + + Platform Memory Range PPI as defined in EFI 2.0 + + PPI for reserving special purpose memory ranges. + +--*/ +// +// +#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_ +#define _PEI_PLATFORM_MEMORY_RANGE_H_ + +#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \ + { \ + 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \ + } + +typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI PEI_PLATFORM_MEMORY_RANGE_PPI ; + +#define PEI_MEMORY_RANGE_OPTION_ROM UINT32 + +#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF +#define PEI_MR_OPTION_ROM_NONE 0x00000000 +#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001 +#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002 +#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004 +#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008 +#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010 +#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020 +#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040 +#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080 +#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100 +#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200 +#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400 +#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800 +#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000 +#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000 +#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000 +#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000 + +// +// SMRAM Memory Range +// +#define PEI_MEMORY_RANGE_SMRAM UINT32 +#define PEI_MR_SMRAM_ALL 0xFFFFFFFF +#define PEI_MR_SMRAM_NONE 0x00000000 +#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000 +#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000 +#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000 +#define PEI_MR_SMRAM_HSEG_MASK 0x00020000 +#define PEI_MR_SMRAM_TSEG_MASK 0x00040000 +// +// If adding additional entries, SMRAM Size +// is a multiple of 128KB. +// +#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF +#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001 +#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002 +#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004 +#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008 +#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010 +#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020 +#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040 + +#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001 +#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001 +#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001 +#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001 +#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001 +#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002 +#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002 +#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004 +#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004 +#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008 +#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008 + +// +// Graphics Memory Range +// +#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32 +#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF +#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000 +#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000 +// +// If adding additional entries, Graphics Memory Size +// is a multiple of 512KB. +// +#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF +#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001 +#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001 +#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002 +#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002 +#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008 +#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008 +#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010 +#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010 +#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020 +#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020 +#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040 +#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040 +#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060 +#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060 +#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080 +#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080 +#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100 +#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100 +#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200 +#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200 +// +// Pci Memory Hole +// +#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32 +#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001 + +typedef +EFI_STATUS +(EFIAPI *PEI_CHOOSE_RANGES) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI * This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask + ); + +struct _PEI_PLATFORM_MEMORY_RANGE_PPI { + PEI_CHOOSE_RANGES ChooseRanges; +}; + +extern EFI_GUID gPeiPlatformMemoryRangePpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h new file mode 100644 index 0000000000..6aa66b51cd --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h @@ -0,0 +1,52 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + PlatformMemorySize.h + +Abstract: + + Platform Memory Size PPI as defined in Tiano + + PPI for describing the minimum platform memory size in order to successfully + pass control into DXE + +--*/ +// +// +#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_ +#define _PEI_PLATFORM_MEMORY_SIZE_H_ + +#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \ + { \ + 0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \ + } + +EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI * This, + IN OUT UINT64 *MemorySize + ); + +typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI { + PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize; +} PEI_PLATFORM_MEMORY_SIZE_PPI; + +extern EFI_GUID gPeiPlatformMemorySizePpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h new file mode 100644 index 0000000000..674d566200 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h @@ -0,0 +1,171 @@ +// +// +/*++ + +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmmAccess.h + +Abstract: + + SmmAccess PPI + + This code abstracts the PEI core to provide SmmAccess services. + +--*/ + +#ifndef _PEI_SMM_ACCESS_PPI_H_ +#define _PEI_SMM_ACCESS_PPI_H_ + +#ifdef ECP_FLAG +#include "Guid/SmramMemoryReserve/SmramMemoryReserve.h" +#else +#include "Guid/SmramMemoryReserve.h" +#endif + +#define PEI_SMM_ACCESS_PPI_GUID \ + { \ + 0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \ + } + +typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_OPEN) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +/*++ + + Routine Description: + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all PEIM + and SMM agents. + + Arguments: + PeiServices - General purpose services available to every PEIM. + This - Pointer to the SMM Access Interface. + DescriptorIndex - Region of SMRAM to Open. + + Returns: + EFI_SUCCESS - The region was successfully opened. + EFI_DEVICE_ERROR - The region could not be opened because locked by + chipset. + EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +--*/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CLOSE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +/*++ + + Routine Description: + This routine accepts a request to "close" a region of SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "close" means that the memory is only visible from SMM agents, + not from PEIM. + + Arguments: + PeiServices - General purpose services available to every PEIM. + This - Pointer to the SMM Access Interface. + DescriptorIndex - Region of SMRAM to Close. + + Returns: + EFI_SUCCESS - The region was successfully closed. + EFI_DEVICE_ERROR - The region could not be closed because locked by + chipset. + EFI_INVALID_PARAMETER - The descriptor index was out of bounds. + +--*/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_LOCK) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +/*++ + + Routine Description: + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to PEIM. + + Arguments: + PeiServices - General purpose services available to every PEIM. + This - Pointer to the SMM Access Interface. + DescriptorIndex - Region of SMRAM to Lock. + + Returns: + EFI_SUCCESS - The region was successfully locked. + EFI_DEVICE_ERROR - The region could not be locked because at least + one range is still open. + EFI_INVALID_PARAMETER - The descriptor index was out of bounds. + +--*/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CAPABILITIES) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ) +/*++ + + Routine Description: + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + Arguments: + PeiServices - General purpose services available to every PEIM. + This - Pointer to the SMRAM Access Interface. + SmramMapSize - Pointer to the variable containing size of the + buffer to contain the description information. + SmramMap - Buffer containing the data describing the Smram + region descriptors. + Returns: + EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer. + EFI_SUCCESS - The user provided a sufficiently-sized buffer. +--*/ +; + +struct _PEI_SMM_ACCESS_PPI { + PEI_SMM_OPEN Open; + PEI_SMM_CLOSE Close; + PEI_SMM_LOCK Lock; + PEI_SMM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gPeiSmmAccessPpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h new file mode 100644 index 0000000000..53a5c12341 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h @@ -0,0 +1,45 @@ + +/*++ + +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvMmioPolicy.h + +Abstract: + + Interface definition details between ValleyView platform drivers during PEI phase. + +--*/ + +#ifndef _VLV_MMIO_POLICY_PPI_H_ +#define _VLV_MMIO_POLICY_PPI_H_ + +#define VLV_MMIO_POLICY_PPI_GUID \ + { \ + 0xE767BF7F, 0x4DB6, 0x5B34, 0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2 \ + } + +extern EFI_GUID gVlvMmioPolicyPpiGuid; + + +// +// MRC Platform Policiy PPI +// +typedef struct _VLV_MMIO_POLICY_PPI { + UINT16 MmioSize; +} VLV_MMIO_POLICY_PPI; + +#pragma pack() + +#endif // _VLV_MMIO_POLICY_PPI_H_ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h new file mode 100644 index 0000000000..9ad30ccd73 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h @@ -0,0 +1,41 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvPeiInit.h + +Abstract: + + Interface definition between ValleyView MRC and VlvInitPeim driver.. + +--*/ + +#ifndef _VLV_PEI_INIT_H_ +#define _VLV_PEI_INIT_H_ + +// +// Define the VLV PEI Init PPI GUID +// +#define VLV_PEI_INIT_PPI_GUID \ + { \ + 0x9ea8911, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11 \ + } + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gVlvPeiInitPpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h new file mode 100644 index 0000000000..19061f7ad2 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h @@ -0,0 +1,112 @@ + +/*++ + +Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvPolicy.h + +Abstract: + + Interface definition details between ValleyView MRC and platform drivers during PEI phase. + +--*/ + +#ifndef _VLV_POLICY_PPI_H_ +#define _VLV_POLICY_PPI_H_ + +// +// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3} +// +#define VLV_POLICY_PPI_GUID \ + { \ + 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \ + } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gVlvPolicyPpiGuid; + +// +// PPI revision number +// Any backwards compatible changes to this PPI will result in an update in the revision number +// Major changes will require publication of a new PPI +// +#define MRC_PLATFORM_POLICY_PPI_REVISION 1 + +#ifndef MAX_SOCKETS +#define MAX_SOCKETS 4 +#endif + +#define S3_TIMING_DATA_LEN 9 +#define S3_READ_TRAINING_DATA_LEN 16 +#define S3_WRITE_TRAINING_DATA_LEN 12 + +#ifndef S3_RESTORE_DATA_LEN +#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN) +#endif // S3_RESTORE_DATA_LEN +#pragma pack(1) +// +// MRC Platform Data Structure +// +typedef struct { + UINT8 SpdAddressTable[MAX_SOCKETS]; + UINT8 TSonDimmSmbusAddress[MAX_SOCKETS]; + + UINT16 SmbusBar; + UINT32 IchRcba; + UINT32 WdbBaseAddress; // Write Data Buffer area (WC caching mode) + UINT32 WdbRegionSize; + UINT32 SmBusAddress; + UINT8 UserBd; + UINT8 PlatformType; + UINT8 FastBoot; + UINT8 DynSR; +} VLV_PLATFORM_DATA; + + +typedef struct { + UINT16 MmioSize; + UINT16 GttSize; + UINT8 IgdDvmt50PreAlloc; + UINT8 PrimaryDisplay; + UINT8 PAVPMode; + UINT8 ApertureSize; + UINT8 InternalGraphics; + UINT8 IgdTurboEn; +} GT_CONFIGURATION; + +typedef struct { + UINT8 EccSupport; + UINT16 DdrFreqLimit; + UINT8 MaxTolud; +} MEMORY_CONFIGURATION; + + +// +// MRC Platform Policiy PPI +// +typedef struct _VLV_POLICY_PPI { + UINT8 Revision; + VLV_PLATFORM_DATA PlatformData; + GT_CONFIGURATION GtConfig; + MEMORY_CONFIGURATION MemConfig; + VOID *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE + UINT8 ISPEn; //ISP (IUNIT) Device Enabled + UINT8 ISPPciDevConfig; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS +} VLV_POLICY_PPI; + +#pragma pack() + +#endif // _VLV_POLICY_PPI_H_ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..8aa7c7b54d --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,219 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + IgdOpRegion.h + +Abstract: + + This file is part of the IGD OpRegion Implementation. The IGD OpRegion is + an interface between system BIOS, ASL code, and Graphics drivers. + + Supporting Specifiction: IGD OpRegion/Software SCI SPEC + + Note: Data structures defined in this protocol are packed not naturally + aligned. + + GUID forms: + {CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3} + (0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3); + + Acronyms: + NVS: ACPI Non Volatile Storage + OpRegion: ACPI Operational Region + VBT: Video BIOS Table (OEM customizable data) + +--*/ + +#ifndef _IGD_OPREGION_PROTOCOL_H_ +#define _IGD_OPREGION_PROTOCOL_H_ + +// +// OpRegion / Software SCI protocol GUID +// +#define IGD_OPREGION_PROTOCOL_GUID \ + { \ + 0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \ + } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gIgdOpRegionProtocolGuid; + +// +// Forward reference for pure ANSI compatability +// +typedef struct _IGD_OPREGION_PROTOCOL IGD_OPREGION_PROTOCOL; + +// +// Protocol data definitions +// + +// +// OpRegion structures: +// Sub-structures define the different parts of the OpRegion followed by the +// main structure representing the entire OpRegion. +// +// Note: These structures are packed to 1 byte offsets because the exact +// data location is requred by the supporting design specification due to +// the fact that the data is used by ASL and Graphics driver code compiled +// separatly. +// + +// +// OpRegion header (mailbox 0) structure and #defines. +// +#pragma pack (1) +typedef struct { + CHAR8 SIGN[0x10]; // 0 OpRegion signature + UINT32 SIZE; // 0x10 OpRegion size + UINT32 OVER; // 0x14 OpRegion structure version + UINT8 SVER[0x20]; // 0x18 System BIOS build version + UINT8 VVER[0x10]; // 0x38 Video BIOS build version + UINT8 GVER[0x10]; // 0x48 Graphic driver build version + UINT32 MBOX; // 0x58 Mailboxes supported + UINT32 DMOD; // 0x5C Driver Model + UINT32 PCON; // 0x60 Platform Configuration Info + CHAR8 GOPV[0x20]; // 0X64 GOP build version + UINT8 RSV[0x7C]; // Reserved +} OPREGION_HEADER; +#pragma pack () + +// +// OpRegion mailbox 1 (public ACPI Methods). +// +#pragma pack (1) +typedef struct { + UINT32 DRDY; // 0 Driver readiness + UINT32 CSTS; // 4 Status + UINT32 CEVT; // 8 Current event + UINT8 RM11[0x14]; // 12 Reserved + UINT32 DIDL; // 32 Supported display devices list + UINT32 DDL2; // 8 Devices. + UINT32 DDL3; + UINT32 DDL4; + UINT32 DDL5; + UINT32 DDL6; + UINT32 DDL7; + UINT32 DDL8; + UINT32 CPDL; // 64 Currently present display devices list + UINT32 CPL2; // 8 Devices. + UINT32 CPL3; + UINT32 CPL4; + UINT32 CPL5; + UINT32 CPL6; + UINT32 CPL7; + UINT32 CPL8; + UINT32 CADL; // 96 Currently active display devices list + UINT32 CAL2; // 8 Devices. + UINT32 CAL3; + UINT32 CAL4; + UINT32 CAL5; + UINT32 CAL6; + UINT32 CAL7; + UINT32 CAL8; + UINT32 NADL; // 128 Next active device list + UINT32 NDL2; // 8 Devices. + UINT32 NDL3; + UINT32 NDL4; + UINT32 NDL5; + UINT32 NDL6; + UINT32 NDL7; + UINT32 NDL8; + UINT32 ASLP; // 160 ASL sleep timeout + UINT32 TIDX; // 164 Toggle table index + UINT32 CHPD; // 168 Current hot plug enable indicator + UINT32 CLID; // 172 Current lid state indicator + UINT32 CDCK; // 176 Current docking state indicator + UINT32 SXSW; // 180 Display Switch notification on Sx State resume + UINT32 EVTS; // 184 Events supported by ASL + UINT32 CNOT; // 188 Current OS Notification + UINT32 NRDY; // 192 Reasons for DRDY = 0 + UINT8 RM12[0x3C]; // 196 Reserved +} OPREGION_MBOX1; +#pragma pack () + +// +// OpRegion mailbox 2 (Software SCI Interface). +// +#pragma pack (1) +typedef struct { + UINT32 SCIC; // 0 Software SCI function number parameters + UINT32 PARM; // 4 Software SCI additional parameters + UINT32 DSLP; // 8 Driver sleep timeout + UINT8 RM21[0xF4]; // 12 Reserved +} OPREGION_MBOX2; +#pragma pack () + +// +// OpRegion mailbox 3 (Power Conservation). +// +#pragma pack (1) +typedef struct { + UINT32 ARDY; // 0 Driver readiness + UINT32 ASLC; // 4 ASLE interrupt command / status + UINT32 TCHE; // 8 Technology enabled indicator + UINT32 ALSI; // 12 Current ALS illuminance reading + UINT32 BCLP; // 16 Backlight britness to set + UINT32 PFIT; // 20 Panel fitting Current State or Request + UINT32 CBLV; // 24 Brightness Current State + UINT16 BCLM[0x14]; // 28 Backlight Brightness Level Duty Cycle Mapping Table + UINT32 CPFM; // 68 Panel Fitting Current Mode + UINT32 EPFM; // 72 Enabled Panel Fitting Mode + UINT8 PLUT[0x4A]; // 76 Panel Look Up Table + UINT32 PFMB; // 150 PWM Frequency and Minimum Brightness + UINT32 CCDV; // 154 Color Correction Default Values + UINT32 PCFT; // 158 Power Conservation Features + UINT8 RM31[0x5E]; // 162 Reserved +} OPREGION_MBOX3; +#pragma pack () + +// +// OpRegion mailbox 4 (VBT). +// +#pragma pack (1) +typedef struct { + UINT8 GVD1[0x1800]; // 6K Reserved +} OPREGION_VBT; +#pragma pack () + +#pragma pack (1) +typedef struct { + UINT8 EDIDOVRD[0x400]; // 6K Edid overriding data +} OPREGION_MBOX5; +#pragma pack () +// +// Entire OpRegion +// +#pragma pack (1) +typedef struct { + OPREGION_HEADER Header; // OpRegion header + OPREGION_MBOX1 MBox1; // Mailbox 1: Public ACPI Methods + OPREGION_MBOX2 MBox2; // Mailbox 2: Software SCI Inteface + OPREGION_MBOX3 MBox3; // Mailbox 3: Power Conservation + OPREGION_VBT VBT; // VBT: Video BIOS Table (OEM customizable data) + OPREGION_MBOX5 MBox5; +} IGD_OPREGION_STRUC; +#pragma pack () + +// +// Protocol data structure definition +// +struct _IGD_OPREGION_PROTOCOL { + IGD_OPREGION_STRUC *OpRegion; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h new file mode 100644 index 0000000000..74e31d48b1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h @@ -0,0 +1,89 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + MemInfo.h + +Abstract: + + This protocol provides the memory information data, such as + total physical memory size, memory frequency, memory size + of each dimm and rank. + + This protocol is EFI compatible. + +--*/ + +#ifndef _MEM_INFO_PROTOCOL_H_ +#define _MEM_INFO_PROTOCOL_H_ + +// +// Define the protocol GUID +// +#define MEM_INFO_PROTOCOL_GUID \ + { \ + 0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \ + } + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gMemInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL; + +// +// Protocol definitions +// + +#define CH_NUM 2 +#define DIMM_NUM 1 +#define RANK_NUM 2 + +#pragma pack(1) +typedef struct { + UINT32 memSize; + UINT8 ddrFreq; + UINT8 ddrType; + BOOLEAN EccSupport; + UINT16 dimmSize[CH_NUM * DIMM_NUM]; + UINT8 reserved; + UINT16 reserved2; +} MEMORY_INFO_DATA; +#pragma pack() + +/*++ +Data definition: + + memSize Total physical memory size + ddrFreq DDR Frequency + EccSupport ECC Support + dimmSize Dimm Size + DimmExist Dimm Present or not + RankInDimm No. of ranks in a dimm + +--*/ + +// +// Protocol definition +// +struct _MEM_INFO_PROTOCOL { + MEMORY_INFO_DATA MemInfoData; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h new file mode 100644 index 0000000000..7e948c70b1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h @@ -0,0 +1,73 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + +/** @file +**/ + +#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_ +#define _PLATFORM_GOP_POLICY_PROTOCOL_H_ + +#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \ + { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } + +#define EFI_BMP_IMAGE_GUID \ + { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } + +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01 +#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222 + +#pragma pack(1) + +typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +typedef enum { + Docked, + UnDocked, + DockStatusMax +} DOCK_STATUS; + +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS *CurrentLidStatus + ); + +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ); + +#pragma pack() + +typedef struct _PLATFORM_GOP_POLICY_PROTOCOL { + UINT32 Revision; + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; + GET_VBT_DATA GetVbtData; +} PLATFORM_GOP_POLICY_PROTOCOL; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPlatformGOPPolicyGuid; + +extern EFI_GUID gBmpImageGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h new file mode 100644 index 0000000000..de98c590f5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h @@ -0,0 +1,111 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + VlvPlatformPolicy.h + +Abstract: + + Interface definition details between MCH and platform drivers during DXE phase. + +--*/ + +#ifndef _VLV_PLATFORM_POLICY_H_ +#define _VLV_PLATFORM_POLICY_H_ + +// +// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-B6AD-B812F6881CD6} +// +#define DXE_VLV_PLATFORM_POLICY_GUID \ + {0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6} + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gDxeVlvPlatformPolicyGuid; + +// +// Protocol revision number +// Any backwards compatible changes to this protocol will result in an update in the revision number +// Major changes will require publication of a new protocol +// +#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0 + + +typedef struct { + UINT8 PFITStatus; + UINT8 IgdTheramlSupport; + UINT8 ALSEnabled; + UINT8 LidStatus; +} IGD_PANEL_FEATURES; + +typedef struct { + UINT8 Reserved00; + UINT8 Reserved01; + UINT16 Reserved02; + UINT16 Reserved03; + UINT16 Reserved04; + UINT16 Reserved05; + UINT16 Reserved06; + UINT16 Reserved07; + UINT16 Reserved08; + UINT16 Reserved09; + UINT16 Reserved0A; + UINT16 Reserved0B; + UINT16 Reserved0C; + UINT16 Reserved0D; + UINT8 Reserved0E; + UINT8 Reserved0F; + UINT32 Reserved10; + UINT32 Reserved11; + UINT32 Reserved12; + UINT32 Reserved13; + UINT32 Reserved14; + UINT8 Reserved15; + UINT8 Reserved16; +} DPTF_SETTINGS; + +// +// MCH DXE Platform Policiy ================================================== +// + +#define NO_AUDIO 0 +#define HD_AUDIO 1 +#define LPE_AUDIO 2 + +typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + IGD_PANEL_FEATURES IgdPanelFeatures; + DPTF_SETTINGS Reserved; + UINT8 GraphicReserve00; + UINT8 GraphicsPerfAnalyzers; + UINT8 PwmReserved00; + UINT8 PwmReserved01; + UINT8 PmSupport; + UINT8 GraphicReserve01; + UINT8 GfxPause; + UINT8 GraphicsFreqReq; + UINT8 GraphicReserve03; + UINT8 GraphicReserve02; + UINT8 GraphicReserve04; + UINT8 PavpMode; + UINT8 GraphicReserve05; + UINT8 UlClockGating; + UINT8 IdleReserve; + UINT8 AudioTypeSupport; + UINT8 GraphicReserve06; +} DXE_VLV_PLATFORM_POLICY_PROTOCOL; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h new file mode 100644 index 0000000000..ccb4eb3516 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h @@ -0,0 +1,61 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Valleyview.h + +Abstract: + + This header file provides common definitions just for Valleyview-SOC using to avoid including extra module's file. +--*/ + +#ifndef _MC_H_INCLUDED_ +#define _MC_H_INCLUDED_ +/* +< Extended Configuration Base Address.*/ +#define EC_BASE 0xE0000000 + +// +// DEVICE 0 (Memroy Controller Hub) +// +#define MC_BUS 0x00 +#define MC_DEV 0x00 +#define MC_DEV2 0x02 +#define MC_FUN 0x00 +// NC DEV 0 Vendor and Device IDs +#define MC_VID 0x8086 +#define MC_DID_OFFSET 0x2 //Device Identification +#define MC_GGC_OFFSET 0x50 //GMCH Graphics Control Register + +// +// Device 2 Register Equates +// +#define IGD_BUS 0x00 +#define IGD_DEV 0x02 +#define IGD_FUN_0 0x00 +#define IGD_FUN_1 0x01 +#define IGD_DEV_FUN (IGD_DEV << 3) +#define IGD_BUS_DEV_FUN (MC_BUS << 8) + IGD_DEV_FUN +#define IGD_VID 0x8086 +#define IGD_DID 0xA001 +#define IGD_MGGC_OFFSET 0x0050 //GMCH Graphics Control Register 0x50 +#define IGD_BSM_OFFSET 0x005C //Base of Stolen Memory +#define IGD_SWSCI_OFFSET 0x00E0 //Software SCI 0xE0 2 +#define IGD_ASLE_OFFSET 0x00E4 //System Display Event Register 0xE4 4 +#define IGD_ASLS_OFFSET 0x00FC // ASL Storage +#define IGD_DID_QS 0x0BE2 //RCOverride -a: Fix the DID error + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h new file mode 100644 index 0000000000..1a1326c976 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h @@ -0,0 +1,260 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + vlvAccess.h + +Abstract: + + Macros to simplify and abstract the interface to PCI configuration. + +--*/ + +#ifndef _VLVACCESS_H_INCLUDED_ +#define _VLVACCESS_H_INCLUDED_ + +#include "Valleyview.h" +#include "VlvCommonDefinitions.h" +#include + +// +// Memory Mapped IO access macros used by MSG BUS LIBRARY +// +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + + +// +// UINT32 +// + +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +#define Mmio32Or( BaseAddr, Register, OrData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + Mmio32( BaseAddr, Register ) | \ + (UINT32)(OrData) \ + ) + +#define Mmio32And( BaseAddr, Register, AndData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + Mmio32( BaseAddr, Register ) & \ + (UINT32)(AndData) \ + ) + +#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + ( Mmio32( BaseAddr, Register ) & \ + (UINT32)(AndData) \ + ) | \ + (UINT32)(OrData) \ + ) + +// +// UINT16 +// + +#define Mmio16Ptr( BaseAddr, Register ) \ + ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio16( BaseAddr, Register ) \ + *Mmio16Ptr( BaseAddr, Register ) + +#define Mmio16Or( BaseAddr, Register, OrData ) \ + Mmio16( BaseAddr, Register ) = \ + (UINT16) ( \ + Mmio16( BaseAddr, Register ) | \ + (UINT16)(OrData) \ + ) + +#define Mmio16And( BaseAddr, Register, AndData ) \ + Mmio16( BaseAddr, Register ) = \ + (UINT16) ( \ + Mmio16( BaseAddr, Register ) & \ + (UINT16)(AndData) \ + ) + +#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \ + Mmio16( BaseAddr, Register ) = \ + (UINT16) ( \ + ( Mmio16( BaseAddr, Register ) & \ + (UINT16)(AndData) \ + ) | \ + (UINT16)(OrData) \ + ) + +// +// UINT8 +// + +#define Mmio8Ptr( BaseAddr, Register ) \ + ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio8( BaseAddr, Register ) \ + *Mmio8Ptr( BaseAddr, Register ) + +#define Mmio8Or( BaseAddr, Register, OrData ) \ + Mmio8( BaseAddr, Register ) = \ + (UINT8) ( \ + Mmio8( BaseAddr, Register ) | \ + (UINT8)(OrData) \ + ) + +#define Mmio8And( BaseAddr, Register, AndData ) \ + Mmio8( BaseAddr, Register ) = \ + (UINT8) ( \ + Mmio8( BaseAddr, Register ) & \ + (UINT8)(AndData) \ + ) + +#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \ + Mmio8( BaseAddr, Register ) = \ + (UINT8) ( \ + ( Mmio8( BaseAddr, Register ) & \ + (UINT8)(AndData) \ + ) | \ + (UINT8)(OrData) \ + ) + +// +// MSG BUS API +// + +#define MSG_BUS_ENABLED 0x000000F0 +#define MSGBUS_MASKHI 0xFFFFFF00 +#define MSGBUS_MASKLO 0x000000FF + +#define MESSAGE_BYTE_EN BIT4 +#define MESSAGE_WORD_EN BIT4 | BIT5 +#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7 + +#define SIDEBAND_OPCODE 0x78 +#define MEMREAD_OPCODE 0x00000000 +#define MEMWRITE_OPCODE 0x01000000 + + + +/***************************/ +// +// Memory mapped PCI IO +// + +#define PciCfgPtr(Bus, Device, Function, Register )\ + (UINTN)(Bus << 20) + \ + (UINTN)(Device << 15) + \ + (UINTN)(Function << 12) + \ + (UINTN)(Register) + +#define PciCfg32Read_CF8CFC(B,D,F,R) \ + (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC)) + +#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \ + (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data)) + +#define PciCfg32Or_CF8CFC(B,D,F,R,O) \ + PciCfg32Write_CF8CFC(B,D,F,R, \ + (PciCfg32Read_CF8CFC(B,D,F,R) | (O))) + +#define PciCfg32And_CF8CFC(B,D,F,R,A) \ + PciCfg32Write_CF8CFC(B,D,F,R, \ + (PciCfg32Read_CF8CFC(B,D,F,R) & (A))) + +#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \ + PciCfg32Write_CF8CFC(B,D,F,R, \ + (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O)) + +// +// Device 0, Function 0 +// +#define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register) +#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData) +#define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData) +#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) + +#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register) +#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData) +#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData) +#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) + +#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register) +#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData) +#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData) +#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) + +#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register) +#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData) +#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData) +#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData) + + +// +// Device 2, Function 0 +// +#define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register) +#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData) +#define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData) +#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) + +#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register) +#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData) +#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData) +#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) + +#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register) +#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData) +#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData) +#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData) + +#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register) +#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData) +#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData) + +// +// IO +// + +#ifndef IoIn8 + +#define IoIn8(Port) \ + IoRead8(Port) + +#define IoIn16(Port) \ + IoRead16(Port) + +#define IoIn32(Port) \ + IoRead32(Port) + +#define IoOut8(Port, Data) \ + IoWrite8(Port, Data) + +#define IoOut16(Port, Data) \ + IoWrite16(Port, Data) + +#define IoOut32(Port, Data) \ + IoWrite32(Port, Data) + +#endif + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h new file mode 100644 index 0000000000..3203fc6ea0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h @@ -0,0 +1,258 @@ + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + VlvCommonDefinitions.h + +Abstract: + + Macros to simplify and abstract the interface to PCI configuration. + +--*/ + +/// +/// PCI CONFIGURATION MAP REGISTER OFFSETS +/// +#ifndef PCI_VID +#define PCI_VID 0x0000 ///< Vendor ID Register +#define PCI_DID 0x0002 ///< Device ID Register +#define PCI_CMD 0x0004 ///< PCI Command Register +#define PCI_STS 0x0006 ///< PCI Status Register +#define PCI_RID 0x0008 ///< Revision ID Register +#define PCI_IFT 0x0009 ///< Interface Type +#define PCI_SCC 0x000A ///< Sub Class Code Register +#define PCI_BCC 0x000B ///< Base Class Code Register +#define PCI_CLS 0x000C ///< Cache Line Size +#define PCI_PMLT 0x000D ///< Primary Master Latency Timer +#define PCI_HDR 0x000E ///< Header Type Register +#define PCI_BIST 0x000F ///< Built in Self Test Register +#define PCI_BAR0 0x0010 ///< Base Address Register 0 +#define PCI_BAR1 0x0014 ///< Base Address Register 1 +#define PCI_BAR2 0x0018 ///< Base Address Register 2 +#define PCI_PBUS 0x0018 ///< Primary Bus Number Register +#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register +#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register +#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer +#define PCI_BAR3 0x001C ///< Base Address Register 3 +#define PCI_IOBASE 0x001C ///< I/O base Register +#define PCI_IOLIMIT 0x001D ///< I/O Limit Register +#define PCI_SECSTATUS 0x001E ///< Secondary Status Register +#define PCI_BAR4 0x0020 ///< Base Address Register 4 +#define PCI_MEMBASE 0x0020 ///< Memory Base Register +#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register +#define PCI_BAR5 0x0024 ///< Base Address Register 5 +#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register +#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register +#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits +#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits +#define PCI_SVID 0x002C ///< Subsystem Vendor ID +#define PCI_SID 0x002E ///< Subsystem ID +#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register +#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register +#define PCI_CAPP 0x0034 ///< Capabilities Pointer +#define PCI_EROM 0x0038 ///< Expansion ROM Base Address +#define PCI_INTLINE 0x003C ///< Interrupt Line Register +#define PCI_INTPIN 0x003D ///< Interrupt Pin Register +#define PCI_MAXGNT 0x003E ///< Max Grant Register +#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register +#define PCI_MAXLAT 0x003F ///< Max Latency Register +#endif +// +// Bit Difinitions +// +#ifndef BIT0 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#endif + +#ifndef _PCIACCESS_H_INCLUDED_ +#define _PCIACCESS_H_INCLUDED_ +#ifndef PCI_EXPRESS_BASE_ADDRESS + #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000 +#endif + +#ifndef MmPciAddress +#define MmPciAddress( Segment, Bus, Device, Function, Register ) \ + ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \ + (UINTN)(Bus << 20) + \ + (UINTN)(Device << 15) + \ + (UINTN)(Function << 12) + \ + (UINTN)(Register) \ + ) +#endif + +// +// UINT64 +// +#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \ + ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) + +#define MmPci64( Segment, Bus, Device, Function, Register ) \ + *MmPci64Ptr( Segment, Bus, Device, Function, Register ) + +#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \ + MmPci64( Segment, Bus, Device, Function, Register ) = \ + (UINT64) ( \ + MmPci64( Segment, Bus, Device, Function, Register ) | \ + (UINT64)(OrData) \ + ) + +#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \ + MmPci64( Segment, Bus, Device, Function, Register ) = \ + (UINT64) ( \ + MmPci64( Segment, Bus, Device, Function, Register ) & \ + (UINT64)(AndData) \ + ) + +#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ + MmPci64( Segment, Bus, Device, Function, Register ) = \ + (UINT64) ( \ + ( MmPci64( Segment, Bus, Device, Function, Register ) & \ + (UINT64)(AndData) \ + ) | \ + (UINT64)(OrData) \ + ) + +// +// UINT32 +// + +#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \ + ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) ) + +#define MmPci32( Segment, Bus, Device, Function, Register ) \ + *MmPci32Ptr( Segment, Bus, Device, Function, Register ) + +#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \ + MmPci32( Segment, Bus, Device, Function, Register ) = \ + (UINT32) ( \ + MmPci32( Segment, Bus, Device, Function, Register ) | \ + (UINT32)(OrData) \ + ) + +#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \ + MmPci32( Segment, Bus, Device, Function, Register ) = \ + (UINT32) ( \ + MmPci32( Segment, Bus, Device, Function, Register ) & \ + (UINT32)(AndData) \ + ) + +#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ + MmPci32( Segment, Bus, Device, Function, Register ) = \ + (UINT32) ( \ + ( MmPci32( Segment, Bus, Device, Function, Register ) & \ + (UINT32)(AndData) \ + ) | \ + (UINT32)(OrData) \ + ) + +// +// UINT16 +// + +#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \ + ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) + +#define MmPci16( Segment, Bus, Device, Function, Register ) \ + *MmPci16Ptr( Segment, Bus, Device, Function, Register ) + +#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \ + MmPci16( Segment, Bus, Device, Function, Register ) = \ + (UINT16) ( \ + MmPci16( Segment, Bus, Device, Function, Register ) | \ + (UINT16)(OrData) \ + ) + +#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \ + MmPci16( Segment, Bus, Device, Function, Register ) = \ + (UINT16) ( \ + MmPci16( Segment, Bus, Device, Function, Register ) & \ + (UINT16)(AndData) \ + ) + +#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ + MmPci16( Segment, Bus, Device, Function, Register ) = \ + (UINT16) ( \ + ( MmPci16( Segment, Bus, Device, Function, Register ) & \ + (UINT16)(AndData) \ + ) | \ + (UINT16)(OrData) \ + ) + +// +// UINT8 +// + +#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \ + ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) + +#define MmPci8( Segment, Bus, Device, Function, Register ) \ + *MmPci8Ptr( Segment, Bus, Device, Function, Register ) + +#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \ + MmPci8( Segment, Bus, Device, Function, Register ) = \ + (UINT8) ( \ + MmPci8( Segment, Bus, Device, Function, Register ) | \ + (UINT8)(OrData) \ + ) + +#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \ + MmPci8( Segment, Bus, Device, Function, Register ) = \ + (UINT8) ( \ + MmPci8( Segment, Bus, Device, Function, Register ) & \ + (UINT8)(AndData) \ + ) + +#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ + MmPci8( Segment, Bus, Device, Function, Register ) = \ + (UINT8) ( \ + ( MmPci8( Segment, Bus, Device, Function, Register ) & \ + (UINT8)(AndData) \ + ) | \ + (UINT8)(OrData) \ + ) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h new file mode 100644 index 0000000000..e6d232103b --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h @@ -0,0 +1,54 @@ +/*++ + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchInitVar.h + +Abstract: + + This file defines variable shared between PCH Init DXE driver and PCH + Init S3 Resume PEIM. + +--*/ +#ifndef _PCH_INIT_VAR_H_ +#define _PCH_INIT_VAR_H_ + +#include +// +// Define the PCH Init Var GUID +// +#define PCH_INIT_VARIABLE_GUID {0xe6c2f70a, 0xb604, 0x4877,{0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}} +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchInitVariableGuid; + +#define PCH_INIT_VARIABLE_NAME L"PchInit" + +// +// Define the Pch Init Variable structure +// +typedef struct { + UINT32 StorePosition; + UINT32 ExecutePosition; +} PCH_S3_PARAMETER_HEADER; + +#pragma pack(1) +typedef struct _PCH_INIT_VARIABLE { + PCH_S3_PARAMETER_HEADER *PchS3Parameter; +} PCH_INIT_VARIABLE; +#pragma pack() + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h new file mode 100644 index 0000000000..52ce58e303 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h @@ -0,0 +1,40 @@ +/*++ + +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SataControllerGuid.h + +Abstract: + + GUID for use in describing SataController + +--*/ +#ifndef _SERIAL_ATA_CONTROLLER_GUID_H_ +#define _SERIAL_ATA_CONTROLLER_GUID_H_ + +#ifdef ECP_FLAG +#define PCH_SATA_CONTROLLER_DRIVER_GUID \ + { \ + 0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \ + } +#else +#define PCH_SATA_CONTROLLER_DRIVER_GUID \ + {\ + 0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \} + +#endif + +extern EFI_GUID gSataControllerDriverGuid; +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h new file mode 100644 index 0000000000..4e69679a32 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h @@ -0,0 +1,36 @@ +// +// +/*++ + +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmbusArpMap.h + +Abstract: + + GUID for use in describing SMBus devices that were ARPed during PEI. + +--*/ +#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_ +#define _EFI_SMBUS_ARP_MAP_GUID_H_ + +#define EFI_SMBUS_ARP_MAP_GUID \ + { \ + 0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \ + } + +extern EFI_GUID gEfiSmbusArpMapGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h new file mode 100644 index 0000000000..64d91f0e30 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h @@ -0,0 +1,34 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Vlv2Variable.h + +Abstract: + + GUID used to define ValleyView2 variable. + +--*/ + +#ifndef _VLV2_VARIABLE_GUID_H_ +#define _VLV2_VARIABLE_GUID_H_ + +#define EFI_VLV2_VARIABLE \ + { \ + 0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5 } \ + } +extern EFI_GUID gEfiVlv2VariableGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h new file mode 100644 index 0000000000..b641ccb42a --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h @@ -0,0 +1,132 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ + +Module Name: + + CEATA.h + +Abstract: + + Header file for chipset CE-AT spec. + +--*/ + +#ifndef _CE_ATA_H +#define _CE_ATA_H + +#pragma pack(1) + + +#define DATA_UNIT_SIZE 512 + + +#define CMD60 60 +#define CMD61 61 + + +#define RW_MULTIPLE_REGISTER CMD60 +#define RW_MULTIPLE_BLOCK CMD61 + + +#define CE_ATA_SIG_CE 0xCE +#define CE_ATA_SIG_AA 0xAA + + +#define Reg_Features_Exp 01 +#define Reg_SectorCount_Exp 02 +#define Reg_LBALow_Exp 03 +#define Reg_LBAMid_Exp 04 +#define Reg_LBAHigh_Exp 05 +#define Reg_Control 06 +#define Reg_Features_Error 09 +#define Reg_SectorCount 10 +#define Reg_LBALow 11 +#define Reg_LBAMid 12 +#define Reg_LBAHigh 13 +#define Reg_Device_Head 14 +#define Reg_Command_Status 15 + +#define Reg_scrTempC 0x80 +#define Reg_scrTempMaxP 0x84 +#define Reg_scrTempMinP 0x88 +#define Reg_scrStatus 0x8C +#define Reg_scrReallocsA 0x90 +#define Reg_scrERetractsA 0x94 +#define Reg_scrCapabilities 0x98 +#define Reg_scrControl 0xC0 + + + +typedef struct { + UINT8 Reserved0; + UINT8 Features_Exp; + UINT8 SectorCount_Exp; + UINT8 LBALow_Exp; + UINT8 LBAMid_Exp; + UINT8 LBAHigh_Exp; + UINT8 Control; + UINT8 Reserved1[2]; + UINT8 Features_Error; + UINT8 SectorCount; + UINT8 LBALow; + UINT8 LBAMid; + UINT8 LBAHigh; + UINT8 Device_Head; + UINT8 Command_Status; +} TASK_FILE; + + +// +//Reduced ATA command set +// +#define IDENTIFY_DEVICE 0xEC +#define READ_DMA_EXT 0x25 +#define WRITE_DMA_EXT 0x35 +#define STANDBY_IMMEDIATE 0xE0 +#define FLUSH_CACHE_EXT 0xEA + + + +typedef struct { + UINT16 Reserved0[10]; + UINT16 SerialNumber[10]; + UINT16 Reserved1[3]; + UINT16 FirmwareRevision[4]; + UINT16 ModelNumber[20]; + UINT16 Reserved2[33]; + UINT16 MajorVersion; + UINT16 Reserved3[19]; + UINT16 MaximumLBA[4]; + UINT16 Reserved4[2]; + UINT16 Sectorsize; + UINT16 Reserved5; + UINT16 DeviceGUID[4]; + UINT16 Reserved6[94]; + UINT16 Features; + UINT16 MaxWritesPerAddress; + UINT16 Reserved7[47]; + UINT16 IntegrityWord; +} IDENTIFY_DEVICE_DATA; + + + + + +#pragma pack() + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h new file mode 100644 index 0000000000..2d5427ade9 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h @@ -0,0 +1,355 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ + +Module Name: + + MMC.h + +Abstract: + + Header file for Industry MMC 4.2 spec. + +--*/ + +#ifndef _MMC_H +#define _MMC_H + +#pragma pack(1) +// +//Command definition +// + +#define CMD0 0 +#define CMD1 1 +#define CMD2 2 +#define CMD3 3 +#define CMD4 4 +#define CMD6 6 +#define CMD7 7 +#define CMD8 8 +#define CMD9 9 +#define CMD10 10 +#define CMD11 11 +#define CMD12 12 +#define CMD13 13 +#define CMD14 14 +#define CMD15 15 +#define CMD16 16 +#define CMD17 17 +#define CMD18 18 +#define CMD19 19 +#define CMD20 20 +#define CMD23 23 +#define CMD24 24 +#define CMD25 25 +#define CMD26 26 +#define CMD27 27 +#define CMD28 28 +#define CMD29 29 +#define CMD30 30 +#define CMD35 35 +#define CMD36 36 +#define CMD38 38 +#define CMD39 39 +#define CMD40 40 +#define CMD42 42 +#define CMD55 55 +#define CMD56 56 + + + +#define GO_IDLE_STATE CMD0 +#define SEND_OP_COND CMD1 +#define ALL_SEND_CID CMD2 +#define SET_RELATIVE_ADDR CMD3 +#define SET_DSR CMD4 +#define SWITCH CMD6 +#define SELECT_DESELECT_CARD CMD7 +#define SEND_EXT_CSD CMD8 +#define SEND_CSD CMD9 +#define SEND_CID CMD10 +#define READ_DAT_UNTIL_STOP CMD11 +#define STOP_TRANSMISSION CMD12 +#define SEND_STATUS CMD13 +#define BUSTEST_R CMD14 +#define GO_INACTIVE_STATE CMD15 +#define SET_BLOCKLEN CMD16 +#define READ_SINGLE_BLOCK CMD17 +#define READ_MULTIPLE_BLOCK CMD18 +#define BUSTEST_W CMD19 +#define WRITE_DAT_UNTIL_STOP CMD20 +#define SET_BLOCK_COUNT CMD23 +#define WRITE_BLOCK CMD24 +#define WRITE_MULTIPLE_BLOCK CMD25 +#define PROGRAM_CID CMD26 +#define PROGRAM_CSD CMD27 +#define SET_WRITE_PROT CMD28 +#define CLR_WRITE_PROT CMD29 +#define SEND_WRITE_PROT CMD30 +#define ERASE_GROUP_START CMD35 +#define ERASE_GROUP_END CMD36 +#define ERASE CMD38 +#define FAST_IO CMD39 +#define GO_IRQ_STATE CMD40 +#define LOCK_UNLOCK CMD42 +#define APP_CMD CMD55 +#define GEN_CMD CMD56 + +#define B_PERM_WP_DIS 0x10 +#define B_PWR_WP_EN 0x01 +#define US_PERM_WP_DIS 0x10 +#define US_PWR_WP_EN 0x01 + +#define FREQUENCY_OD (400 * 1000) +#define FREQUENCY_MMC_PP (26 * 1000 * 1000) +#define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000) + +#define DEFAULT_DSR_VALUE 0x404 + +// +//Registers definition +// + +typedef struct { + UINT32 Reserved0: 7; // 0 + UINT32 V170_V195: 1; // 1.70V - 1.95V + UINT32 V200_V260: 7; // 2.00V - 2.60V + UINT32 V270_V360: 9; // 2.70V - 3.60V + UINT32 Reserved1: 5; // 0 + UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode) + UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine +} OCR; + + +typedef struct { + UINT8 NotUsed: 1; // 1 + UINT8 CRC: 7; // CRC7 checksum + UINT8 MDT; // Manufacturing date + UINT32 PSN; // Product serial number + UINT8 PRV; // Product revision + UINT8 PNM[6]; // Product name + UINT16 OID; // OEM/Application ID + UINT8 MID; // Manufacturer ID +} CID; + + +typedef struct { + UINT8 NotUsed: 1; // 1 [0:0] + UINT8 CRC: 7; // CRC [7:1] + UINT8 ECC: 2; // ECC code [9:8] + UINT8 FILE_FORMAT: 2; // File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] + UINT8 COPY: 1; // Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] + UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16] + UINT16 Reserved0: 4; // 0 [20:17] + UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] + UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32] + UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37] + UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42] + UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47] + UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50] + UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53] + UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56] + UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59] + UINT32 C_SIZELow2: 2;// Device size [73:62] + UINT32 C_SIZEHigh10: 10;// Device size [73:62] + UINT32 Reserved1: 2; // 0 [75:74] + UINT32 DSR_IMP: 1; // DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] + UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80] + UINT32 CCC: 12;// Card command classes [95:84] + UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] + UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; // Data read access-time 1 [119:112] + UINT8 Reserved2: 2; // 0 [121:120] + UINT8 SPEC_VERS: 4; // System specification version [125:122] + UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] +} CSD; + +typedef struct { + UINT8 Reserved133_0[134]; // [133:0] 0 + UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode + UINT8 Reserved135; // [135] 0 + UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address + UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size + UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size + UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size + UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size + UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size + UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting + UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes + UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size + UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support + UINT8 HPI_MGMT; // [161] HPI management + UINT8 RST_n_FUNCTION; // [162] H/W reset function + UINT8 BKOPS_EN; // [163] Enable background operations handshake + UINT8 BKOPS_START; // [164] Manually start background operations + UINT8 Reserved165; // [165] 0 + UINT8 WR_REL_PARAM; // [166] Write reliability parameter register + UINT8 WR_REL_SET; // [167] Write reliability setting register + UINT8 RPMB_SIZE_MULT; // [168] RPMB Size + UINT8 FW_CONFIG; // [169] FW configuration + UINT8 Reserved170; // [170] 0 + UINT8 USER_WP; // [171] User area write protection + UINT8 Reserved172; // [172] 0 + UINT8 BOOT_WP; // [173] Boot area write protection + UINT8 Reserved174; // [174] 0 + UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition + UINT8 Reserved176; // [176] 0 + UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width + UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection + UINT8 PARTITION_CONFIG; // [179] Partition config + UINT8 Reserved180; // [180] 0 + UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content + UINT8 Reserved182; // [182] 0 + UINT8 BUS_WIDTH; // [183] Bus Width Mode + UINT8 Reserved184; // [184] 0 + UINT8 HS_TIMING; // [185] High Speed Interface Timing + UINT8 Reserved186; // [186] 0 + UINT8 POWER_CLASS; // [187] Power Class + UINT8 Reserved188; // [188] 0 + UINT8 CMD_SET_REV; // [189] Command Set Revision + UINT8 Reserved190; // [190] 0 + UINT8 CMD_SET; // [191] Command Set + UINT8 EXT_CSD_REV; // [192] Extended CSD Revision + UINT8 Reserved193; // [193] 0 + UINT8 CSD_STRUCTURE; // [194] CSD Structure Version + UINT8 Reserved195; // [195] 0 + UINT8 CARD_TYPE; // [196] Card Type + UINT8 Reserved197; // [197] 0 + UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing + UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing + UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V + UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V + UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V + UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V + UINT8 Reserved204; // [204] 0 + UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz + UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz + UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz + UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz + UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz + UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz + UINT8 Reserved211; // [211] 0 + UINT8 SEC_COUNT[4]; // [215:212] Sector Count + UINT8 Reserved216; // [216] 0 + UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout + UINT8 Reserved218; // [218] 0 + UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ) + UINT8 S_C_VCC; // [220] Sleep current (VCC) + UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size + UINT8 REL_WR_SEC_C; // [222] Reliable write sector count + UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout + UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size + UINT8 ACC_SIZE; // [225] Access size + UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size + UINT8 Reserved227; // [227] 0 + UINT8 BOOT_INFO; // [228] Boot information + UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier + UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier + UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support + UINT8 TRIM_MULT; // [232] TRIM Multiplier + UINT8 Reserved233; // [233] 0 + UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz + UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz + UINT8 Reserved237_236[2]; // [237:236] 0 + UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V + UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V + UINT8 Reserved240; // [240] 0 + UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning + UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors + UINT8 BKOPS_STATUS; // [246] Background operations status + UINT8 Reserved501_247[255]; // [501:247] 0 + UINT8 BKOPS_SUPPORT; // [502] Background operations support + UINT8 HPI_FEATURES; // [503] HPI features + UINT8 S_CMD_SET; // [504] Sector Count + UINT8 Reserved511_505[7]; // [511:505] Sector Count +} EXT_CSD; + + +// +//Card Status definition +// +typedef struct { + UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode + UINT32 Reserved1: 2; //Reserved for Application Specific commands + UINT32 Reserved2: 1; // + UINT32 SAPP_CMD: 1; // + UINT32 Reserved3: 1; //Reserved + UINT32 SWITCH_ERROR: 1; // + UINT32 READY_FOR_DATA: 1; // + UINT32 CURRENT_STATE: 4; // + UINT32 ERASE_RESET: 1; // + UINT32 Reserved4: 1; //Reserved + UINT32 WP_ERASE_SKIP: 1; // + UINT32 CID_CSD_OVERWRITE: 1; // + UINT32 OVERRUN: 1; // + UINT32 UNDERRUN: 1; // + UINT32 ERROR: 1; // + UINT32 CC_ERROR: 1; // + UINT32 CARD_ECC_FAILED: 1; // + UINT32 ILLEGAL_COMMAND: 1; // + UINT32 COM_CRC_ERROR: 1; // + UINT32 LOCK_UNLOCK_FAILED: 1; // + UINT32 CARD_IS_LOCKED: 1; // + UINT32 WP_VIOLATION: 1; // + UINT32 ERASE_PARAM: 1; // + UINT32 ERASE_SEQ_ERROR: 1; // + UINT32 BLOCK_LEN_ERROR: 1; // + UINT32 ADDRESS_MISALIGN: 1; // + UINT32 ADDRESS_OUT_OF_RANGE:1; // +} CARD_STATUS; + +typedef struct { + UINT32 CmdSet: 3; + UINT32 Reserved0: 5; + UINT32 Value: 8; + UINT32 Index: 8; + UINT32 Access: 2; + UINT32 Reserved1: 6; +} SWITCH_ARGUMENT; + +#define CommandSet_Mode 0 +#define SetBits_Mode 1 +#define ClearBits_Mode 2 +#define WriteByte_Mode 3 + + +#define Idle_STATE 0 +#define Ready_STATE 1 +#define Ident_STATE 2 +#define Stby_STATE 3 +#define Tran_STATE 4 +#define Data_STATE 5 +#define Rcv_STATE 6 +#define Prg_STATE 7 +#define Dis_STATE 8 +#define Btst_STATE 9 + + + +#pragma pack() +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h new file mode 100644 index 0000000000..835800d782 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h @@ -0,0 +1,163 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ +Module Name: + + SDCard.h + +Abstract: + + Header file for Industry SD Card 2.0 spec. + +--*/ + +#ifndef _SD_CARD_H +#define _SD_CARD_H + +#include "Mmc.h" + +#pragma pack(1) + +#define CHECK_PATTERN 0xAA + +#define ACMD6 6 +#define ACMD13 13 +#define ACMD23 23 +#define ACMD41 41 +#define ACMD42 42 +#define ACMD51 51 + + +#define SWITCH_FUNC CMD6 +#define SEND_IF_COND CMD8 + + +#define SET_BUS_WIDTH ACMD6 +#define SD_STATUS ACMD13 +#define SET_WR_BLK_ERASE_COUNT ACMD23 +#define SD_SEND_OP_COND ACMD41 +#define SET_CLR_CARD_DETECT ACMD42 +#define SEND_SCR ACMD51 + + + +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 + + + +#define FREQUENCY_SD_PP (25 * 1000 * 1000) +#define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000) + + +#define SD_SPEC_10 0 +#define SD_SPEC_11 1 +#define SD_SPEC_20 2 + + +#define VOLTAGE_27_36 0x1 + +typedef struct { + UINT8 NotUsed: 1; // 1 [0:0] + UINT8 CRC: 7; // CRC [7:1] + UINT8 ECC: 2; // ECC code [9:8] + UINT8 FILE_FORMAT: 2; // File format [11:10] + UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12] + UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13] + UINT8 COPY: 1; // Copy flag (OTP) [14:14] + UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15] + UINT16 Reserved0: 5; // 0 [20:16] + UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21] + UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22] + UINT16 R2W_FACTOR: 3; // Write speed factor [28:26] + UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29] + UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31] + UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32] + UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39] + UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46] + UINT16 Reserved1: 1; // 0 [47:47] + + UINT32 C_SIZE: 22; // Device size [69:48] + UINT32 Reserved2: 6; // 0 [75:70] + UINT32 DSR_IMP: 1; // DSR implemented [76:76] + UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77] + UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78] + UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79] + + UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80] + UINT16 CCC: 12; // Card command classes [95:84] + UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96] + UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104] + UINT8 TAAC ; // Data read access-time 1 [119:112] + UINT8 Reserved3: 6; // 0 [125:120] + UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126] +} CSD_SDV2; + +typedef struct { + UINT32 Reserved0; + UINT32 Reserved1: 16; + UINT32 SD_BUS_WIDTH: 4; + UINT32 SD_SECURITY: 3; + UINT32 DATA_STAT_AFTER_ERASE: 1; + UINT32 SD_SPEC: 4; + UINT32 SCR_STRUCT: 4; +} SCR; + + +typedef struct { + UINT8 Reserved0[50]; + UINT8 ERASE_OFFSET: 2; + UINT8 ERASE_TIMEOUT: 6; + UINT16 ERASE_SIZE; + UINT8 Reserved1: 4; + UINT8 AU_SIZE: 4; + UINT8 PERFORMANCE_MOVE; + UINT8 SPEED_CLASS; + UINT32 SIZE_OF_PROTECTED_AREA; + UINT32 SD_CARD_TYPE: 16; + UINT32 Reserved2: 13; + UINT32 SECURED_MODE: 1; + UINT32 DAT_BUS_WIDTH: 2; +} SD_STATUS_REG; + + + +typedef struct { + UINT8 Reserved0[34]; + UINT16 Group1BusyStatus; + UINT16 Group2BusyStatus; + UINT16 Group3BusyStatus; + UINT16 Group4BusyStatus; + UINT16 Group5BusyStatus; + UINT16 Group6BusyStatus; + UINT8 DataStructureVersion; + UINT8 Group21Status; + UINT8 Group43Status; + UINT8 Group65Status; + UINT16 Group1Function; + UINT16 Group2Function; + UINT16 Group3Function; + UINT16 Group4Function; + UINT16 Group5Function; + UINT16 Group6Function; + UINT16 MaxCurrent; +} SWITCH_STATUS; + + +#pragma pack() +#endif + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h new file mode 100644 index 0000000000..9173364c48 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h @@ -0,0 +1,175 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + I2CRegs.h + +Abstract: + + Register Definitions for I2C Driver/PEIM. + +--*/ +#include +#include + +#ifndef I2C_REGS_A0_H +#define I2C_REGS_A0_H + +// +// FIFO write workaround value. +// +#define FIFO_WRITE_DELAY 2 + +// +// MMIO Register Definitions +// +#define R_IC_CON ( 0x00) // I2C Control +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_SPEED_STANDARD 0x02 +#define V_SPEED_FAST 0x04 +#define V_SPEED_HIGH 0x06 +#define B_MASTER_MODE BIT0 + +#define R_IC_TAR ( 0x04) // I2C Target Address +#define IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_SAR ( 0x08) // I2C Slave Address +#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address +#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command + +#define B_READ_CMD BIT8 // 1 = read, 0 = write +#define B_CMD_STOP BIT9 // 1 = STOP +#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN + +#define V_WRITE_CMD_MASK ( 0xFF) + +#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count +#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count +#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count +#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count +#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count +#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count +#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status +#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask +#define I2C_INTR_GEN_CALL BIT11 // General call received +#define I2C_INTR_START_DET BIT10 +#define I2C_INTR_STOP_DET BIT9 +#define I2C_INTR_ACTIVITY BIT8 +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK +#define I2C_INTR_TX_EMPTY BIT4 +#define I2C_INTR_TX_OVER BIT3 +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold +#define I2C_INTR_RX_OVER BIT1 +#define I2C_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status +#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold +#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt +#define R_IC_ENABLE ( 0x6C) // I2C Enable +#define R_IC_STATUS ( 0x70) // I2C Status + +#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits + +#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status. +#define STAT_RFF BIT4 // RX FIFO is completely full +#define STAT_RFNE BIT3 // RX FIFO is not empty +#define STAT_TFE BIT2 // TX FIFO is completely empty +#define STAT_TFNF BIT1 // TX FIFO is not full + +#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register +#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register +#define R_IC_DMA_CR ( 0x88) // DMA Control Register +#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level +#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level +#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register +#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register +#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID +#define R_IC_COMP_TYPE ( 0xFC) // Component Type + +#define R_IC_CLK_GATE ( 0xC0) // Clock Gate + +#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD +#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4 +#define I2C_FS_SCL_HCNT_VALUE_100M 0x54 +#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a +#define I2C_HS_SCL_HCNT_VALUE_100M 0x7 +#define I2C_HS_SCL_LCNT_VALUE_100M 0xE + +#define IC_TAR_10BITADDR_MASTER BIT12 +#define FIFO_SIZE 32 +#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status +#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask +#define I2C_INTR_GEN_CALL BIT11 // General call received +#define I2C_INTR_START_DET BIT10 +#define I2C_INTR_STOP_DET BIT9 +#define I2C_INTR_ACTIVITY BIT8 +#define I2C_INTR_TX_ABRT BIT6 // Set on NACK +#define I2C_INTR_TX_EMPTY BIT4 +#define I2C_INTR_TX_OVER BIT3 +#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold +#define I2C_INTR_RX_OVER BIT1 +#define I2C_INTR_RX_UNDER BIT0 + +EFI_STATUS ProgramPciLpssI2C ( + IN UINT8 BusNo + ); +EFI_STATUS ByteReadI2C_Basic( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer, + IN UINT8 Start, + IN UINT8 End + ); +EFI_STATUS ByteWriteI2C_Basic( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT8 Start, + IN UINT8 End + ); + +EFI_STATUS ByteReadI2C( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer + ); +EFI_STATUS ByteWriteI2C( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer + ); + +#endif // I2C_REGS_A0_H diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h new file mode 100644 index 0000000000..8f0ca027b4 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h @@ -0,0 +1,121 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + @file + PchPlatformLib.h + + @brief + Header file for PchPlatform Lib. + +**/ +#ifndef _PCH_PLATFORM_LIB_H_ +#define _PCH_PLATFORM_LIB_H_ + +/// +/// Timeout value used when Sending / Receiving messages. +/// NOTE: this must cover the longest possible wait time +/// between message being sent and response being available. +/// e.g. Virtual function readiness might take some time. +/// +VOID +EFIAPI +PchPmTimerStall ( + IN UINTN Microseconds + ) +/** + + @brief + Delay for at least the request number of microseconds. + This function would be called by runtime driver, please do not use any MMIO marco here. + + @param[in] Microseconds Number of microseconds to delay. + + @retval NONE + +**/ +; + +BOOLEAN +EFIAPI +PchIsSpiDescriptorMode ( + IN UINTN SpiBase + ) +/** + + @brief + Check whether SPI is in descriptor mode + + @param[in] SpiBase The PCH Spi Base Address + + @retval TRUE SPI is in descriptor mode + @retval FALSE SPI is not in descriptor mode + +**/ +; + +PCH_STEPPING +EFIAPI +PchStepping ( + VOID + ) +/** + + @brief + Return Pch stepping type + + @param[in] None + + @retval PCH_STEPPING Pch stepping type + +**/ +; + +BOOLEAN +IsPchSupported ( + VOID + ) +/** + + @brief + Determine if PCH is supported + + @param[in] None + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported + +**/ +; + +VOID +EFIAPI +PchAlternateAccessMode ( + IN UINTN IlbBase, + IN BOOLEAN AmeCtrl + ) +/** + + This function can be called to enable/disable Alternate Access Mode + + @param[in] IlbBase The PCH ILB Base Address + @param[in] AmeCtrl If TRUE, enable Alternate Access Mode. + If FALSE, disable Alternate Access Mode. + + @retval NONE + +**/ +; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h new file mode 100644 index 0000000000..3f44d2bfa9 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h @@ -0,0 +1,526 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchAccess.h + + @brief + Macros that simplify accessing PCH devices's PCI registers. + + ** NOTE ** these macros assume the PCH device is on BUS 0 + +**/ +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchRegs.h" +#include "PchCommonDefinitions.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + +/// +/// Memory Mapped PCI Access macros +/// +/// +/// PCI Device MM Base +/// +#ifndef MmPciAddress +#define MmPciAddress(Segment, Bus, Device, Function, Register) \ + ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \ + (UINTN) (Bus << 20) + \ + (UINTN) (Device << 15) + \ + (UINTN) (Function << 12) + \ + (UINTN) (Register) \ + ) +#endif +/// +/// Pch Controller PCI access macros +/// +#define PCH_RCRB_BASE ( \ + MmioRead32 (MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + PCI_FUNCTION_NUMBER_PCH_LPC), \ + R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \ + ) + +/// +/// Device 0x1b, Function 0 +/// +#define PchAzaliaPciCfg32(Register) \ + MmioRead32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register) \ + ) + +#define PchAzaliaPciCfg32Or(Register, OrData) \ + MmioOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchAzaliaPciCfg32And(Register, AndData) \ + MmioAnd32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchAzaliaPciCfg16(Register) \ + MmioRead16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register) \ + ) + +#define PchAzaliaPciCfg16Or(Register, OrData) \ + MmioOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchAzaliaPciCfg16And(Register, AndData) \ + MmioAnd16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + AndData, \ + OrData \ + ) + +#define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register)) + +#define PchAzaliaPciCfg8Or(Register, OrData) \ + MmioOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchAzaliaPciCfg8And(Register, AndData) \ + MmioAnd8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_AZALIA, \ + 0, \ + Register), \ + AndData, \ + OrData \ + ) + +/// +/// Device 0x1f, Function 0 +/// +#define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register)) + +#define PchLpcMmioOr32 (Register, OrData) \ + MmioOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchLpcPciCfg32And(Register, AndData) \ + MmioAnd32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData, \ + OrData \ + ) + +#define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register)) + +#define PchLpcPciCfg16Or(Register, OrData) \ + MmioOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchLpcPciCfg16And(Register, AndData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData, \ + OrData \ + ) + +#define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register)) + +#define PchLpcPciCfg8Or(Register, OrData) \ + MmioOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + OrData \ + ) + +#define PchLpcPciCfg8And(Register, AndData) \ + MmioAnd8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData \ + ) + +#define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_LPC, \ + 0, \ + Register), \ + AndData, \ + OrData \ + ) + + +/// +/// SATA device 0x13, Function 0 +/// +#define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register)) + +#define PchSataPciCfg32Or(Register, OrData) \ + MmioOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + OrData \ + ) + +#define PchSataPciCfg32And(Register, AndData) \ + MmioAnd32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData \ + ) + +#define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr32 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + +#define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register)) + +#define PchSataPciCfg16Or(Register, OrData) \ + MmioOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + OrData \ + ) + +#define PchSataPciCfg16And(Register, AndData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData \ + ) + +#define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr16 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + +#define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register)) + +#define PchSataPciCfg8Or(Register, OrData) \ + MmioOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + OrData \ + ) + +#define PchSataPciCfg8And(Register, AndData) \ + MmioAnd8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData \ + ) + +#define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \ + MmioAndThenOr8 ( \ + MmPciAddress (0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_SATA, \ + PCI_FUNCTION_NUMBER_PCH_SATA, \ + Register), \ + AndData, \ + OrData \ + ) + + +/// +/// Root Complex Register Block +/// +#define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register) + +#define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData) + +#define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData) + +#define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData) + +#define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register) + +#define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData) + +#define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData) + +#define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData) + +#define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register) + +#define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData) + +#define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData) + +#define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData) + + +/// +/// Message Bus +/// + +/// +/// Message Bus Registers +/// +#define MC_MCR 0x000000D0 // Cunit Message Control Register +#define MC_MDR 0x000000D4 // Cunit Message Data Register +#define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension + +/// +/// Message Bus API +/// +#define MSG_BUS_ENABLED 0x000000F0 +#define MSGBUS_MASKHI 0xFFFFFF00 +#define MSGBUS_MASKLO 0x000000FF +#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7 + +#define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \ +{ \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ +} + +#define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \ +{ \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ +} + +#define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \ +{ \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ +} + +#define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \ +{ \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ +} + +typedef struct _PCH_MSG_BUS_TABLE_STRUCT { + UINT32 PortId; + UINT32 Address; + UINT32 AndMask; + UINT32 OrMask; + UINT32 ReadOpCode; + UINT32 WriteOpCode; +} PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT; + +#ifndef _S3SUPPORT_ +#define _S3SUPPORT_ +UINTN MCRX; +UINTN MCR; +// +// In S3 execute, we should follow the MSG BUS access procedure to restore the saving data. +// To do so, we adopt READ ->> SAVE +// Indirect IO access: (According BayTrail-M EDS chapter 3.6) +// 1. Write Index port into MSG BUS_MCRX first. +// 2. Write content to data register which is called MSG BUS_MDR. +// 3. Send "message bus control" to complete the procedure. +// +#define S3BootScriptSaveMsgBusToMemWrite(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \ +{ \ + MCRX = (UINTN) Register & MSGBUS_MASKHI; \ + MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1, (VOID *) (UINTN) &MCRX); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \ + (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1, (VOID *) &Dbuff); \ + MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1, (VOID *) (UINTN) &MCR); \ +} + +// +// This macro combines two function: 1. PchMsgBusAndThenOr32 () 2. S3 boot script save +// +#define PchMsgBusAndThenOr32AddToS3Save(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \ +{ \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \ + MCRX = (UINTN) Register & MSGBUS_MASKHI; \ + MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1,(VOID *) (UINTN) &MCRX); \ + MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \ + (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1,(VOID *) &Dbuff); \ + MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \ + S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1,(VOID *) (UINTN) &MCR); \ +} + +#endif + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h new file mode 100644 index 0000000000..29002cc842 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h @@ -0,0 +1,216 @@ +/*++ + +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchCommonDefinitions.h + +Abstract: + + This header file provides common definitions for PCH + +--*/ +#ifndef _PCH_COMMON_DEFINITIONS_H_ +#define _PCH_COMMON_DEFINITIONS_H_ + +// +// MMIO access macros +// +#define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register)) + +// +// 32 bit MMIO access +// +#define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register)) + +#define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register) + +#define PchMmio32Or(BaseAddr, Register, OrData) \ + PchMmio32 (BaseAddr, Register) = (UINT32) \ + (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData)) + +#define PchMmio32And(BaseAddr, Register, AndData) \ + PchMmio32 (BaseAddr, Register) = (UINT32) \ + (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) + +#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \ + PchMmio32 (BaseAddr, Register) = (UINT32) \ + ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData)) + +// +// 16 bit MMIO access +// +#define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register)) + +#define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register) + +#define PchMmio16Or(BaseAddr, Register, OrData) \ + PchMmio16 (BaseAddr, Register) = (UINT16) \ + (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData)) + +#define PchMmio16And(BaseAddr, Register, AndData) \ + PchMmio16 (BaseAddr, Register) = (UINT16) \ + (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) + +#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \ + PchMmio16 (BaseAddr, Register) = (UINT16) \ + ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData)) + +// +// 8 bit MMIO access +// +#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register)) + +#define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register) + +#define PchMmio8Or(BaseAddr, Register, OrData) \ + PchMmio8 (BaseAddr, Register) = (UINT8) \ + (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData)) + +#define PchMmio8And(BaseAddr, Register, AndData) \ + PchMmio8 (BaseAddr, Register) = (UINT8) \ + (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) + +#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \ + PchMmio8 (BaseAddr, Register) = (UINT8) \ + ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData)) + +// +// Memory Mapped PCI Access macros +// +#define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000 +// +// PCI Device MM Base +// +#define PchPciDeviceMmBase(Bus, Device, Function) \ + ( \ + (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \ + (Function << 12) \ + ) + +// +// PCI Device MM Address +// +#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \ + ( \ + (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \ + (Function << 12) + (UINTN) (Register) \ + ) + +// +// 32 bit PCI access +// +#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \ + ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register)) + +#define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register) + +#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \ + PchMmPci32 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData)) + +#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \ + PchMmPci32 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) + +#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \ + PchMmPci32 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData)) + +// +// 16 bit PCI access +// +#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \ + ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register)) + +#define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register) + +#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \ + PchMmPci16 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData)) + +#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \ + PchMmPci16 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) + +#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \ + PchMmPci16 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData)) + +// +// 8 bit PCI access +// +#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \ + ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register)) + +#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register) + +#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \ + PchMmPci8 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData)) + +#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \ + PchMmPci8 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) + +#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \ + PchMmPci8 ( \ + Segment, \ + Bus, \ + Device, \ + Function, \ + Register \ + ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData)) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h new file mode 100644 index 0000000000..21ca877bd1 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h @@ -0,0 +1,211 @@ +/** + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegs.h + + @brief + Register names for VLV SC. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_H_ +#define _PCH_REGS_H_ + +/// +/// Bit Definitions. BUGBUG: drive these definitions to code base. Should not need +/// to be part of chipset modules +/// +#ifndef BIT0 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x100000000 +#define BIT33 0x200000000 +#define BIT34 0x400000000 +#define BIT35 0x800000000 +#define BIT36 0x1000000000 +#define BIT37 0x2000000000 +#define BIT38 0x4000000000 +#define BIT39 0x8000000000 +#define BIT40 0x10000000000 +#define BIT41 0x20000000000 +#define BIT42 0x40000000000 +#define BIT43 0x80000000000 +#define BIT44 0x100000000000 +#define BIT45 0x200000000000 +#define BIT46 0x400000000000 +#define BIT47 0x800000000000 +#define BIT48 0x1000000000000 +#define BIT49 0x2000000000000 +#define BIT50 0x4000000000000 +#define BIT51 0x8000000000000 +#define BIT52 0x10000000000000 +#define BIT53 0x20000000000000 +#define BIT54 0x40000000000000 +#define BIT55 0x80000000000000 +#define BIT56 0x100000000000000 +#define BIT57 0x200000000000000 +#define BIT58 0x400000000000000 +#define BIT59 0x800000000000000 +#define BIT60 0x1000000000000000 +#define BIT61 0x2000000000000000 +#define BIT62 0x4000000000000000 +#define BIT63 0x8000000000000000 +#endif +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +/// +/// Default Vendor ID and Subsystem ID +/// +#define V_PCH_INTEL_VENDOR_ID 0x8086 +#define V_PCH_DEFAULT_SID 0x7270 +#define V_PCH_DEFAULT_SVID_SID (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) + +/// +/// Include device register definitions +/// +#include "PchRegs/PchRegsHda.h" +#include "PchRegs/PchRegsLpss.h" +#include "PchRegs/PchRegsPcie.h" +#include "PchRegs/PchRegsPcu.h" +#include "PchRegs/PchRegsRcrb.h" +#include "PchRegs/PchRegsSata.h" +#include "PchRegs/PchRegsScc.h" +#include "PchRegs/PchRegsSmbus.h" +#include "PchRegs/PchRegsSpi.h" +#include "PchRegs/PchRegsUsb.h" +//#include "PchRegs/PchRegsLpe.h" + +/// +/// Device IDS that are PCH Server specific +/// +#define IS_PCH_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LPC_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LPC_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LPC_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LPC_DEVICE_ID_3) \ + ) + +#define IS_PCH_VLV_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_VLV_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_VLV_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_VLV_SATA_MODE_DEVICE_ID (DeviceId) || \ + IS_PCH_VLV_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_VLV_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_VLV_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \ + ) + +#define IS_PCH_VLV_SATA_MODE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \ + (DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \ + ) +#define IS_PCH_VLV_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_USB_DEVICE_ID_0) || \ + (DeviceId == V_PCH_USB_DEVICE_ID_1) \ + ) +#define IS_PCH_VLV_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \ + (DeviceId == V_PCH_PCIE_DEVICE_ID_7) \ + ) + +/// +/// Any device ID that is Valleyview SC +/// +#define IS_PCH_VLV_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_VLV_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_VLV_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_VLV_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_VLV_PCIE_DEVICE_ID (DeviceId) || \ + (DeviceId) == V_PCH_SMBUS_DEVICE_ID || \ + (DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \ + (DeviceId) == V_PCH_HDA_DEVICE_ID_1 \ + ) + +#define IS_SUPPORTED_DEVICE_ID(DeviceId) IS_PCH_VLV_DEVICE_ID (DeviceId) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h new file mode 100644 index 0000000000..5d68925cb5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h @@ -0,0 +1,56 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsHda.h + + @brief + Register names for PCH High Definition Audio device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +/// +/// Azalia Controller Registers (D27:F0) +/// +#define PCI_DEVICE_NUMBER_PCH_AZALIA 27 +#define PCI_FUNCTION_NUMBER_PCH_AZALIA 0 + +#define R_PCH_HDA_PCS 0x54 // Power Management Control and Status +#define B_PCH_HDA_PCS_DATA 0xFF000000 // Data, does not apply +#define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply +#define B_PCH_HDA_PCS_PMES BIT15 // PME Status +#define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) // Power State - D0/D3 Hot +#define V_PCH_HDA_PCS_PS0 0x00 +#define V_PCH_HDA_PCS_PS3 0x03 + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h new file mode 100644 index 0000000000..4e3cd6c311 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h @@ -0,0 +1,492 @@ +/*++ + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchRegsLpss.h + +Abstract: + + Register names for VLV Low Input Output (LPSS) module. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +--*/ +#ifndef _PCH_REGS_LPSS_H_ +#define _PCH_REGS_LPSS_H_ + + +// +// Low Power Input Output (LPSS) Module Registers +// + +// +// LPSS DMAC Modules +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30 +#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0 + +#define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID +#define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID +#define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID + +#define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command +#define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA +#define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA +#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List +#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status +#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable +#define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable +#define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable +#define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable + +#define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code +#define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code +#define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID + +#define R_PCH_LPSS_DMAC_CLHB 0x0C +#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23 +#define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type +#define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer +#define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size + +#define R_PCH_LPSS_DMAC_BAR 0x10 // BAR +#define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address +#define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000 +#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14 +#define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable +#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space + +#define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1 +#define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address +#define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable +#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space + +#define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID +#define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID +#define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID + +#define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR +#define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address + +#define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer +#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power + +#define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt +#define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency +#define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000 +#define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin +#define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line + +#define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID +#define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support +#define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version +#define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability +#define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability + +#define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status +#define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status +#define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable +#define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset +#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State + +#define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID +#define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID + + +// +// LPSS I2C Module +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7 + +#define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID +#define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID +#define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID + +#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command +#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA +#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA +#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List +#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status +#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable +#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable +#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable +#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable + +#define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code +#define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code +#define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID + +#define R_PCH_LPSS_I2C_CLHB 0x0C +#define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23 +#define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type +#define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer +#define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size + +#define R_PCH_LPSS_I2C_BAR 0x10 // BAR +#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address +#define V_PCH_LPSS_I2C_BAR_SIZE 0x1000 +#define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12 +#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable +#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space + +#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1 +#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address +#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable +#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space + +#define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID +#define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID +#define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID + +#define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR +#define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address + +#define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer +#define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power + +#define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt +#define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency +#define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000 +#define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin +#define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line + +#define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID +#define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support +#define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version +#define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability +#define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability + +#define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status +#define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status +#define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable +#define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset +#define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State + +#define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID +#define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID + +// +// LPSS I2C Module +// Memory Space Registers +// +#define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset +#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset +#define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset + +// +// LPSS PWM Modules +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2 + +#define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID +#define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID +#define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID + +#define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command +#define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA +#define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA +#define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List +#define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status +#define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable +#define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable +#define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable +#define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable + +#define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code +#define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code +#define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID + +#define R_PCH_LPSS_PWM_CLHB 0x0C +#define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23 +#define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type +#define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer +#define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size + +#define R_PCH_LPSS_PWM_BAR 0x10 // BAR +#define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address +#define V_PCH_LPSS_PWM_BAR_SIZE 0x1000 +#define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12 +#define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable +#define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space + +#define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1 +#define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address +#define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable +#define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space + +#define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID +#define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID +#define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID + +#define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR +#define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address + +#define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer +#define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power + +#define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt +#define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency +#define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000 +#define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin +#define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line + +#define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID +#define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support +#define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version +#define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability +#define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability + +#define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status +#define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status +#define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable +#define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset +#define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State + +#define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID +#define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID + +// +// LPSS PWM Module +// Memory Space Registers +// +#define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset +#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset +#define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset + +// +// LPSS HSUART Modules +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4 + +#define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID +#define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID +#define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID + +#define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command +#define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA +#define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA +#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List +#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status +#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable +#define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable +#define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable +#define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable + +#define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code +#define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code +#define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID + +#define R_PCH_LPSS_HSUART_CLHB 0x0C +#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23 +#define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type +#define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer +#define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size + +#define R_PCH_LPSS_HSUART_BAR 0x10 // BAR +#define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address +#define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000 +#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12 +#define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable +#define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space + +#define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1 +#define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address +#define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable +#define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space + +#define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID +#define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID +#define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID + +#define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR +#define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address + +#define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer +#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power + +#define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt +#define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency +#define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000 +#define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin +#define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line + +#define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID +#define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support +#define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version +#define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability +#define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability + +#define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status +#define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status +#define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable +#define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset +#define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State + +#define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID +#define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID + +// +// LPSS HSUART Module +// Memory Space Registers +// +#define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters +#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update +#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider +#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider +#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable + +#define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset +#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset +#define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset + +// +// LPSS SPI Module +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30 +#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5 + +#define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID +#define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID +#define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID + +#define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command +#define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA +#define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA +#define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List +#define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status +#define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable +#define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable +#define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable +#define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable + +#define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code +#define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code +#define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID + +#define R_PCH_LPSS_SPI_CLHB 0x0C +#define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23 +#define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type +#define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer +#define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size + +#define R_PCH_LPSS_SPI_BAR 0x10 // BAR +#define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address +#define V_PCH_LPSS_SPI_BAR_SIZE 0x1000 +#define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12 +#define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable +#define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space + +#define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1 +#define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address +#define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator +#define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable +#define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type +#define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space + +#define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID +#define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID +#define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID + +#define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR +#define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address + +#define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer +#define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power + +#define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt +#define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency +#define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000 +#define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin +#define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line + +#define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID +#define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support +#define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version +#define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability +#define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability + +#define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status +#define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status +#define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable +#define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset +#define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State + +#define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID +#define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID + +// +// LPSS SPI Module +// Memory Space Registers +// +#define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters +#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update +#define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider +#define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider +#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable + +#define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset +#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset +#define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h new file mode 100644 index 0000000000..bb50709182 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h @@ -0,0 +1,89 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsPcie.h + + @brief + Register names for VLV PCI-E root port devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +--*/ +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +#define PCH_PCIE_MAX_ROOT_PORTS 4 + +/// +/// VLV PCI Express Root Ports (D28:F0~F3) +/// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 + +#define R_PCH_PCIE_ID 0x00 // Identifiers +#define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID +#define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1 +#define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2 +#define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3 +#define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4 +#define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID + + +#define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer +#define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer +#define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number +#define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number +#define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number +#define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer +#define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer + +#define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status +#define S_PCH_PCIE_SLCTL_SLSTS 4 +#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed +#define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State +#define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State +#define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed +#define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed +#define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected +#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable +#define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control +#define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable +#define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable +#define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable + +#define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs +#define S_PCH_PCIE_SVID 4 +#define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier +#define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h new file mode 100644 index 0000000000..29629890c0 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h @@ -0,0 +1,1205 @@ +/*++ + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchRegsPcu.h + +Abstract: + + Register names for VLV PCU device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +--*/ +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +// +// VLV PCU Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +// Silicon Steppings +typedef enum { + PchA0 = 0, + PchA1 = 1, + PchB0 = 2, + PchB1 = 3, + PchB2 = 4, + PchB3 = 5, + PchC0 = 6, + PchD0 = 7, + PchSteppingMax +} PCH_STEPPING; + +#define R_PCH_LPC_REG_ID 0x00 // Identifiers Register +#define B_PCH_LPC_DEVICE_ID 0xFFFF0000 // Device Identification +#define B_PCH_LPC_VENDOR_ID 0x0000FFFF // Vendor Identification +#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Vendor ID for Intel +// +// General VLV PCU Device ID +// +#define V_PCH_LPC_DEVICE_ID_0 0x0F1C +#define V_PCH_LPC_DEVICE_ID_1 0x0F1D +#define V_PCH_LPC_DEVICE_ID_2 0x0F1E +#define V_PCH_LPC_DEVICE_ID_3 0x0F1F + +#define R_PCH_LPC_COMMAND 0x04 // Command +#define B_PCH_LPC_COMMAND_ID BIT10 // Interrupt Disable +#define B_PCH_LPC_COMMAND_FBE BIT9 // Fast Back to Back Enable +#define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable +#define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control +#define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable +#define B_PCH_LPC_COMMAND_VPS BIT5 // VGA Palette Snoop +#define B_PCH_LPC_COMMAND_MWIE BIT4 // Memory Write and Invalidate Enable +#define B_PCH_LPC_COMMAND_SCE BIT3 // Special Cycle Enable +#define B_PCH_LPC_COMMAND_BME BIT2 // Bus Master Enable +#define B_PCH_LPC_COMMAND_MSE BIT1 // Memory Space Enable +#define B_PCH_LPC_COMMAND_IOSE BIT0 // I/O Space Enable + +#define R_PCH_LPC_DEV_STS 0x06 // Status +#define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error +#define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error +#define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort +#define B_PCH_LPC_DEV_STS_RTA BIT12 // Received Target Abort +#define B_PCH_LPC_DEV_STS_STA BIT11 // Signaled Target Abort +#define B_PCH_LPC_DEV_STS_DEVT_STS (BIT10 | BIT9) // DEVSEL# Timing Status +#define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error +#define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable +#define B_PCH_LPC_DEV_STS_66MHZ_CAP BIT5 // 66 MHz capable +#define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List +#define B_PCH_LPC_DEV_STS_INT_STS BIT3 // Interrupt Status + +#define R_PCH_LPC_RID_CC 0x08 // Revision ID & Class Code +#define B_PCH_LPC_RID_CC_BCC 0xFF000000 // Base Class Code +#define B_PCH_LPC_RID_CC_SCC 0x00FF0000 // Sub-Class Code +#define B_PCH_LPC_RID_CC_PI 0x0000FF00 // Programming Interface +#define B_PCH_LPC_RID_CC_RID 0x000000FF // Revision ID + +// Silicon Steppings + +#define V_PCH_LPC_RID_0 0x01 // A0 Stepping (17 x 17) +#define V_PCH_LPC_RID_1 0x02 // A0 Stepping (25 x 27) +#define V_PCH_LPC_RID_2 0x03 // A1 Stepping (17 x 17) +#define V_PCH_LPC_RID_3 0x04 // A1 Stepping (25 x 27) +#define V_PCH_LPC_RID_4 0x05 // B0 Stepping (17 x 17) +#define V_PCH_LPC_RID_5 0x06 // B0 Stepping (25 x 27) +#define V_PCH_LPC_RID_6 0x07 // B1 Stepping (17 x 17) +#define V_PCH_LPC_RID_7 0x08 // B1 Stepping (25 x 27) +#define V_PCH_LPC_RID_8 0x09 // B2 Stepping (17 x 17) +#define V_PCH_LPC_RID_9 0x0A // B2 Stepping (25 x 27) +#define V_PCH_LPC_RID_A 0x0B // B3 Stepping (17 x 17) +#define V_PCH_LPC_RID_B 0x0C // B3 Stepping (25 x 27) +#define V_PCH_LPC_RID_C 0x0D // C0 Stepping (17 x 17) +#define V_PCH_LPC_RID_D 0x0E // C0 Stepping (25 x 27) + +#define R_PCH_LPC_MLT 0x0D // Master Latency Timer +#define B_PCH_LPC_MLT_MLC 0xF8 // Master Latency Count + +#define R_PCH_LPC_HEADTYP 0x0E // Header Type +#define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device +#define B_PCH_LPC_HEADTYP_HT 0x7F // Header Type + +#define R_PCH_LPC_SS 0x2C // Subsystem ID & Vendor ID +#define B_PCH_LPC_SS_SSID 0xFFFF0000 // Subsystem ID +#define B_PCH_LPC_SS_SSVID 0x0000FFFF // Subsystem Vendor ID + +#define R_PCH_LPC_CAP_LIST 0x34 // Capability List +#define B_PCH_LPC_CAP_LIST_CP 0xFF // Capability Pointer + +#define R_PCH_LPC_ACPI_BASE 0x40 // ABASE, 16bit +#define B_PCH_LPC_ACPI_BASE_BAR 0x0000FF80 // Base Address, 128 Bytes +#define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_ACPI_BASE_MEMI BIT0 // Memory Space Indication + +#define R_PCH_LPC_PMC_BASE 0x44 // PBASE, 32bit, 512 Bytes +#define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00 // Base Address +#define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_PMC_BASE_MEMI BIT0 // Memory Space Indication + +#define R_PCH_LPC_GPIO_BASE 0x48 // GBASE, 16bit +#define B_PCH_LPC_GPIO_BASE_BAR 0xFF00 // Base Address, 256 Bytes +#define B_PCH_LPC_GPIO_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_GPIO_BASE_MEMI BIT0 // Memory Space Indication + +#define R_PCH_LPC_IO_BASE 0x4C // IOBASE, 32bit +#define B_PCH_LPC_IO_BASE_BAR 0xFFFFC000 // Base Address, 16 KiloBytes +#define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_IO_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_IO_BASE_MEMI BIT0 // Memory Space Indication + +#define R_PCH_LPC_ILB_BASE 0x50 // IBASE, 32bit +#define B_PCH_LPC_ILB_BASE_BAR 0xFFFFFE00 // Base Address, 512 bytes +#define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_ILB_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_ILB_BASE_MEMI BIT0 // Memory Space Indication + +#define R_PCH_LPC_SPI_BASE 0x54 // SBASE, 32bit +#define B_PCH_LPC_SPI_BASE_BAR 0xFFFFFE00 // Base Address, 512 bytes +#define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_SPI_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_SPI_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_SPI_BASE_MEMI BIT0 // Memory Space Indicator + +#define R_PCH_LPC_MPHY_BASE 0x58 // MPBASE, 32bit +#define B_PCH_LPC_MPHY_BASE_BAR 0xFFF00000 // Base Address, 1 MegaByte +#define B_PCH_LPC_MPHY_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_MPHY_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_MPHY_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_MPHY_BASE_MEMI BIT0 // Memory Space Indicator + +#define R_PCH_LPC_PUNIT_BASE 0x5C // PUBASE, 32bit +#define B_PCH_LPC_PUNIT_BASE_BAR 0xFFFFF800 // Base Address, 2K bytes +#define B_PCH_LPC_PUNIT_BASE_PREF BIT3 // Prefetchable +#define B_PCH_LPC_PUNIT_BASE_ADDRNG BIT2 // Address Range +#define B_PCH_LPC_PUNIT_BASE_EN BIT1 // Enable Bit +#define B_PCH_LPC_PUNIT_BASE_MEMI BIT0 // Memory Space Indicator + +#define R_PCH_LPC_UART_CTRL 0x80 // UART Control +#define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable + +#define R_PCH_LPC_FWH_BIOS_DEC 0xD8 // BIOS Decode Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EE0 BIT12 // E0-E8 Enable +#define B_PCH_LPC_FWH_BIOS_DEC_ED8 BIT11 // D8-DF Enable +#define B_PCH_LPC_FWH_BIOS_DEC_ED0 BIT10 // D0-D8 Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EC8 BIT9 // C8-CF Enable +#define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable +#define B_PCH_LPC_FWH_BIOS_DEC_LFE BIT7 // Legacy F Segment Enable +#define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable +#define B_PCH_LPC_FWH_BIOS_DEC_E70 BIT3 // 70-7F Enable +#define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable +#define B_PCH_LPC_FWH_BIOS_DEC_E50 BIT1 // 50-5F Enable +#define B_PCH_LPC_FWH_BIOS_DEC_E40 BIT0 // 40-4F Enable + +#define R_PCH_LPC_FDCAP 0xE0 // Feature Detection Capability ID +#define B_PCH_LPC_FDCAP_NEXT 0xFF00 // Next Capability +#define B_PCH_LPC_FDCAP_CAPID 0x00FF // Capability ID + +#define R_PCH_LPC_FDLEN 0xE2 // Feature Detection Capability Length +#define B_PCH_LPC_FDLEN_CAPLEN 0xFF // Capability Length + +#define R_PCH_LPC_FDVER 0xE3 // Feature Detection Capability Version +#define B_PCH_LPC_FDVER_VSCID 0xF0 // Vendor Specific Capability ID +#define B_PCH_LPC_FDVER_CAPVER 0x0F // Capability Version + +#define R_PCH_LPC_FVECTIDX 0xE4 // Feature Vector Index + +#define R_PCH_LPC_FVECTD 0xE8 // Feature Vector Data + +#define R_PCH_LPC_RCBA 0xF0 // RCBA, 32bit +#define B_PCH_LPC_RCBA_BAR 0xFFFFFC00 // Base Address, 1 KiloByte +#define B_PCH_LPC_RCBA_EN BIT0 // Enable Bit + +#define R_PCH_LPC_ULT_OBS 0xF4 // ULT Observability +#define B_PCH_LPC_ULT_OBS_WNUM 0x3FF000 // Reserved Wafer Number +#define B_PCH_LPC_ULT_OBS_XLOC 0xFC0 // Reserved X Loc +#define B_PCH_LPC_ULT_OBS_YLOC 0x3F // Reserved Y Loc + +#define R_PCH_LPC_MAN_ID 0xF8 // Manufacturer ID +#define B_PCH_LPC_MAN_ID_DPID 0xF000000 // Dot Portion of Process ID +#define B_PCH_LPC_MAN_ID_MSID 0xFF0000 // Manufacturing Stepping Identifier +#define B_PCH_LPC_MAN_ID_MID 0xFF00 // Manufacturing Identifier +#define B_PCH_LPC_MAN_ID_PPID 0xFF // Process Portion of Process ID + +#define R_PCH_LPC_CGC 0xFC // Clock Gating Control +#define B_PCH_LPC_CGC_SBLCG BIT9 // IOSF-SB Local Clock Gating Disable +#define B_PCH_LPC_CGC_SBTCG BIT8 // IOSF-SB Trunk Clock Gating (Request) Disable +#define B_PCH_LPC_CGC_PRILCG BIT1 // IOSF-PRI Local Clock Gating Disable +#define B_PCH_LPC_CGC_PRITCG BIT0 // IOSF-PRI Trunk Clock Gating (Request) Disable + +// +// iLB Memory Space Registers (IBASE) +// +#define R_PCH_ILB_ACPI_CNT 0x00 // ACPI Control +#define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_9 0 // IRQ9 +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_10 BIT0 // IRQ10 +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_11 BIT1 // IRQ11 +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20 BIT2 // IRQ20 (Only if APIC enabled) +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_21 (BIT2 | BIT0) // IRQ21 (Only if APIC enabled) +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_22 (BIT2 | BIT1) // IRQ22 (Only if APIC enabled) +#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled) + +#define R_PCH_ILB_MC 0x04 // Miscellaneous Control +#define B_PCH_ILB_MC_DRTC BIT3 // Disable RTC +#define B_PCH_ILB_MC_D8259 BIT2 // Disable 8259 +#define B_PCH_ILB_MC_D8254 BIT1 // Disable 8254 +#define B_PCH_ILB_MC_AME BIT0 // Alternate Access Mode Enable + +#define R_PCH_ILB_PIRQA_ROUT 0x08 // PIRQA Routing Control +#define R_PCH_ILB_PIRQB_ROUT 0x09 // PIRQB Routing Control +#define R_PCH_ILB_PIRQC_ROUT 0x0A // PIRQC Routing Control +#define R_PCH_ILB_PIRQD_ROUT 0x0B // PIRQD Routing Control +#define R_PCH_ILB_PIRQE_ROUT 0x0C // PIRQE Routing Control +#define R_PCH_ILB_PIRQF_ROUT 0x0D // PIRQF Routing Control +#define R_PCH_ILB_PIRQG_ROUT 0x0E // PIRQG Routing Control +#define R_PCH_ILB_PIRQH_ROUT 0x0F // PIRQH Routing Control +// +// Bit values are the same for R_PCH_ILB_PIRQA_ROUT to R_PCH_ILB_PIRQH_ROUT +// +#define B_PCH_ILB_PIRQX_ROUT_IRQEN BIT7 // Interrupt Routing Enable +#define B_PCH_ILB_PIRQX_ROUT 0x0F // IRQ Routing +#define V_PCH_ILB_PIRQX_ROUT_IRQ_3 0x03 // Route to IRQ3 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_4 0x04 // Route to IRQ4 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_5 0x05 // Route to IRQ5 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_6 0x06 // Route to IRQ6 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_7 0x07 // Route to IRQ7 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_9 0x09 // Route to IRQ9 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_10 0x0A // Route to IRQ10 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_11 0x0B // Route to IRQ11 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_12 0x0C // Route to IRQ12 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_14 0x0E // Route to IRQ14 +#define V_PCH_ILB_PIRQX_ROUT_IRQ_15 0x0F // Route to IRQ15 + +#define R_PCH_ILB_SERIRQ_CNT 0x10 // Serial IRQ Control +#define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode + +#define R_PCH_ILB_ULKMC 0x14 // USB Legacy Keyboard / Mouse Control +#define B_PCH_ILB_ULKMC_TRAPBY64W BIT11 // SMI Caused by Port 64 Write +#define B_PCH_ILB_ULKMC_TRAPBY64R BIT10 // SMI Caused by Port 64 Read +#define B_PCH_ILB_ULKMC_TRAPBY60W BIT9 // SMI Caused by Port 60 Write +#define B_PCH_ILB_ULKMC_TRAPBY60R BIT8 // SMI Caused by Port 60 Read +#define B_PCH_ILB_ULKMC_64WEN BIT3 // SMI on Port 64 Writes Enable +#define B_PCH_ILB_ULKMC_64REN BIT2 // SMI on Port 64 Reads Enable +#define B_PCH_ILB_ULKMC_60WEN BIT1 // SMI on Port 60 Writes Enable +#define B_PCH_ILB_ULKMC_60REN BIT0 // SMI on Port 60 Reads Enable + +#define R_PCH_ILB_FWH_BIOS_SEL 0x18 // FWH ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_F8 0xF0000000 // F8-FF ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_F0 0x0F000000 // F0-F7 ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_E8 0x00F00000 // E8-EF ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_E0 0x000F0000 // E0-E7 ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_D8 0x0000F000 // D8-DF ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_D0 0x00000F00 // D0-D7 ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_C8 0x000000F0 // C8-CF ID Select +#define B_PCH_ILB_FWH_BIOS_SEL_C0 0x0000000F // C0-C7 ID Select + +#define R_PCH_ILB_BIOS_CNTL 0x1C // BIOS Control +#define S_PCH_ILB_BIOS_CNTL 4 +#define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable +#define B_PCH_ILB_BIOS_CNTL_LE BIT1 // Lock Enable +#define N_PCH_ILB_BIOS_CNTL_LE 1 +#define B_PCH_ILB_BIOS_CNTL_WP BIT0 // Write Protect + +#define R_PCH_ILB_D0IR 0x20 // Device 0 Interrupt Route +#define R_PCH_ILB_D1IR 0x22 // Device 1 Interrupt Route +#define R_PCH_ILB_D2IR 0x24 // Device 2 Interrupt Route +#define R_PCH_ILB_D3IR 0x26 // Device 3 Interrupt Route +#define R_PCH_ILB_D4IR 0x28 // Device 4 Interrupt Route +#define R_PCH_ILB_D5IR 0x2A // Device 5 Interrupt Route +#define R_PCH_ILB_D6IR 0x2C // Device 6 Interrupt Route +#define R_PCH_ILB_D7IR 0x2E // Device 7 Interrupt Route +#define R_PCH_ILB_D8IR 0x30 // Device 8 Interrupt Route +#define R_PCH_ILB_D9IR 0x32 // Device 9 Interrupt Route +#define R_PCH_ILB_D10IR 0x34 // Device 10 Interrupt Route +#define R_PCH_ILB_D11IR 0x36 // Device 11 Interrupt Route +#define R_PCH_ILB_D12IR 0x38 // Device 12 Interrupt Route +#define R_PCH_ILB_D13IR 0x3A // Device 13 Interrupt Route +#define R_PCH_ILB_D14IR 0x3C // Device 14 Interrupt Route +#define R_PCH_ILB_D15IR 0x3E // Device 15 Interrupt Route +#define R_PCH_ILB_D16IR 0x40 // Device 16 Interrupt Route +#define R_PCH_ILB_D17IR 0x42 // Device 17 Interrupt Route +#define R_PCH_ILB_D18IR 0x44 // Device 18 Interrupt Route +#define R_PCH_ILB_D19IR 0x46 // Device 19 Interrupt Route +#define R_PCH_ILB_D20IR 0x48 // Device 20 Interrupt Route +#define R_PCH_ILB_D21IR 0x4A // Device 21 Interrupt Route +#define R_PCH_ILB_D22IR 0x4C // Device 22 Interrupt Route +#define R_PCH_ILB_D23IR 0x4E // Device 23 Interrupt Route +#define R_PCH_ILB_D24IR 0x50 // Device 24 Interrupt Route +#define R_PCH_ILB_D25IR 0x52 // Device 25 Interrupt Route +#define R_PCH_ILB_D26IR 0x54 // Device 26 Interrupt Route +#define R_PCH_ILB_D27IR 0x56 // Device 27 Interrupt Route +#define R_PCH_ILB_D28IR 0x58 // Device 28 Interrupt Route +#define R_PCH_ILB_D29IR 0x5A // Device 29 Interrupt Route +#define R_PCH_ILB_D30IR 0x5C // Device 30 Interrupt Route +#define R_PCH_ILB_D31IR 0x5E // Device 31 Interrupt Route + +#define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) // INTD Mask +#define V_PCH_ILB_DXXIR_IDR_PIRQA 0 // INTD Mapping to IRQ A +#define V_PCH_ILB_DXXIR_IDR_PIRQB BIT12 // INTD Mapping to IRQ B +#define V_PCH_ILB_DXXIR_IDR_PIRQC BIT13 // INTD Mapping to IRQ C +#define V_PCH_ILB_DXXIR_IDR_PIRQD (BIT13 | BIT12) // INTD Mapping to IRQ D +#define V_PCH_ILB_DXXIR_IDR_PIRQE BIT14 // INTD Mapping to IRQ E +#define V_PCH_ILB_DXXIR_IDR_PIRQF (BIT14 | BIT12) // INTD Mapping to IRQ F +#define V_PCH_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) // INTD Mapping to IRQ G +#define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H + +#define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) // INTC Mask +#define V_PCH_ILB_DXXIR_ICR_PIRQA 0 // INTC Mapping to IRQ A +#define V_PCH_ILB_DXXIR_ICR_PIRQB BIT8 // INTC Mapping to IRQ B +#define V_PCH_ILB_DXXIR_ICR_PIRQC BIT9 // INTC Mapping to IRQ C +#define V_PCH_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) // INTC Mapping to IRQ D +#define V_PCH_ILB_DXXIR_ICR_PIRQE BIT10 // INTC Mapping to IRQ E +#define V_PCH_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) // INTC Mapping to IRQ F +#define V_PCH_ILB_DXXIR_ICR_PIRQG (BIT10 | BIT9) // INTC Mapping to IRQ G +#define V_PCH_ILB_DXXIR_ICR_PIRQH (BIT10 | BIT9 | BIT8) // INTC Mapping to IRQ H + +#define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask +#define V_PCH_ILB_DXXIR_IBR_PIRQA 0 // INTB Mapping to IRQ A +#define V_PCH_ILB_DXXIR_IBR_PIRQB BIT4 // INTB Mapping to IRQ B +#define V_PCH_ILB_DXXIR_IBR_PIRQC BIT5 // INTB Mapping to IRQ C +#define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) // INTB Mapping to IRQ D +#define V_PCH_ILB_DXXIR_IBR_PIRQE BIT6 // INTB Mapping to IRQ E +#define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F +#define V_PCH_ILB_DXXIR_IBR_PIRQG (BIT6 | BIT5) // INTB Mapping to IRQ G +#define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H + +#define B_PCH_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) // INTA Mask +#define V_PCH_ILB_DXXIR_IAR_PIRQA 0 // INTA Mapping to IRQ A +#define V_PCH_ILB_DXXIR_IAR_PIRQB BIT0 // INTA Mapping to IRQ B +#define V_PCH_ILB_DXXIR_IAR_PIRQC BIT1 // INTA Mapping to IRQ C +#define V_PCH_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) // INTA Mapping to IRQ D +#define V_PCH_ILB_DXXIR_IAR_PIRQE BIT2 // INTA Mapping to IRQ E +#define V_PCH_ILB_DXXIR_IAR_PIRQF (BIT2 | BIT0) // INTA Mapping to IRQ F +#define V_PCH_ILB_DXXIR_IAR_PIRQG (BIT2 | BIT1) // INTA Mapping to IRQ G +#define V_PCH_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H + +#define R_PCH_ILB_OIC 0x60 // Other Interrupt Controller +#define B_PCH_ILB_OIC_SIRQEN BIT12 // Serial IRQ Enable +#define B_PCH_ILB_OIC_AEN BIT8 // APIC Enable + +#define R_PCH_ILB_RTC_CONF 0x64 // RTC Control +#define B_PCH_ILB_RTC_CONF_UCMOS_LOCK BIT1 // Upper 128 Byte Lock +#define B_PCH_ILB_RTC_CONF_LCMOS_LOCK BIT0 // Lower 128 Byte Lock + +#define R_PCH_ILB_RTM 0x68 // RTC Test Mode +#define B_PCH_ILB_RTM_RTM1 (BIT2 | BIT1 | BIT0) + +#define R_PCH_ILB_BCS 0x6C // BIOS Control Status +#define B_PCH_ILB_BCS_SMIWPEN BIT1 // SMI WPD Enable +#define B_PCH_ILB_BCS_SMIWPST BIT0 // SMI WPD Status + +#define R_PCH_ILB_LE 0x70 // LE +#define B_PCH_ILB_LE_IRQ12C BIT1 // IRQ12 Cause +#define B_PCH_ILB_LE_IRQ1C BIT0 // IRQ1 Cause + +#define R_PCH_ILB_RTCC 0x74 // RTC HIP Configuration +#define B_PCH_ILB_RTCC_RTCB4 BIT6 // RTC Bias Resistor 4, Adds 480 Kohm +#define B_PCH_ILB_RTCC_RTCB3 BIT5 // RTC Bias Resistor 3, Adds 240 Kohm +#define B_PCH_ILB_RTCC_RTCB2 BIT4 // RTC Bias Resistor 2, Adds 120 Kohm +#define B_PCH_ILB_RTCC_RTCB1 BIT3 // RTC Bias Resistor 1, Adds 60 Kohm +#define B_PCH_ILB_RTCC_RTCB0 BIT2 // RTC Bias Resistor 0, Adds 30 Kohm +#define B_PCH_ILB_RTCC_DSWEN BIT1 // Deep Sleep Well Enable +#define B_PCH_ILB_RTCC_FEN BIT0 // Enable the Fast Oscillator Bypass Mode + +#define R_PCH_ILB_DEF0 0x78 // Defeature Register 0 +#define B_PCH_ILB_DEF0_SHRTSYNC BIT22 // Short Sync Abort Defeature +#define B_PCH_ILB_DEF0_SDD BIT21 // Sub Decode Disable + +#define R_PCH_ILB_DEF1 0x7C // Defeature Register 1 +#define B_PCH_ILB_DEF1_TPMPF BIT10 // usb2leg_chknbit_TPM_PF +#define B_PCH_ILB_DEF1_HPETDEF BIT8 // usb2leg_chknbit_hpet +#define B_PCH_ILB_DEF1_ECWS BIT6 // 8254 Early CW Select +#define B_PCH_ILB_DEF1_FOF BIT5 // 8254 Freeze on first on 1st rd wr11 +#define B_PCH_ILB_DEF1_FOAR BIT4 // 8254 Freeze_On_AnyRead +#define B_PCH_ILB_DEF1_LMOO BIT3 // 8259 L2L0_Match_On_OCW2 +#define B_PCH_ILB_DEF1_DFP BIT2 // 8259 Disable_Freeze_Priority +#define B_PCH_ILB_DEF1_EETI BIT1 // 8259 Extend_EdgeTrig_IRQ +#define B_PCH_ILB_DEF1_DSAEOI BIT0 // 8259 Disable_Slave_AEOI + +#define R_PCH_ILB_GNMI 0x80 // NMI Register +#define S_PCH_ILB_GNMI 4 +#define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable +#define N_PCH_ILB_GNMI_NMI2SMIEN 6 +#define B_PCH_ILB_GNMI_NMI2SMIST BIT5 // NMI to SMI Status +#define N_PCH_ILB_GNMI_NMI2SMIST 5 +#define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW +#define B_PCH_ILB_GNMI_NMINS BIT3 // NMI NOW Status +#define B_PCH_ILB_GNMI_GNMIED BIT2 // GPIO NMI Edge Detection +#define B_PCH_ILB_GNMI_GNMIE BIT1 // GPIO NMI Enable +#define B_PCH_ILB_GNMI_GNMIS BIT0 // GPIO NMI Status + +#define R_PCH_ILB_LPCC 0x84 // LPC Control +#define B_PCH_ILB_LPCC_LPCCLK_SLC BIT8 // iLPCCLK Mux Select +#define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3 +#define B_PCH_ILB_LPCC_CLKRUN_EN BIT2 // LPC CLKRUN Protocol Enable +#define B_PCH_ILB_LPCC_LPCCLK1EN BIT1 // Clock 1 Enable +#define B_PCH_ILB_LPCC_LPCCLK0EN BIT0 // Clock 0 Enable + +#define R_PCH_ILB_IRQE 0x88 // IRQ Enable Control +#define B_PCH_ILB_IRQE_IRQ4TO7EN (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable +#define B_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable + +// +// ACPI and Legacy I/O Registers (ABASE) +// +#define R_PCH_ACPI_PM1_STS 0x00 // Power Management 1 Status +#define S_PCH_ACPI_PM1_STS 2 +#define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status +#define B_PCH_ACPI_PM1_STS_WAK_PCIE0 BIT14 // PCI Express 0 Wake Status +#define B_PCH_ACPI_PM1_STS_USB_CLKLESS BIT13 // USB Clockless Status +#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 // Power Button Override Status +#define B_PCH_ACPI_PM1_STS_RTC BIT10 // RTC Status +#define B_PCH_ACPI_PM1_STS_PWRBTN BIT8 // Power Button Status +#define B_PCH_ACPI_PM1_STS_GBL BIT5 // Global Status +#define B_PCH_ACPI_PM1_STS_WAK_PCIE3 BIT4 // PCI Express 3 Wake Status +#define B_PCH_ACPI_PM1_STS_WAK_PCIE2 BIT3 // PCI Express 2 Wake Status +#define B_PCH_ACPI_PM1_STS_WAK_PCIE1 BIT2 // PCI Express 1 Wake Status +#define B_PCH_ACPI_PM1_STS_TMROF BIT0 // Timer Overflow Status +#define N_PCH_ACPI_PM1_STS_WAK 15 +#define N_PCH_ACPI_PM1_STS_PRBTNOR 11 +#define N_PCH_ACPI_PM1_STS_RTC 10 +#define N_PCH_ACPI_PM1_STS_PWRBTN 8 +#define N_PCH_ACPI_PM1_STS_GBL 5 +#define N_PCH_ACPI_PM1_STS_TMROF 0 + +#define R_PCH_ACPI_PM1_EN 0x02 // Power Management 1 Enables +#define S_PCH_ACPI_PM1_EN 2 +#define B_PCH_ACPI_PM1_WAK_DIS_PCIE0 BIT14 // PCI Express 0 Disable +#define B_PCH_ACPI_PM1_EN_USB_CLKLESS BIT13 // USB Clockless Enable Bit +#define B_PCH_ACPI_PM1_EN_RTC BIT10 // RTC Alarm Enable Bit +#define B_PCH_ACPI_PM1_EN_PWRBTN BIT8 // Power Button Enable Bit +#define B_PCH_ACPI_PM1_EN_GBL BIT5 // Global Enable Bit +#define B_PCH_ACPI_PM1_WAK_DIS_PCIE3 BIT4 // PCI Express 3 Disable +#define B_PCH_ACPI_PM1_WAK_DIS_PCIE2 BIT3 // PCI Express 2 Disable +#define B_PCH_ACPI_PM1_WAK_DIS_PCIE1 BIT2 // PCI Express 1 Disable +#define B_PCH_ACPI_PM1_EN_TMROF BIT0 // Timer Overflow Interrupt Enable Bit +#define N_PCH_ACPI_PM1_EN_RTC 10 +#define N_PCH_ACPI_PM1_EN_PWRBTN 8 +#define N_PCH_ACPI_PM1_EN_GBL 5 +#define N_PCH_ACPI_PM1_EN_TMROF 0 + +#define R_PCH_ACPI_PM1_CNT 0x04 // Power Management 1 Control +#define S_PCH_ACPI_PM1_CNT 4 +#define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable +#define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) // Sleep Type +#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 // ON (S0) +#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 // Puts CPU in S1 state (S1) +#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 // Suspend-to-RAM (S3) +#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 // Suspend-to-Disk (S4) +#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 // Soft Off (S5) +#define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 +#define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1 // Treated as Scratchpad Bit +#define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0 // SCI Enable + +#define R_PCH_ACPI_PM1_TMR 0x08 // Power Management 1 Timer +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF // The timer value mask +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 // The timer is 24 bit overflow +#define V_PCH_ACPI_PM1_TMR_FREQUENCY 3579545 // Timer Frequency +#define V_PCH_ACPI_PM1_TMR_NUM_BITS 24 // Programmed to 24 not 32 +#define V_PCH_ACPI_PM1_TMR_MAX_BITS 32 + +#define R_PCH_ACPI_GPE0a_STS 0x20 // General Purpose Event 0a Status +#define S_PCH_ACPI_GPE0a_STS 4 +#define B_PCH_ACPI_GPE0a_STS_CORE_GPIO 0xFF000000 // CORE GPIO Status +#define B_PCH_ACPI_GPE0a_STS_SUS_GPIO 0x00FF0000 // SUS GPIO Status +#define B_PCH_ACPI_GPE0a_STS_PME_B0 BIT13 // Power Management Event Bus 0 Status +#define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 // Battery Low Status +#define B_PCH_ACPI_GPE0a_STS_PCI_EXP BIT9 // PCI Express Status +#define B_PCH_ACPI_GPE0a_STS_GUNIT_SCI BIT5 // GUNIT SCI Status +#define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status +#define B_PCH_ACPI_GPE0a_STS_SWGPE BIT2 // Software GPE Status +#define B_PCH_ACPI_GPE0a_STS_HOT_PLUG BIT1 // Hot Plug Status +#define N_PCH_ACPI_GPE0a_STS_PME_B0 13 +#define N_PCH_ACPI_GPE0a_STS_BATLOW 10 +#define N_PCH_ACPI_GPE0a_STS_PCI_EXP 9 +#define N_PCH_ACPI_GPE0a_STS_GUNIT_SCI 5 +#define N_PCH_ACPI_GPE0a_STS_PUNIT_SCI 4 +#define N_PCH_ACPI_GPE0a_STS_SWGPE 2 +#define N_PCH_ACPI_GPE0a_STS_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0a_EN 0x28 // General Purpose Event 0a Enables +#define S_PCH_ACPI_GPE0a_EN 4 +#define B_PCH_ACPI_GPE0a_EN_CORE_GPIO 0xFF000000 // CORE GPIO Enable +#define B_PCH_ACPI_GPE0a_EN_SUS_GPIO 0x00FF0000 // SUS GPIO Enable +#define B_PCH_ACPI_GPE0a_EN_PME_B0 BIT13 // Power Management Event Bus 0 Enable +#define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 // Battery Low Enable +#define B_PCH_ACPI_GPE0a_EN_PCI_EXP BIT9 // PCI Express Enable +#define B_PCH_ACPI_GPE0a_EN_SWGPE BIT2 // Software GPE Enable +#define B_PCH_ACPI_GPE0a_EN_HOT_PLUG BIT1 // Hot Plug Enable +#define N_PCH_ACPI_GPE0a_EN_PME_B0 13 +#define N_PCH_ACPI_GPE0a_EN_BATLOW 10 +#define N_PCH_ACPI_GPE0a_EN_PCI_EXP 9 +#define N_PCH_ACPI_GPE0a_EN_SWGPE 2 +#define N_PCH_ACPI_GPE0a_EN_HOT_PLUG 1 + +#define R_PCH_SMI_EN 0x30 // SMI Control and Enable +#define S_PCH_SMI_EN 4 +#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 // Legacy USB 3 Enable +#define B_PCH_SMI_EN_INTEL_USB2 BIT18 // Intel USB 2 Enable +#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 // Legacy USB 2 Enable +#define B_PCH_SMI_EN_PERIODIC BIT14 // Periodic Enable +#define B_PCH_SMI_EN_TCO BIT13 // TCO Enable +#define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS +#define B_PCH_SMI_EN_SWSMI_TMR BIT6 // Software SMI Timer Enable +#define B_PCH_SMI_EN_APMC BIT5 // APMC Enable +#define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable +#define B_PCH_SMI_EN_BIOS BIT2 // BIOS Enable +#define B_PCH_SMI_EN_EOS BIT1 // End of SMI +#define B_PCH_SMI_EN_GBL_SMI BIT0 // Global SMI Enable +#define N_PCH_SMI_EN_LEGACY_USB3 31 +#define N_PCH_SMI_EN_GPIO_UNLOCK 27 +#define N_PCH_SMI_EN_INTEL_USB2 18 +#define N_PCH_SMI_EN_LEGACY_USB2 17 +#define N_PCH_SMI_EN_PERIODIC 14 +#define N_PCH_SMI_EN_TCO 13 +#define N_PCH_SMI_EN_BIOS_RLS 7 +#define N_PCH_SMI_EN_SWSMI_TMR 6 +#define N_PCH_SMI_EN_APMC 5 +#define N_PCH_SMI_EN_ON_SLP_EN 4 +#define N_PCH_SMI_EN_BIOS 2 +#define N_PCH_SMI_EN_EOS 1 +#define N_PCH_SMI_EN_GBL_SMI 0 + +#define R_PCH_SMI_STS 0x34 // SMI Status Register +#define S_PCH_SMI_STS 4 +#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 // Legacy USB 3 Status +#define B_PCH_SMI_STS_GUNIT_SMI BIT29 // GUNIT SMI Status +#define B_PCH_SMI_STS_PUNIT_SMI BIT28 // PUNIT SMI Status +#define B_PCH_SMI_STS_SPI BIT26 // SPI SMI Status +#define B_PCH_SMI_STS_PCI_EXP BIT20 // PCI Express SMI Status +#define B_PCH_SMI_STS_INTEL_USB2 BIT18 // Intel USB 2 Status +#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 // Legacy USB 2 Status +#define N_PCH_SMI_STS_TCO 13 +#define B_PCH_SMI_STS_SMBUS BIT16 // SMBUS SMI Status +#define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status +#define B_PCH_SMI_STS_PERIODIC BIT14 // Periodic Status +#define B_PCH_SMI_STS_TCO BIT13 // TCO Status +#define B_PCH_SMI_STS_GPE0 BIT9 // GPE0 Status +#define B_PCH_SMI_STS_PM1_STS_REG BIT8 // PM1 Status Register +#define B_PCH_SMI_STS_SWSMI_TMR BIT6 // Software SMI Timer Status +#define B_PCH_SMI_STS_APM BIT5 // APM Status +#define B_PCH_SMI_STS_ON_SLP_EN BIT4 // SMI On Sleep Enable Status +#define B_PCH_SMI_STS_BIOS BIT2 // BIOS Status +#define N_PCH_SMI_STS_LEGACY_USB3 31 +#define N_PCH_SMI_STS_SPI 26 +#define N_PCH_SMI_STS_PCI_EXP 20 +#define N_PCH_SMI_STS_INTEL_USB2 18 +#define N_PCH_SMI_STS_LEGACY_USB2 17 +#define N_PCH_SMI_STS_SMBUS 16 +#define N_PCH_SMI_STS_ILB 15 +#define N_PCH_SMI_STS_PERIODIC 14 +#define N_PCH_SMI_STS_TCO 13 +#define N_PCH_SMI_STS_GPE0 9 +#define N_PCH_SMI_STS_PM1_STS_REG 8 +#define N_PCH_SMI_STS_SWSMI_TMR 6 +#define N_PCH_SMI_STS_APM 5 +#define N_PCH_SMI_STS_ON_SLP_EN 4 +#define N_PCH_SMI_STS_BIOS 2 + +#define R_PCH_ALT_GP_SMI_EN 0x38 // Alternate GPI SMI Enable +#define S_PCH_ALT_GP_SMI_EN 2 +#define B_PCH_ALT_GP_SMI_EN_CORE_GPIO 0xFF00 // SUS GPIO SMI Enable +#define B_PCH_ALT_GP_SMI_EN_SUS_GPIO 0x00FF // CORE GPIO SMI Enable + +#define R_PCH_ALT_GP_SMI_STS 0x3A // Alternate GPI SMI Status +#define S_PCH_ALT_GP_SMI_STS 2 +#define B_PCH_ALT_GP_SMI_STS_CORE_GPIO 0xFF00 // SUS GPIO SMI Status +#define B_PCH_ALT_GP_SMI_STS_SUS_GPIO 0x00FF // CORE GPIO SMI Status + +#define R_PCH_UPRWC 0x3C // USB Per-Port Registers Write Control +#define S_PCH_UPRWC 2 +#define B_PCH_UPRWC_WR_EN_SMI_STS BIT8 // Write Enable Status +#define B_PCH_UPRWC_WR_EN BIT1 // USB Per-Port Registers Write Enable +#define B_PCH_UPRWC_WR_EN_SMI_EN BIT0 // Write Enable SMI Enable + +#define R_PCH_ACPI_GPE_CNTL 0x40 // General Purpose Event Control +#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 // Software GPE Control +#define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3 +#define B_PCH_ACPI_GPE_CNTL_PCIE2_SCI_EN BIT2 +#define B_PCH_ACPI_GPE_CNTL_PCIE1_SCI_EN BIT1 +#define B_PCH_ACPI_GPE_CNTL_PCIE0_SCI_EN BIT0 + +#define R_PCH_ACPI_PM2_CNT 0x50 // PM2a Control Block +#define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0 // Scratchpad Bit + +#define R_PCH_TCO_RLD 0x60 // TCO Reload +#define B_PCH_TCO_RLD_VAL 0x3FF // TCO Timer Count Value + +#define R_PCH_TCO_STS 0x64 // TCO Timer Status +#define S_PCH_TCO_STS 4 +#define B_PCH_TCO_STS_SECOND_TO BIT17 // Second Timeout Status +#define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout +#define N_PCH_TCO_STS_TIMEOUT 3 + +#define R_PCH_TCO_CNT 0x68 // TCO Control +#define S_PCH_TCO_CNT 2 +#define B_PCH_TCO_CNT_OS_POLICY (BIT21 | BIT20) // OS Policy +#define B_PCH_TCO_CNT_LOCK BIT12 // TCO Enable Lock +#define B_PCH_TCO_CNT_TMR_HLT BIT11 // TCO Timer Halt + +#define R_PCH_TCO_TMR 0x70 // TCO Timer +#define B_PCH_TCO_TMR_TCO_TRLD 0x3FF0000 + +// +// PMC Memory Space Registers (PBASE) +// +#define R_PCH_PMC_PRSTS 0x00 // Power and Reset Status +#define B_PCH_PMC_PRSTS_PRODID 0xFF000000 // Power Management Controller Product ID +#define B_PCH_PMC_PRSTS_REVID 0x00FF0000 // Power Management Controller Revision ID +#define B_PCH_PMC_PRSTS_PM_WD_TMR BIT15 // PMC Watchdog Timer Status +#define B_PCH_PMC_PRSTS_CODE_COPIED_STS BIT11 // Patch Copied Over Status +#define B_PCH_PMC_PRSTS_CODE_LOAD_TO BIT9 // Patch Load Timeout Status +#define B_PCH_PMC_PRSTS_OP_STS BIT8 // PMC Operational Status +#define B_PCH_PMC_PRSTS_SEC_GBLRST_STS BIT7 // SEC Global Reset Status +#define B_PCH_PMC_PRSTS_SEC_WD_TMR_STS BIT6 // SEC Watchdog Timer Status +#define B_PCH_PMC_PRSTS_WOL_OVR_WK_STS BIT5 // Wake On LAN Override Wake Status +#define B_PCH_PMC_PRSTS_HOST_WAKE_STS BIT4 // PMC Host Wake Status + +#define R_PCH_PMC_PM_CFG 0x08 // Power Management Configuration +#define B_PCH_PMC_PM_CFG_SPS BIT5 // Shutdown Policy Select +#define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap +#define B_PCH_PMC_PM_CFG_SX_ENT_TO_EN BIT3 // S1 / 3 / 4 / 5 Entry Timeout Enable +#define B_PCH_PMC_PM_CFG_TIMING_T581 (BIT1 | BIT0) // Timing t581 + +#define R_PCH_PMC_PM_STS 0x0C // Power Management Status +#define B_PCH_PMC_PM_STS_PMC_MSG_FULL BIT24 // PMC Message Full Status +#define B_PCH_PMC_PM_STS_PMC_MSG_4_FULL BIT23 // PMC 4 Message Full Status +#define B_PCH_PMC_PM_STS_PMC_MSG_3_FULL BIT22 // PMC 3 Message Full Status +#define B_PCH_PMC_PM_STS_PMC_MSG_2_FULL BIT21 // PMC 2 Message Full Status +#define B_PCH_PMC_PM_STS_PMC_MSG_1_FULL BIT20 // PMC 1 Message Full Status +#define B_PCH_PMC_PM_STS_CODE_REQ BIT8 // Patch Request Status +#define B_PCH_PMC_PM_STS_HPR_ENT_TO BIT2 // Host partition Reset Entry Timeout Status +#define B_PCH_PMC_PM_STS_SX_ENT_TO BIT1 // S3 / 4 / 5 Entry Timeout Status + +#define R_PCH_PMC_MTPMC 0x10 // Message to PMC + +#define R_PCH_PMC_GEN_PMCON_1 0x20 // General PM Configuration 1 +#define B_PCH_PMC_GEN_PMCON_UART_EN BIT24 // UART Debug Port Enable +#define B_PCH_PMC_GEN_PMCON_DRAM_INIT BIT23 // DRAM Initialization Scratchpad Bit +#define B_PCH_PMC_GEN_PMCON_MEM_SR BIT21 // Memory Placed in Self-Refresh +#define B_PCH_PMC_GEN_PMCON_SRS BIT20 // System Reset Status +#define B_PCH_PMC_GEN_PMCON_CTS BIT19 // CPU Thermal Trip Status +#define B_PCH_PMC_GEN_PMCON_MIN_SLP_S4 BIT18 // Minimum SLP_S4# Assertion Width Violation Status +#define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure +#define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable +#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure +#define B_PCH_PMC_GEN_PMCON_WOL_ENABLE_OVERRIDE BIT13 // WOL Enable Override +#define B_PCH_PMC_GEN_PMCON_DISABLE_SX_STRETCH BIT12 // Disable SLP_X Scretching After SUS Well Power Up +#define B_PCH_PMC_GEN_PMCON_SLP_S3_MAW (BIT11 | BIT10) // SLP_S3# Minimum Assertion Width +#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_60US 0x000 // 60 micro seconds +#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_1MS 0x400 // 1 milli second +#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_50MS 0x800 // 50 milli seconds +#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_2S 0xC00 // 2 seconds +#define B_PCH_PMC_GEN_PMCON_GEN_RST_STS BIT9 // General Reset Status +#define B_PCH_PMC_GEN_PMCON_RTC_RESERVED BIT8 // RTC Reserved +#define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) // SWSMI Rate Select +#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_64MS 0xC0 // 64ms +/- 4ms +#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_32MS 0x80 // 32ms +/- 4ms +#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_16MS 0x40 // 16ms +/- 4ms +#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_1_5MS 0x00 // 1.5ms +/- 0.6ms +#define B_PCH_PMC_GEN_PMCON_SLP_S4_MAW (BIT5 | BIT4) // SLP_S4# Minimum Assertion Width +#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_1S 0x30 // 1 second +#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_2S 0x20 // 2 seconds +#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_3S 0x10 // 3 seconds +#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S 0x00 // 4 seconds +#define B_PCH_PMC_GEN_PMCON_SLP_S4_ASE BIT3 // SLP_S4# Assertion Scretch Enable +#define B_PCH_PMC_GEN_PMCON_RTC_PWR_STS BIT2 // RTC Power Status +#define B_PCH_PMC_GEN_PMCON_AFTERG3_EN BIT0 // After G3 State Enable + +#define R_PCH_PMC_GEN_PMCON_2 0x24 // General PM Configuration 2 +#define B_PCH_PMC_GEN_PMCON_LOCK_S4_STRET_LD BIT18 // SLP_S3 / SLP_S4 Stretching Policy Lock-Down +#define B_PCH_PMC_GEN_PMCON_BIOS_PCI_EXP_EN BIT10 // BIOS PCI Express Enable +#define B_PCH_PMC_GEN_PMCON_PWRBTN_LVL BIT9 // Power Button Level +#define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock +#define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) // Period SMI Select +#define V_PCH_PMC_GEN_PMCON_PER_SMI_64S 0x0000 // 64 seconds +#define V_PCH_PMC_GEN_PMCON_PER_SMI_32S 0x0001 // 32 seconds +#define V_PCH_PMC_GEN_PMCON_PER_SMI_16S 0x0002 // 16 seconds +#define V_PCH_PMC_GEN_PMCON_PER_SMI_8S 0x0003 // 8 seconds + +#define R_PCH_PMC_MFPMC 0x28 // Message from PMC + +#define R_PCH_PMC_SEC_STS 0x2C // SEC Status +#define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause + +#define R_PCH_PMC_CRID 0x30 // Configured Revision ID +#define B_PCH_PMC_CRID_RID_SEL (BIT1 | BIT0) // Revision ID Select + +#define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7 BIT31 // LPSS2 I2C #7 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6 BIT30 // LPSS2 I2C #6 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5 BIT29 // LPSS2 I2C #5 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4 BIT28 // LPSS2 I2C #4 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3 BIT27 // LPSS2 I2C #3 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2 BIT26 // LPSS2 I2C #2 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1 BIT25 // LPSS2 I2C #1 +#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC0 BIT24 // LPSS2 DMA Disable +#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC3 BIT23 // PCI Express Function 3 Disable +#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC2 BIT22 // PCI Express Function 2 Disable +#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC1 BIT21 // PCI Express Function 1 Disable +#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 BIT20 // PCI Express Function 0 Disable +#define N_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 20 +#define B_PCH_PMC_FUNC_DIS_SEC BIT19 // SEC Disable +#define B_PCH_PMC_FUNC_DIS_USB BIT18 // USB Disable +#define B_PCH_PMC_FUNC_DIS_SATA BIT17 // SATA Disable +#define B_PCH_PMC_FUNC_DIS_USH BIT15 // USH (USB3) Disable +#define B_PCH_PMC_FUNC_DIS_OTG BIT14 // USB OTG Disable +#define B_PCH_PMC_FUNC_DIS_LPE BIT13 // LPE Disable +#define B_PCH_PMC_FUNC_DIS_AZALIA BIT12 // Azalia Disable +#define B_PCH_PMC_FUNC_DIS_MIPI BIT11 // MIPI-HSI Disable +#define B_PCH_PMC_FUNC_DIS_SDIO4 BIT11 // SCC SDIO #4 (Device 23, eMMC4.5) Disable +#define B_PCH_PMC_FUNC_DIS_SDIO3 BIT10 // SCC SDIO #3 (Device 18, SD Card) Disable +#define B_PCH_PMC_FUNC_DIS_SDIO2 BIT9 // SCC SDIO #2 (Device 17, SDIO) Disable +#define B_PCH_PMC_FUNC_DIS_SDIO1 BIT8 // SCC SDIO #1 (Device 16, eMMC) Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC7 BIT7 // LPSS1 Spare #2 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC6 BIT6 // LPSS1 Spare #1 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC5 BIT5 // LPSS1 SPI Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC4 BIT4 // LPSS1 HS-UART #2 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC3 BIT3 // LPSS1 HS-UART #1 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC2 BIT2 // LPSS1 PWM #2 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC1 BIT1 // LPSS1 PWM #1 Disable +#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC0 BIT0 // LPSS1 DMA Disable + +#define R_PCH_PMC_FUNC_DIS2 0x38 // Function Disable 2 Register +#define B_PCH_PMC_FUNC_DIS2_USH_SS_PHY BIT2 // USH Super Speed PHY Disable +#define B_PCH_PMC_FUNC_DIS2_OTG_SS_PHY BIT1 // OTG Super Speed PHY Disable +#define B_PCH_PMC_FUNC_DIS2_SMBUS BIT0 // SMBus Disable + +#define R_PCH_PMC_PMIR 0x48 // Extended Test Mode Register (ETR) +#define B_PCH_PMC_PMIR_CF9LOCK BIT31 // CF9h Lockdown +#define B_PCH_PMC_PMIR_LTR_DEF BIT22 // LTR Default +#define B_PCH_PMC_PMIR_IGNORE_HPET BIT21 // Ignore HPET Disable Check Before Going to S0i2 +#define B_PCH_PMC_PMIR_CF9GR BIT20 // CF9h Global Reset + +#define R_PCH_PMC_VLT 0x50 // Voltage Detect Register +#define B_PCH_PMC_VLT_FUSES 0xFF // Voltage Detect Fuses + +#define R_PCH_PMC_GPI_ROUT 0x58 // GPI Rout +#define B_PCH_PMC_GPI_ROUT_0 (BIT1 | BIT0) +#define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2) +#define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4) +#define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6) +#define B_PCH_PMC_GPI_ROUT_4 (BIT9 | BIT8) +#define B_PCH_PMC_GPI_ROUT_5 (BIT11 | BIT10) +#define B_PCH_PMC_GPI_ROUT_6 (BIT13 | BIT12) +#define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14) +#define B_PCH_PMC_GPI_ROUT_8 (BIT17 | BIT16) +#define B_PCH_PMC_GPI_ROUT_9 (BIT19 | BIT18) +#define B_PCH_PMC_GPI_ROUT_10 (BIT21 | BIT20) +#define B_PCH_PMC_GPI_ROUT_11 (BIT23 | BIT22) +#define B_PCH_PMC_GPI_ROUT_12 (BIT25 | BIT24) +#define B_PCH_PMC_GPI_ROUT_13 (BIT27 | BIT26) +#define B_PCH_PMC_GPI_ROUT_14 (BIT29 | BIT28) +#define B_PCH_PMC_GPI_ROUT_15 (BIT31 | BIT30) + +#define R_PCH_PMC_PCC0 0x60 // Platform Clock Control 0 +#define B_PCH_PMC_PCC0_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC0_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_PCC1 0x64 // Platform Clock Control 1 +#define B_PCH_PMC_PCC1_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC1_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_PCC2 0x68 // Platform Clock Control 2 +#define B_PCH_PMC_PCC2_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC2_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_PCC3 0x6C // Platform Clock Control 3 +#define B_PCH_PMC_PCC3_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC3_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_PCC4 0x70 // Platform Clock Control 4 +#define B_PCH_PMC_PCC4_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC4_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_PCC5 0x74 // Platform Clock Control 5 +#define B_PCH_PMC_PCC5_CLK_FREQ BIT2 // Clock Frequency +#define B_PCH_PMC_PCC5_CLK_CTL (BIT1 | BIT0) // Clock Gating + +#define R_PCH_PMC_S0IR_TMR 0x80 // S0I Ready Residency Timer +#define B_PCH_PMC_S0IR_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I Ready State + +#define R_PCH_PMC_S0I1_TMR 0x84 // S0I1 Ready Residency Timer +#define B_PCH_PMC_S0I1_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I1 Ready State + +#define R_PCH_PMC_S0I2_TMR 0x88 // S0I2 Ready Residency Timer +#define B_PCH_PMC_S0I2_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I2 Ready State + +#define R_PCH_PMC_S0I3_TMR 0x8C // S0I3 Ready Residency Timer +#define B_PCH_PMC_S0I3_TMR_RTIME 0xFFFFFFFF // Time Spent in S0I3 Ready State + +#define R_PCH_PMC_S0_TMR 0x90 // S0 Residency Timer +#define B_PCH_PMC_S0_TMR_RTIME 0xFFFFFFFF // Time Spent in S0 State + +#define R_PCH_PMC_PSS 0x98 // Power Island Power Status +#define B_PCH_PMC_PSS_PG_STS 0x3FFFF // Power Gate Status of All Power Islands +#define B_PCH_PMC_PSS_PG_STS_USB_SUS BIT17 // USB SUS +#define B_PCH_PMC_PSS_PG_STS_USB BIT16 // USB +#define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK BIT15 // OTG VCCACLK +#define B_PCH_PMC_PSS_PG_STS_OTG VCCA BIT14 // OTG VCCA +#define B_PCH_PMC_PSS_PG_STS_OTG_VCCS BIT13 // OTG VCCS +#define B_PCH_PMC_PSS_PG_STS_OTG_CTL BIT12 // OTG Control +#define B_PCH_PMC_PSS_PG_STS_USH_VCCA BIT11 // USH VCCA +#define B_PCH_PMC_PSS_PG_STS_USH_VCCS BIT10 // USH VCCS +#define B_PCH_PMC_PSS_PG_STS_USH_SUS BIT9 // USH SUS +#define B_PCH_PMC_PSS_PG_STS_USH_CTL BIT8 // USH Control +#define B_PCH_PMC_PSS_PG_STS_DFX BIT7 // DFX +#define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio +#define B_PCH_PMC_PSS_PG_STS_LPSS BIT5 // LPSS +#define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe +#define B_PCH_PMC_PSS_PG_STS_HDA BIT2 // HDA +#define B_PCH_PMC_PSS_PG_STS_SATA BIT1 // SATA + +#define R_PCH_PMC_D3_STS_0 0xA0 // D3 Status 0 +#define B_PCH_PMC_D3_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7 +#define B_PCH_PMC_D3_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6 +#define B_PCH_PMC_D3_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5 +#define B_PCH_PMC_D3_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4 +#define B_PCH_PMC_D3_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3 +#define B_PCH_PMC_D3_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2 +#define B_PCH_PMC_D3_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1 +#define B_PCH_PMC_D3_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0 +#define B_PCH_PMC_D3_STS_0_PCIEF3 BIT23 // PCIe Function 3 +#define B_PCH_PMC_D3_STS_0_PCIEF2 BIT22 // PCIe Function 2 +#define B_PCH_PMC_D3_STS_0_PCIEF1 BIT21 // PCIe Function 1 +#define B_PCH_PMC_D3_STS_0_PCIEF0 BIT20 // PCIe Function 0 +#define B_PCH_PMC_D3_STS_0_USB BIT18 // USB +#define B_PCH_PMC_D3_STS_0_SATA BIT17 // SATA +#define B_PCH_PMC_D3_STS_0_USH BIT15 // USH +#define B_PCH_PMC_D3_STS_0_OTG BIT14 // OTG +#define B_PCH_PMC_D3_STS_0_LPE BIT13 // LPE +#define B_PCH_PMC_D3_STS_0_HDA BIT12 // HDA +#define B_PCH_PMC_D3_STS_0_MIPI BIT11 // MIPI-HSI +#define B_PCH_PMC_D3_STS_0_SCCF2 BIT10 // SCC Function 2 +#define B_PCH_PMC_D3_STS_0_SCCF1 BIT9 // SCC Function 1 +#define B_PCH_PMC_D3_STS_0_SCCF0 BIT8 // SCC Function 0 +#define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7 +#define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6 +#define B_PCH_PMC_D3_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5 +#define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4 +#define B_PCH_PMC_D3_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3 +#define B_PCH_PMC_D3_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2 +#define B_PCH_PMC_D3_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1 +#define B_PCH_PMC_D3_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0 + +#define R_PCH_PMC_D3_STS_1 0xA4 // D3 Status 1 +#define B_PCH_PMC_D3_STS_1_DFX BIT3 // DFX +#define B_PCH_PMC_D3_STS_1_OTG_SS BIT2 // OTG SS +#define B_PCH_PMC_D3_STS_1_USH_SS BIT1 // USH SS +#define B_PCH_PMC_D3_STS_1_SMB BIT0 // SMBus +#define R_PCH_PMC_D3_STDBY_STS_0 0xA8 // D3 Standby Status 0 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F7 BIT31 // LPSS 1 Function 7 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F6 BIT30 // LPSS 1 Function 6 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F5 BIT29 // LPSS 1 Function 5 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F4 BIT28 // LPSS 1 Function 4 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F3 BIT27 // LPSS 1 Function 3 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F2 BIT26 // LPSS 1 Function 2 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F1 BIT25 // LPSS 1 Function 1 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F0 BIT24 // LPSS 1 Function 0 +#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF3 BIT23 // PCIe Function 3 +#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF2 BIT22 // PCIe Function 2 +#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF1 BIT21 // PCIe Function 1 +#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF0 BIT20 // PCIe Function 0 +#define B_PCH_PMC_D3_STDBY_STS_0_USB BIT18 // USB +#define B_PCH_PMC_D3_STDBY_STS_0_SATA BIT17 // SATA +#define B_PCH_PMC_D3_STDBY_STS_0_USH BIT15 // USH +#define B_PCH_PMC_D3_STDBY_STS_0_OTG BIT14 // OTG +#define B_PCH_PMC_D3_STDBY_STS_0_LPE BIT13 // LPE +#define B_PCH_PMC_D3_STDBY_STS_0_HDA BIT12 // HDA +#define B_PCH_PMC_D3_STDBY_STS_0_MIPI BIT11 // MIPI-HSI +#define B_PCH_PMC_D3_STDBY_STS_0_SCCF2 BIT10 // SCC Function 2 +#define B_PCH_PMC_D3_STDBY_STS_0_SCCF1 BIT9 // SCC Function 1 +#define B_PCH_PMC_D3_STDBY_STS_0_SCCF0 BIT8 // SCC Function 0 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F5 BIT5 // LPSS 0 Function 5 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F2 BIT2 // LPSS 0 Function 2 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1 +#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0 + +#define R_PCH_PMC_D3_STDBY_STS_1 0xAC // D3 Standby Status 1 +#define B_PCH_PMC_D3_STDBY_STS_1_DFX BIT3 // DFX +#define B_PCH_PMC_D3_STDBY_STS_1_OTG_SS BIT2 // OTG SS +#define B_PCH_PMC_D3_STDBY_STS_1_USH_SS BIT1 // USH SS +#define B_PCH_PMC_D3_STDBY_STS_1_SMB BIT0 // SMBus + +#define R_PCH_PMC_MTPMC1 0xB0 // Message to PMC 1 + +#define R_PCH_PMC_MTPMC2 0xB4 // Message to PMC 2 + +#define R_PCH_PMC_MTPMC3 0xB8 // Message to PMC 3 + +#define R_PCH_PMC_MTPMC4 0xBC // Message to PMC 4 + +// +// IO Memory Space Registers (IOBASE) +// +#define R_PCH_CFIO_PAD_CONF0 0x00 // CFIO PAD_CONF0 +#define R_PCH_CFIO_PAD_CONF1 0x04 // CFIO PAD_CONF1 +#define R_PCH_CFIO_PAD_VAL 0x08 // CFIO PAD_VAL +#define R_PCH_CFIO_PAD_DFT 0x0C // CFIO PAD_CFT + +// +// GPIO Register Offsets from GBASE +// +#define R_PCH_GPIO_SC_USE_SEL 0x00 // GPIO South Usage Select [31:0] +#define R_PCH_GPIO_SC_IO_SEL 0x04 // GPIO South Input / Output Select [31:0] +#define R_PCH_GPIO_SC_LVL 0x08 // GPIO South Level for Input or Output [31:0] + +#define R_PCH_GPIO_SC_TPE 0x0C // GPIO South Trigger Positive Edge Enable [31:0] +#define R_PCH_GPIO_SC_TNE 0x10 // GPIO South Trigger Negative Edge Enable [31:0] +#define R_PCH_GPIO_SC_TS 0x14 // GPIO South Trigger Status [31:0] + +#define R_PCH_GPIO_SC_USE_SEL2 0x20 // GPIO South Usage Select 2 [63:32] +#define R_PCH_GPIO_SC_IO_SEL2 0x24 // GPIO South Input / Output Select 2 [63:32] +#define R_PCH_GPIO_SC_LVL2 0x28 // GPIO South Level for Input or Output 2 [63:32] + +#define R_PCH_GPIO_SC_TPE2 0x2C // GPIO South Trigger Positive Edge Enable 2 [63:32] +#define R_PCH_GPIO_SC_TNE2 0x30 // GPIO South Trigger Negative Edge Enable 2 [63:32] +#define R_PCH_GPIO_SC_TS2 0x34 // GPIO South Trigger Status 2 [63:32] + +#define R_PCH_GPIO_SC_USE_SEL3 0x40 // GPIO South Usage Select 3 [95:64] +#define R_PCH_GPIO_SC_IO_SEL3 0x44 // GPIO South Input / Output Select 3 [95:64] +#define R_PCH_GPIO_SC_LVL3 0x48 // GPIO South Level for Input or Output 3 [95:64] + +#define R_PCH_GPIO_SC_TPE3 0x4C // GPIO South Trigger Positive Edge Enable 3 [95:64] +#define R_PCH_GPIO_SC_TNE3 0x50 // GPIO South Trigger Negative Edge Enable 3 [95:64] +#define R_PCH_GPIO_SC_TS3 0x54 // GPIO South Trigger Status 3 [95:64] + +#define R_PCH_GPIO_SC_USE_SEL4 0x60 // GPIO South Usage Select 4 [127:96] +#define R_PCH_GPIO_SC_IO_SEL4 0x64 // GPIO South Input / Output Select 4 [127:96] +#define R_PCH_GPIO_SC_LVL4 0x68 // GPIO South Level for Input or Output 4 [127:96] + +#define R_PCH_GPIO_SC_TPE4 0x6C // GPIO South Trigger Positive Edge Enable 4 [127:96] +#define R_PCH_GPIO_SC_TNE4 0x70 // GPIO South Trigger Negative Edge Enable 4 [127:96] +#define R_PCH_GPIO_SC_TS4 0x74 // GPIO South Trigger Status 4 [127:96] + +#define R_PCH_GPIO_SUS_USE_SEL 0x80 // GPIO Suspend Use Select [31:0] +#define R_PCH_GPIO_SUS_IO_SEL 0x84 // GPIO Suspend Input / Output Select [31:0] +#define R_PCH_GPIO_SUS_LVL 0x88 // GPIO Suspend Level for Input or Output [31:0] + +#define R_PCH_GPIO_SUS_TPE 0x8C // GPIO Suspend Trigger Positive Edge Enable [31:0] +#define R_PCH_GPIO_SUS_TNE 0x90 // GPIO Suspend Trigger Negative Edge Enable [31:0] +#define R_PCH_GPIO_SUS_TS 0x94 // GPIO Suspend Trigger Status [31:0] + +#define R_PCH_GPIO_SUS_WAKE_EN 0x98 // GPIO Suspend Wake Enable [31:0] + +#define R_PCH_GPIO_SUS_USE_SEL2 0x100 // GPIO Suspend Use Select 2 [42:32] +#define R_PCH_GPIO_SUS_IO_SEL2 0x104 // GPIO Suspend Input / Output Select 2 [42:32] +#define R_PCH_GPIO_SUS_LVL2 0x108 // GPIO Suspend Level for Input or Output 2 [42:32] + +#define R_PCH_GPIO_SUS_TPE2 0x10C // GPIO Suspend Trigger Positive Edge Enable [42:32] +#define R_PCH_GPIO_SUS_TNE2 0x110 // GPIO Suspend Trigger Negative Edge Enable [42:32] +#define R_PCH_GPIO_SUS_TS2 0x114 // GPIO Suspend Trigger Status [42:32] + +#define R_PCH_GPIO_SUS_WAKE_EN2 0x118 // GPIO Suspend Wake Enable 2 [42:32] + +// +// Fixed IO Space +// + +// +// Processor Interface Registers +// +#define R_PCH_NMI_SC 0x61 // NMI Status and Control +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 // Timer Counter 2 Status +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 // Refresh Cycle toggle Status +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 // IOCHK NMI Enable +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 // SERR# NMI Enable +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 // Speaker Data Enable +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 // Timer Counter 2 Enable + +#define R_PCH_NMI_EN 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_RTC_INDEX +#define B_PCH_NMI_EN_NMI_EN BIT7 // NMI Enable, must preserve this bit first before writing to IO port 0x70 + +// +// RTC Registers +// +#define R_PCH_RTC_INDEX 0x70 // NMI Enable and Real Time Clock Index, Co-function with R_PCH_NMI_EN +#define R_PCH_RTC_TARGET 0x71 // Real-Time Clock Target Register +#define R_PCH_RTC_EXT_INDEX 0x72 // Extended RAM Index Register +#define R_PCH_RTC_EXT_TARGET 0x73 // Extended RAM Target Register +#define R_PCH_RTC_INDEX2 0x74 // Real-Time Clock Index Register +#define R_PCH_RTC_TARGET2 0x75 // Real-Time Clock Target Register +#define R_PCH_RTC_EXT_INDEX2 0x76 // Extended RAM Index Register +#define R_PCH_RTC_EXT_TARGET2 0x77 // Extended RAM Target Register + +#define R_PCH_RTC_SECONDS 0x00 // Seconds, Range 0..59 +#define R_PCH_RTC_SECONDSALARM 0x01 // Seconds Alarm, Range 0..59 +#define R_PCH_RTC_MINUTES 0x02 // Minutes, Range 0..59 +#define R_PCH_RTC_MINUTESALARM 0x03 // Minutes Alarm, Range 0..59 +#define R_PCH_RTC_HOURS 0x04 // Hours, Range 1..12 or 0..23 Bit 7 is AM/PM +#define R_PCH_RTC_HOURSALARM 0x05 // Hours Alarm, Range 1..12 or 0..23 Bit 7 is AM/PM +#define R_PCH_RTC_DAYOFWEEK 0x06 // Day of Week, Range 1..7 +#define R_PCH_RTC_DAYOFMONTH 0x07 // Day of Month, Range 1..31 +#define R_PCH_RTC_MONTH 0x08 // Month, Range 1..12 +#define R_PCH_RTC_YEAR 0x09 // Year, Range 0..99 + +#define R_PCH_RTC_REGISTERA 0x0A // RTC Register A +#define B_PCH_RTC_REGISTERA_UIP BIT7 // Update In Progress +#define B_PCH_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) // Division Chain Select +#define V_PCH_RTC_REGISTERA_DV_NORM_OP 0x20 // Normal Operation +#define V_PCH_RTC_REGISTERA_DV_BYP_5 0x30 // Bypass 5 Stages (Test mode only) +#define V_PCH_RTC_REGISTERA_DV_BYP_10 0x40 // Bypass 10 Stages (Test mode only) +#define V_PCH_RTC_REGISTERA_DV_BYP_15 0x50 // Bypass 15 Stages (Test mode only) +#define V_PCH_RTC_REGISTERA_DV_DIV_RST1 0x60 // Divider Reset +#define V_PCH_RTC_REGISTERA_DV_DIV_RST2 0x70 // Divider Reset +#define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select +#define V_PCH_RTC_REGISTERA_RS_INT_NV_TGL 0x00 // Interrupt Never Toggles +#define V_PCH_RTC_REGISTERA_RS_3P906MS1 0x01 // 3.90625 ms +#define V_PCH_RTC_REGISTERA_RS_7P812MS1 0x02 // 7.8125 ms +#define V_PCH_RTC_REGISTERA_RS_122P0US 0x03 // 122.070 us +#define V_PCH_RTC_REGISTERA_RS_244P1US 0x04 // 244.141 us +#define V_PCH_RTC_REGISTERA_RS_488P2US 0x05 // 488.281 us +#define V_PCH_RTC_REGISTERA_RS_976P5US 0x06 // 976.5625 us +#define V_PCH_RTC_REGISTERA_RS_1P953MS 0x07 // 1.953125 ms +#define V_PCH_RTC_REGISTERA_RS_3P906MS 0x08 // 3.90625 ms +#define V_PCH_RTC_REGISTERA_RS_7P812MS 0x09 // 7.8125 ms +#define V_PCH_RTC_REGISTERA_RS_15P62MS 0x0A // 15.625 ms +#define V_PCH_RTC_REGISTERA_RS_31P25MS 0x0B // 31.25 ms +#define V_PCH_RTC_REGISTERA_RS_62P5MS 0x0C // 62.5 ms +#define V_PCH_RTC_REGISTERA_RS_125MS 0x0D // 125 ms +#define V_PCH_RTC_REGISTERA_RS_250MS 0x0E // 250 ms +#define V_PCH_RTC_REGISTERA_RS_500MS 0x0F // 500 ms + +#define R_PCH_RTC_REGISTERB 0x0B // RTC Register B +#define B_PCH_RTC_REGISTERB_SET BIT7 // Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs +#define B_PCH_RTC_REGISTERB_PIE BIT6 // Periodic Interrupt Enable +#define B_PCH_RTC_REGISTERB_AIE BIT5 // Alarm Interrupt Enable +#define B_PCH_RTC_REGISTERB_UIE BIT4 // Update-ended Interrupt Enable +#define B_PCH_RTC_REGISTERB_SQWE BIT3 // Square Wave Enable (Not implemented) +#define B_PCH_RTC_REGISTERB_DM BIT2 // Data Mode 1: Binary; 0:BCD +#define B_PCH_RTC_REGISTERB_HF BIT1 // Hour Format 1: 24 mode; 0: 12 mode. +#define B_PCH_RTC_REGISTERB_DSE BIT0 // Daylight Savings Enable (Not Implemented) + +#define R_PCH_RTC_REGISTERC 0x0C // RTC Register C +#define B_PCH_RTC_REGISTERC_IRQF BIT7 // Interrupt Request Flag +#define B_PCH_RTC_REGISTERC_PF BIT6 // Periodic Interrupt Flag +#define B_PCH_RTC_REGISTERC_AF BIT5 // Alarm Flag +#define B_PCH_RTC_REGISTERC_UF BIT4 // Update-ended Flag +#define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0) + +#define R_PCH_RTC_REGISTERD 0x0D // RTC Register D +#define B_PCH_RTC_REGISTERD_VRT BIT7 // Valid RAM and Time Bit +#define B_PCH_RTC_REGISTERD_RESERVED BIT6 +#define B_PCH_RTC_REGISTERD_DA 0x3F // Date Alarm + +#define B_PCH_RTC_CENTURY 0x32 // Century Data + +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 // Advanced Power Management Control Port +#define R_PCH_APM_STS 0xB3 // Advanced Power Management Status Port + +// +// INIT Register +// +#define R_PCH_PORT92 0x92 +#define B_PCH_PORT92_ALT_A20_GATE BIT1 // Alternate A20 Gate +#define B_PCH_PORT92_INIT_NOW BIT0 // Init Now + +// +// PCU UART +// +#define R_PCH_COM1_BASE 0x3F8 // COM1 IO BASE + +// +// Reset Control Register +// +#define R_PCH_RST_CNT 0xCF9 // Reset Control +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 // Not supported by VLV +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// Fixed Memory Region +// + +// +// IO APIC Registers +// +#define R_PCH_IO_APIC_INDEX 0xFEC00000 // IOAPIC Index Register, 8bit +#define R_PCH_IO_APIC_WINDOW 0xFEC00010 // IOAPIC Window Register, 32bit +#define R_PCH_IO_APIC_EOI 0xFEC00040 // IOAPIC EOI Register, 8bit + +#define R_PCH_IO_APIC_ID 0x00 // Identification +#define B_PCH_IO_APIC_ID_AID (BIT27 | BIT26 | BIT25 | BIT24) // APIC Identification + +#define R_PCH_IO_APIC_VS 0x01 // Version +#define B_PCH_IO_APIC_VS_MRE 0xFF0000 // Maximum Redirection Entries +#define B_PCH_IO_APIC_VS_PRQ BIT15 // Pin Assertion Register Supported +#define B_PCH_IO_APIC_VS_VS 0xFF // Version + +// +// HPET Registers +// +#define R_PCH_PCH_HPET 0xFED00000 // HPET Base Address + +#define R_PCH_PCH_HPET_GCID 0x00 // HPET General Capabilities and ID, 64bit +#define B_PCH_PCH_HPET_GCID_CTP 0xFFFFFFFF00000000 // Counter Tick Period +#define B_PCH_PCH_HPET_GCID_VID 0xFFFF0000 // Vendor ID +#define B_PCH_PCH_HPET_GCID_LRC BIT15 // Legacy Rout Capable +#define B_PCH_PCH_HPET_GCID_CS BIT13 // Counter Size +#define B_PCH_PCH_HPET_GCID_NT 0x1F00 // Number of Timers +#define B_PCH_PCH_HPET_GCID_RID 0xFF // Revision ID +#define N_PCH_HPET_ADDR_ASEL 12 + +#define R_PCH_PCH_HPET_GCFG 0x10 // HPET General Configuration +#define B_PCH_PCH_HPET_GCFG_LRE BIT1 // Legacy Rout Enable +#define B_PCH_PCH_HPET_GCFG_EN BIT0 // Overall Enable + +#define R_PCH_PCH_HPET_GIS 0x20 // HPET General Interrupt Status +#define B_PCH_PCH_HPET_GIS_T2 BIT2 // Timer 2 Status +#define B_PCH_PCH_HPET_GIS_T1 BIT1 // Timer 1 Status +#define B_PCH_PCH_HPET_GIS_T0 BIT0 // Timer 0 Status + +#define R_PCH_PCH_HPET_MCV 0xF0 // HPET Main Counter Value, 64bit + +#define R_PCH_PCH_HPET_T0C 0x100 // HPET Timer 0 Config and Capabilities +#define R_PCH_PCH_HPET_T0CV_L 0x108 // HPET Timer 0 Lower Comparator Value +#define R_PCH_PCH_HPET_T0CV_H 0x10C // HPET Timer 0 Upper Comparator Value + +#define R_PCH_PCH_HPET_T1C 0x120 // HPET Timer 1 Config and Capabilities +#define R_PCH_PCH_HPET_T1CV 0x128 // HPET Timer 1 Comparator Value + +#define R_PCH_PCH_HPET_T2C 0x140 // HPET Timer 2 Config and Capabilities +#define R_PCH_PCH_HPET_T2CV 0x148 // HPET Timer 2 Comparator Value + +#define B_PCH_PCH_HPET_TXC_IRC 0xFFFFFFFF00000000 // Interrupt Rout Capability +#define B_PCH_PCH_HPET_TXC_FID BIT15 // FSB Interrupt Delivery +#define B_PCH_PCH_HPET_TXC_FE BIT14 // FSB Enable +#define B_PCH_PCH_HPET_TXC_IR 0x3E00 // Interrupt Rout +#define B_PCH_PCH_HPET_TXC_T32M BIT8 // Timer 32-bit Mode +#define B_PCH_PCH_HPET_TXC_TVS BIT6 // Timer Value Set +#define B_PCH_PCH_HPET_TXC_TS BIT5 // Timer Size +#define B_PCH_PCH_HPET_TXC_PIC BIT4 // Periodic Interrupt Capable +#define B_PCH_PCH_HPET_TXC_TYP BIT3 // Timer Type +#define B_PCH_PCH_HPET_TXC_IE BIT2 // Interrupt Enable +#define B_PCH_PCH_HPET_TXC_IT BIT1 // Timer Interrupt Type + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h new file mode 100644 index 0000000000..32f36458ad --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h @@ -0,0 +1,54 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsRcrb.h + + @brief + Register names for VLV Chipset Configuration Registers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_RCRB_H_ +#define _PCH_REGS_RCRB_H_ + +/// +/// Chipset Configuration Registers (Memory space) +/// RCBA +/// +#define R_PCH_RCRB_GCS 0x00 // General Control and Status +#define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size +#define B_PCH_RCRB_GCS_BBS (BIT11 | BIT10) // Boot BIOS Straps +#define V_PCH_RCRB_GCS_BBS_SPI (3 << 10) // Boot BIOS strapped to SPI +#define V_PCH_RCRB_GCS_BBS_LPC (0 << 10) // Boot BIOS strapped to LPC +#define B_PCH_RCRB_GCS_TS BIT1 // Top Swap +#define B_PCH_RCRB_GCS_BILD BIT0 // BIOS Interface Lock-Down + + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h new file mode 100644 index 0000000000..7b86de3831 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h @@ -0,0 +1,251 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsSata.h + + @brief + Register names for VLV SATA controllers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +/// +/// VLV SATA Message Bus +/// +#define PCH_SATA_PHY_PORT_ID 0xA3 // SATA PHY Port ID +#define PCH_SATA_PHY_MMIO_READ_OPCODE 0x00 // CUnit to SATA PHY MMIO Read Opcode +#define PCH_SATA_PHY_MMIO_WRITE_OPCODE 0x01 // CUnit to SATA PHY MMIO Write Opcode + +/// +/// SATA Controller Registers (D19:F0) +/// +#define PCI_DEVICE_NUMBER_PCH_SATA 19 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 + +#define R_PCH_SATA_ID 0x00 // Identifiers +#define B_PCH_SATA_ID_DID 0xFFFF0000 // Device ID +#define B_PCH_SATA_ID_VID 0x0000FFFF // Vendor ID +#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_SATA_DEVICE_ID_D_IDE 0x0F20 // Desktop IDE Mode (Ports 0 and 1) +#define V_PCH_SATA_DEVICE_ID_D_AHCI 0x0F22 // Desktop AHCI Mode (Ports 0 and 1) +#define V_PCH_SATA_DEVICE_ID_D_RAID 0x2822 // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7] + +#define V_PCH_SATA_DEVICE_ID_M_IDE 0x0F21 // Mobile IDE Mode (Ports 0 and 1) +#define V_PCH_SATA_DEVICE_ID_M_AHCI 0x0F23 // Mobile AHCI Mode (Ports 0 and 1) +#define V_PCH_SATA_DEVICE_ID_M_RAID 0x282A // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7] + +#define R_PCH_SATA_COMMAND 0x04 // Command +#define B_PCH_SATA_COMMAND_INT_DIS BIT10 // Interrupt Disable +#define B_PCH_SATA_COMMAND_FBE BIT9 // Fast Back-to-back Enable +#define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable +#define B_PCH_SATA_COMMAND_WCC BIT7 // Wait Cycle Enable +#define B_PCH_SATA_COMMAND_PER BIT6 // Parity Error Response Enable +#define B_PCH_SATA_COMMAND_VPS BIT5 // VGA Palette Snooping Enable +#define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable +#define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable +#define B_PCH_SATA_COMMAND_BME BIT2 // Bus Master Enable +#define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable +#define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable + +#define R_PCH_SATA_PCISTS 0x06 // Device Status +#define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error +#define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error +#define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status +#define B_PCH_SATA_PCISTS_RTA BIT12 // Received Target-Abort Status +#define B_PCH_SATA_PCISTS_STA BIT11 // Signaled Target-Abort Status +#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) // DEVSEL# Timing Status +#define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected +#define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List +#define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status + +#define R_PCH_SATA_RID 0x08 // Revision ID (8 bits) + +#define R_PCH_SATA_PI_REGISTER 0x09 // Programming Interface (8 bits) +#define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable +#define B_PCH_SATA_PI_REGISTER_SNE BIT2 // Secondary Mode Native Enable +#define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable +#define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable + +#define R_PCH_SATA_CC 0x0A // Class Code +#define B_PCH_SATA_CC_BCC 0xFF00 // Base Class Code +#define B_PCH_SATA_CC_SCC 0x00FF // Sub Class Code +#define V_PCH_SATA_CC_SCC_IDE 0x01 +#define V_PCH_SATA_CC_SCC_AHCI 0x06 +#define V_PCH_SATA_CC_SCC_RAID 0x04 + +#define R_PCH_SATA_CLS 0x0C // Cache Line Size (8 bits) +#define B_PCH_SATA_CLS 0xFF + +#define R_PCH_SATA_MLT 0x0D // Master Latency Timer (8 bits) +#define B_PCH_SATA_MLT 0xFF + +#define R_PCH_SATA_HTYPE 0x0E // Header Type +#define B_PCH_SATA_HTYPE_MFD BIT7 // Multi-function Device +#define B_PCH_SATA_HTYPE_HL 0x7F // Header Layout + +#define R_PCH_SATA_PCMD_BAR 0x10 // Primary Command Block Base Address +#define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 // Base Address +#define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_PCTL_BAR 0x14 // Primary Control Block Base Address +#define B_PCH_SATA_PCTL_BAR_BA 0x0000FFFC // Base Address +#define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_SCMD_BAR 0x18 // Secondary Command Block Base Address +#define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 // Base Address +#define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_SCTL_BAR 0x1C // Secondary Control Block Base Address +#define B_PCH_SATA_SCTL_BAR_BA 0x0000FFFC // Base Address +#define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_LBAR 0x20 // Legacy IDE Base Address / AHCI Index Data Pair Base Address +#define B_PCH_SATA_LBAR_BA 0x0000FFE0 // Base Address +#define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4 +#define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_SIDPBA 0x24 // Serial ATA Index Data Pair Base Address +#define R_PCH_SATA_ABAR 0x24 // AHCI Base Address +#define B_PCH_SATA_ABAR_BA 0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01) +#define V_PCH_SATA_ABAR_LENGTH 0x800 // AHCI Memory Length (When CC.SCC not equal 0x01) +#define N_PCH_SATA_ABAR_ALIGNMENT 11 // AHCI Base Address Alignment (When CC.SCC not equal 0x01) +#define B_PCH_SATA_SIDPBA_BA 0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01) +#define V_PCH_SATA_SIDPBA_LENGTH 0x10 // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01) +#define N_PCH_SATA_SIDPBA_ALIGNMENT 4 // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01) +#define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable +#define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type +#define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator + +#define R_PCH_SATA_SS 0x2C // Sub System Identifiers +#define B_PCH_SATA_SS_SSID 0xFFFF0000 // Subsystem ID +#define B_PCH_SATA_SS_SSVID 0x0000FFFF // Subsystem Vendor ID + +#define R_PCH_SATA_AHCI_CAP_PTR 0x34 // Capabilities Pointer (8 bits) +#define B_PCH_SATA_AHCI_CAP_PTR 0xFF + +#define R_PCH_SATA_INTR 0x3C // Interrupt Information +#define B_PCH_SATA_INTR_IPIN 0xFFFF0000 // Interrupt Pin +#define B_PCH_SATA_INTR_ILINE 0x0000FFFF // Interrupt Line + +#define R_PCH_SATA_PMCS 0x74 // PCI Power Management Control and Status +#define B_PCH_SATA_PMCS_PMES BIT15 // PME Status +#define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable +#define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 + +#define R_PCH_SATA_MAP 0x90 // Port Mapping Register +#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable +#define B_PCH_SATA_PORT6_DISABLED BIT14 +#define B_PCH_SATA_PORT5_DISABLED BIT13 +#define B_PCH_SATA_PORT4_DISABLED BIT12 +#define B_PCH_SATA_PORT3_DISABLED BIT11 +#define B_PCH_SATA_PORT2_DISABLED BIT10 +#define B_PCH_SATA_PORT1_DISABLED BIT9 +#define B_PCH_SATA_PORT0_DISABLED BIT8 +#define B_PCH_SATA_MAP_SMS_MASK (BIT7 | BIT6) // SATA Mode Select +#define V_PCH_SATA_MAP_SMS_IDE 0x00 +#define V_PCH_SATA_MAP_SMS_AHCI 0x40 +#define V_PCH_SATA_MAP_SMS_RAID 0x80 +#define B_PCH_SATA_PORT_TO_CONTROLLER_CFG BIT5 // SATA Port-to-Controller Configuration + +#define R_PCH_SATA_PCS 0x92 // Port Control and Status +#define S_PCH_SATA_PCS 0x2 +#define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode +#define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present +#define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present +#define B_PCH_SATA_PCS_PORT4_DET BIT12 // Port 4 Present +#define B_PCH_SATA_PCS_PORT3_DET BIT11 // Port 3 Present +#define B_PCH_SATA_PCS_PORT2_DET BIT10 // Port 2 Present +#define B_PCH_SATA_PCS_PORT1_DET BIT9 // Port 1 Present +#define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present +#define B_PCH_SATA_PCS_PORT5_EN BIT5 // Port 5 Enabled +#define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled +#define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled +#define B_PCH_SATA_PCS_PORT2_EN BIT2 // Port 2 Enabled +#define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled +#define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled + +#define R_PCH_SATA_AHCI_PI 0x0C // Ports Implemented +#define B_PCH_SATA_PORT_MASK 0x3F +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 // Port 5 Implemented +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 // Port 2 Implemented +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 // Port 0 Implemented + +#define R_PCH_SATA_AHCI_P0SSTS 0x128 // Port 0 Serial ATA Status +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 // Port 1 Serial ATA Status +#define B_PCH_SATA_AHCI_PXSSTS_IPM 0x00000F00 // Interface Power Management +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD 0x000000F0 // Current Interface Speed +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET 0x0000000F // Device Detection +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 + +// +// Macros of VLV capabilities for SATA controller which are used by SATA controller driver +// +// +// +// Define the individual capabilities of each SATA controller +// +#define PCH_SATA_MAX_CONTROLLERS 1 // Max SATA controllers number supported +#define PCH_SATA_MAX_DEVICES 2 // Max SATA devices number of single SATA channel +#define PCH_IDE_MAX_CHANNELS 2 // Max IDE channels number of single SATA controller +#define PCH_IDE_MAX_DEVICES 2 // Max IDE devices number of single SATA channel +#define PCH_AHCI_MAX_PORTS 2 // Max number of SATA ports in VLV +#define PCH_IDE_MAX_PORTS 2 // Max number of IDE ports in VLV + +// +// GPIOS_14 SATA0GP is the SATA port 0 reset pin. +// +#define PCH_GPIO_SATA_PORT0_RESET 14 +// +// GPIOS_15 SATA1GP is the SATA port 1 reset pin. +// +#define PCH_GPIO_SATA_PORT1_RESET 15 + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h new file mode 100644 index 0000000000..7b1af9ce6b --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h @@ -0,0 +1,59 @@ +/*++ + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchRegsScc.h + +Abstract: + + Register names for VLV SCC module. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +--*/ +#ifndef _PCH_REGS_SCC_H_ +#define _PCH_REGS_SCC_H_ + + +// +// SCC Modules Registers +// + +// +// SCC SDIO Modules +// PCI Config Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0 16 +#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1 17 +#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2 18 +#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_3 23 + +#define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO 0 + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h new file mode 100644 index 0000000000..075974a128 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h @@ -0,0 +1,155 @@ +/** + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsSmbus.h + + @brief + Register names for VLV Smbus Device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +/// +/// SMBus Controller Registers (D31:F3) +/// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3 + +#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID +#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID + +#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID +#define V_PCH_SMBUS_DEVICE_ID 0x0F12 + +#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt +#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable +#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0' +#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0' +#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0' +#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0' +#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0' +#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0' +#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0' +#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0' +#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable +#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable + +#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address +#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator + +#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID +#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status +#define B_PCH_SMBUS_IUS BIT6 // In Use Status +#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert +#define B_PCH_SMBUS_FAIL BIT4 // Failed +#define B_PCH_SMBUS_BERR BIT3 // Bus Error +#define B_PCH_SMBUS_DERR BIT2 // Device Error +#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR) +#define B_PCH_SMBUS_INTR BIT1 // Interrupt +#define B_PCH_SMBUS_HBSY BIT0 // Host Busy + +#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W +#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable +#define B_PCH_SMBUS_START BIT6 // Start +#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte +#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick +#define B_PCH_SMBUS_KILL BIT1 // Kill +#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable + +#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W +#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted + +#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W +#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave +#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write +#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read +#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write +// +#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W +#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W + +#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved) + +#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W + +#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC +#define B_PCH_SMBUS_CRCE BIT0 // CRC Error +// +#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W +#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer +#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC + +#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W +#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported +#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported +#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported + + +#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W +#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control +#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status +#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status + +#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status + +#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W +#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable + +#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address + +#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO +#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h new file mode 100644 index 0000000000..132c64b837 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h @@ -0,0 +1,119 @@ +/** + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsSpi.h + + @brief + Register names for PCH SPI device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +/// +/// SPI Host Interface Registers +/// + +#define R_PCH_SPI_HSFS 0x04 // Hardware Sequencing Flash Status Register (16bits) +#define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down +#define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid +#define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status +#define B_PCH_SPI_HSFS_SCIP BIT5 // SPI Cycle in Progress +#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size +#define V_PCH_SPI_HSFS_BERASE_256B 0x00 // Block/Sector = 256 Bytes +#define V_PCH_SPI_HSFS_BERASE_4K 0x01 // Block/Sector = 4K Bytes +#define V_PCH_SPI_HSFS_BERASE_8K 0x10 // Block/Sector = 8K Bytes +#define V_PCH_SPI_HSFS_BERASE_64K 0x11 // Block/Sector = 64K Bytes +#define B_PCH_SPI_HSFS_AEL BIT2 // Access Error Log +#define B_PCH_SPI_HSFS_FCERR BIT1 // Flash Cycle Error +#define B_PCH_SPI_HSFS_FDONE BIT0 // Flash Cycle Done + +#define R_PCH_SPI_PR0 0x74 // Protected Region 0 Register +#define B_PCH_SPI_PR0_WPE BIT31 // Write Protection Enable +#define B_PCH_SPI_PR0_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12] +#define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable +#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12] + +#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits) +#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask +#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask + +#define R_PCH_SPI_OPTYPE 0x96 // Opcode Type Configuration +#define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask +#define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask +#define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) // Opcode Type 5 Mask +#define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) // Opcode Type 4 Mask +#define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) // Opcode Type 3 Mask +#define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) // Opcode Type 2 Mask +#define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask +#define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) // Opcode Type 0 Mask +#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 // Read cycle type without address +#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 // Write cycle type without address +#define V_PCH_SPI_OPTYPE_RDADDR 0x02 // Address required; Read cycle type +#define V_PCH_SPI_OPTYPE_WRADDR 0x03 // Address required; Write cycle type + +#define R_PCH_SPI_OPMENU0 0x98 // Opcode Menu Configuration 0 (32bits) +#define R_PCH_SPI_OPMENU1 0x9C // Opcode Menu Configuration 1 (32bits) + +#define R_PCH_SPI_IND_LOCK 0xA4 // Indvidual Lock +#define B_PCH_SPI_IND_LOCK_PR0 BIT2 // PR0 LockDown + + +#define R_PCH_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register (32 bits) +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select +#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 // Flash Signature and Descriptor Map +#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 // Component +#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 // Region +#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 // Master +#define V_PCH_SPI_FDOC_FDSS_VLVS 0x4000 // Soft Straps +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index + +#define R_PCH_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register (32 bits) + +#define R_PCH_SPI_BCR 0xFC // BIOS Control Register +#define S_PCH_SPI_BCR 1 +#define B_PCH_SPI_BCR_SMM_BWP BIT5 // SMM BIOS Write Protect Disable +#define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC) +#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN 0x08 // Prefetch Enable, Cache Enable +#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 // Prefetch Disable, Cache Disable +#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN 0x00 // Prefetch Disable, Cache Enable +#define B_PCH_SPI_BCR_BLE BIT1 // Lock Enable (LE) +#define B_PCH_SPI_BCR_BIOSWE BIT0 // Write Protect Disable (WPD) +#define N_PCH_SPI_BCR_BLE 1 +#define N_PCH_SPI_BCR_BIOSWE 0 + +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 // Flash Valid Signature +#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h new file mode 100644 index 0000000000..ccc41a5909 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h @@ -0,0 +1,98 @@ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchRegsUsb.h + + @brief + Register names for PCH USB devices. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH__" in register/bit names. e.g., "_PCH_VLV_" + - Registers / bits that are different between SKUs are denoted by "_" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without inserted. + +**/ +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +/// +/// USB Definitions +/// + +typedef enum { + PchEhci1 = 0, + PchEhciControllerMax +} PCH_USB20_CONTROLLER_TYPE; + +#define PCH_USB_MAX_PHYSICAL_PORTS 4 /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R. +#define PCH_EHCI_MAX_PORTS 4 /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports. +#define PCH_HSIC_MAX_PORTS 2 +#define PCH_XHCI_MAX_USB3_PORTS 1 + +#define PCI_DEVICE_NUMBER_PCH_USB 29 +#define PCI_FUNCTION_NUMBER_PCH_EHCI 0 + +#define R_PCH_USB_VENDOR_ID 0x00 // Vendor ID +#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define R_PCH_USB_DEVICE_ID 0x02 // Device ID +#define V_PCH_USB_DEVICE_ID_0 0x0F34 // EHCI#1 + +#define R_PCH_EHCI_SVID 0x2C // USB2 Subsystem Vendor ID +#define B_PCH_EHCI_SVID 0xFFFF // USB2 Subsystem Vendor ID Mask + +#define R_PCH_EHCI_PWR_CNTL_STS 0x54 // Power Management Control / Status +#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status +#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale +#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) // Data Select +#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable +#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State +#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0 0 // D0 State +#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State + +/// +/// USB3 (XHCI) related definitions +/// +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 +// +///// +///// XHCI PCI Config Space registers +///// + +#define R_PCH_XHCI_SVID 0x2C +#define B_PCH_XHCI_SVID 0xFFFF + + +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h new file mode 100644 index 0000000000..3e90a12426 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h @@ -0,0 +1,81 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchInit.h + + @brief + This file defines the PCH Init PPI + +**/ +#ifndef _PCH_INIT_H_ +#define _PCH_INIT_H_ + +// +// Define the PCH Init PPI GUID +// + + +#include +#define PCH_INIT_PPI_GUID \ + { \ + 0x9ea894a, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95 \ + } +extern EFI_GUID gPchInitPpiGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _PCH_INIT_PPI PCH_INIT_PPI; + +/// +/// Data structure definitions +/// +typedef enum _CPU_STRAP_OPERATION { + GetCpuStrapSetData, + SetCpuStrapSetData, + LockCpuStrapSetData +} CPU_STRAP_OPERATION; + +typedef +EFI_STATUS +(EFIAPI *PCH_USB_INIT) ( + IN EFI_PEI_SERVICES **PeiServices + ) +/** + + @brief + The function performing USB init in PEI phase. This could be used by USB recovery + or debug features that need USB initialization during PEI phase. + Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize + has been done and PchUsbPolicyPpi has been installed. + + @param[in] PeiServices General purpose services available to every PEIM + + @retval EFI_SUCCESS The function completed successfully + @retval Others All other error conditions encountered result in an ASSERT. + +**/ +; + +/// +/// PCH_INIT_PPI Structure Definition +/// +struct _PCH_INIT_PPI { + PCH_USB_INIT UsbInit; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h new file mode 100644 index 0000000000..81995cf5a5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h @@ -0,0 +1,40 @@ + +/*++ + +Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +Module Name: + + PchPeiInit.h + +Abstract: + + +--*/ + +#ifndef _PCH_PEI_INIT_H_ +#define _PCH_PEI_INIT_H_ + +// +// Define the PCH PEI Init PPI GUID +// +#define PCH_PEI_INIT_PPI_GUID \ + { \ + 0xACB93B08, 0x5CDC, 0x4A8F, 0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E \ + } + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchPeiInitPpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h new file mode 100644 index 0000000000..f2f444c77b --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h @@ -0,0 +1,167 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchPlatformPolicy.h + + @brief + PCH policy PPI produced by a platform driver specifying various + expected PCH settings. This PPI is consumed by the PCH PEI modules. + +**/ +#ifndef PCH_PLATFORM_POLICY_H_ +#define PCH_PLATFORM_POLICY_H_ +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// + + +#include "PchRegs.h" + +// +#define PCH_PLATFORM_POLICY_PPI_GUID \ + { \ + 0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \ + } + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI; + +/// +/// PPI revision number +/// Any backwards compatible changes to this PPI will result in an update in the revision number +/// Major changes will require publication of a new PPI +/// +/// Revision 1: Original version +/// +#define PCH_PLATFORM_POLICY_PPI_REVISION_1 1 +#define PCH_PLATFORM_POLICY_PPI_REVISION_2 2 +#define PCH_PLATFORM_POLICY_PPI_REVISION_3 3 +#define PCH_PLATFORM_POLICY_PPI_REVISION_4 4 +#define PCH_PLATFORM_POLICY_PPI_REVISION_5 5 +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +typedef struct { + UINT8 ThermalDataReportEnable : 1; // OBSOLETE from Revision 5 !!! DO NOT USE !!! + UINT8 MchTempReadEnable : 1; + UINT8 PchTempReadEnable : 1; + UINT8 CpuEnergyReadEnable : 1; + UINT8 CpuTempReadEnable : 1; + UINT8 Cpu2TempReadEnable : 1; + UINT8 TsOnDimmEnable : 1; + UINT8 Dimm1TempReadEnable : 1; + + UINT8 Dimm2TempReadEnable : 1; + UINT8 Dimm3TempReadEnable : 1; + UINT8 Dimm4TempReadEnable : 1; + UINT8 Rsvdbits : 5; +} PCH_THERMAL_REPORT_CONTROL; +// +// ---------------------------- HPET Config ----------------------------- +// +typedef struct { + BOOLEAN Enable; /// Determines if enable HPET function + UINT32 Base; /// The HPET base address +} PCH_HPET_CONFIG; + + +/// +/// ---------------------------- SATA Config ----------------------------- +/// +typedef enum { + PchSataModeIde, + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +/// +/// ---------------------------- PCI Express Config ----------------------------- +/// +typedef enum { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2 +} PCH_PCIE_SPEED; + +typedef struct { + PCH_PCIE_SPEED PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS]; +} PCH_PCIE_CONFIG; + +/// +/// ---------------------------- IO APIC Config ----------------------------- +/// +typedef struct { + UINT8 IoApicId; +} PCH_IOAPIC_CONFIG; + +/// +/// --------------------- Low Power Input Output Config ------------------------ +/// +typedef struct { + UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled + UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled + UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled + UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled + UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled + UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled + UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled + UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled + UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled + UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled + UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled + UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled + UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled + UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled + UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled + UINT8 Rsvdbits : 2; +} PEI_PCH_LPSS_CONFIG; + +/// +/// ------------ General PCH Platform Policy PPI definition ------------ +/// +struct _PCH_PLATFORM_POLICY_PPI { + UINT8 Revision; + UINT8 BusNumber; // Bus Number of the PCH device + UINT32 SpiBase; // SPI Base Address. + UINT32 PmcBase; // PMC Base Address. + UINT32 SmbmBase; // SMB Memory Base Address. + UINT32 IoBase; // IO Base Address. + UINT32 IlbBase; // Intel Legacy Block Base Address. + UINT32 PUnitBase; // PUnit Base Address. + UINT32 Rcba; // Root Complex Base Address. + UINT32 MphyBase; // MPHY Base Address. + UINT16 AcpiBase; // ACPI I/O Base address. + UINT16 GpioBase; // GPIO Base address + PCH_HPET_CONFIG *HpetConfig; + PCH_SATA_MODE SataMode; + PCH_PCIE_CONFIG *PcieConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PEI_PCH_LPSS_CONFIG *LpssConfig; + BOOLEAN EnableRmh; // Determines if enable USB RMH function + BOOLEAN EhciPllCfgEnable; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h new file mode 100644 index 0000000000..41c2b48263 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h @@ -0,0 +1,75 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchUsbPolicy.h + + @brief + PCH Usb policy PPI produced by a platform driver specifying + various expected PCH Usb settings. This PPI is consumed by the + PCH PEI drivers. + +**/ +#ifndef _PCH_USB_POLICY_H_ +#define _PCH_USB_POLICY_H_ + +// +// PCH Usb policy provided by platform for PEI phase +// + +#ifndef ECP_FLAG +#include +#endif + +#include "PchRegs.h" +#include + +#define PCH_USB_POLICY_PPI_GUID \ + { \ + 0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \ + } + +extern EFI_GUID gPchUsbPolicyPpiGuid; + +typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI; + +/// +/// PPI revision number +/// Any backwards compatible changes to this PPI will result in an update in the revision number +/// Major changes will require publication of a new PPI +/// +/// Revision 1: Original version +/// +#define PCH_USB_POLICY_PPI_REVISION_1 1 + +/// +/// Generic definitions for device enabling/disabling used by PCH code. +/// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +#define EHCI_MODE 1 + +struct _PCH_USB_POLICY_PPI { + UINT8 Revision; + PCH_USB_CONFIG *UsbConfig; + UINT8 Mode; + UINTN EhciMemBaseAddr; + UINT32 EhciMemLength; + UINTN XhciMemBaseAddr; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h new file mode 100644 index 0000000000..16a137f151 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h @@ -0,0 +1,236 @@ +/** @file + Block IO protocol as defined in the UEFI 2.0 specification. + + The Block IO protocol is used to abstract block devices like hard drives, + DVD-ROMs and floppy drives. + + Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PEI_BLOCK_IO_H__ +#define __PEI_BLOCK_IO_H__ +// {BC5FA650-EDBB-4d0d-B3A3-D98907F847DF} +#ifndef ECP_FLAG +#define PEI_BLOCK_IO_PPI_GUID \ + { \ + 0xbc5fa650, 0xedbb, 0x4d0d, { 0xb3, 0xa3, 0xd9, 0x89, 0x7, 0xf8, 0x47, 0xdf } \ + } +#endif +typedef struct _PEI_BLOCK_IO_PPI PEI_BLOCK_IO_PPI; + + +/** + Reset the Block Device. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Driver may perform diagnostics on reset. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The device is not functioning properly and could + not be reset. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_RESET)( + IN PEI_BLOCK_IO_PPI *This, + IN BOOLEAN ExtendedVerification + ); + +/** + Read BufferSize bytes from Lba into Buffer. + + @param This Indicates a pointer to the calling context. + @param MediaId Id of the media, changes every time the media is replaced. + @param Lba The starting Logical Block Address to read from + @param BufferSize Size of Buffer, must be a multiple of device block size. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while performing the read. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_READ)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BLOCK_IO_PPI *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ); + +/** + Write BufferSize bytes from Lba into Buffer. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. The caller is + responsible for writing to only legitimate locations. + @param BufferSize Size of Buffer, must be a multiple of device block size. + @param Buffer A pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data was written correctly to the device. + @retval EFI_WRITE_PROTECTED The device can not be written to. + @retval EFI_DEVICE_ERROR The device reported an error while performing the write. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHNAGED The MediaId does not matched the current device. + @retval EFI_BAD_BUFFER_SIZE The Buffer was not a multiple of the block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_WRITE)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BLOCK_IO_PPI *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ); + +/** + Flush the Block Device. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data was written to the device + @retval EFI_DEVICE_ERROR The device reported an error while writting back the data + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_BLOCK_FLUSH)( + IN PEI_BLOCK_IO_PPI *This + ); + +/** + Block IO read only mode data and updated only via members of BlockIO +**/ +typedef struct { + /// + /// The curent media Id. If the media changes, this value is changed. + /// + UINT32 MediaId; + + /// + /// TRUE if the media is removable; otherwise, FALSE. + /// + BOOLEAN RemovableMedia; + + /// + /// TRUE if there is a media currently present in the device; + /// othersise, FALSE. THis field shows the media present status + /// as of the most recent ReadBlocks() or WriteBlocks() call. + /// + BOOLEAN MediaPresent; + + /// + /// TRUE if LBA 0 is the first block of a partition; otherwise + /// FALSE. For media with only one partition this would be TRUE. + /// + BOOLEAN LogicalPartition; + + /// + /// TRUE if the media is marked read-only otherwise, FALSE. + /// This field shows the read-only status as of the most recent WriteBlocks () call. + /// + BOOLEAN ReadOnly; + + /// + /// TRUE if the WriteBlock () function caches write data. + /// + BOOLEAN WriteCaching; + + /// + /// The intrinsic block size of the device. If the media changes, then + /// this field is updated. + /// + UINT32 BlockSize; + + /// + /// Supplies the alignment requirement for any buffer to read or write block(s). + /// + UINT32 IoAlign; + + /// + /// The last logical block address on the device. + /// If the media changes, then this field is updated. + /// + EFI_LBA LastBlock; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to + /// a physical block boundary. + /// + EFI_LBA LowestAlignedLba; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks + /// per physical block. + /// + UINT32 LogicalBlocksPerPhysicalBlock; + + /// + /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to + /// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length + /// granularity as a number of logical blocks. + /// + UINT32 OptimalTransferLengthGranularity; +#ifdef ECP_FLAG +} PEI_BLOCK_IO_MEDIA2; +#else +} PEI_BLOCK_IO_MEDIA; +#endif +#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000 +#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001 +#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031 + +/// +/// Revision defined in EFI1.1. +/// +#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION + +/// +/// This protocol provides control over block devices. +/// +struct _PEI_BLOCK_IO_PPI { + /// + /// The revision to which the block IO interface adheres. All future + /// revisions must be backwards compatible. If a future version is not + /// back wards compatible, it is not the same GUID. + /// + UINT64 Revision; + /// + /// Pointer to the EFI_BLOCK_IO_MEDIA data for this device. + /// + PEI_BLOCK_IO_MEDIA *Media; + PEI_BLOCK_RESET Reset; + PEI_BLOCK_READ ReadBlocks; + PEI_BLOCK_WRITE WriteBlocks; + PEI_BLOCK_FLUSH FlushBlocks; +}; + +//extern EFI_GUID gEfiBlockIoProtocolGuid; +extern EFI_GUID gPeiBlockIoPpiGuid; +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h new file mode 100644 index 0000000000..2239959e8f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h @@ -0,0 +1,365 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + Spi.h + + @brief + This file defines the EFI SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +**/ +#ifndef _PEI_SDHC_H_ +#define _PEI_SDHC_H_ + + + +// +#define PEI_SDHC_PPI_GUID \ + { \ + 0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \ + } +typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI; + +#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01 + +typedef enum { + ResponseNo = 0, + ResponseR1, + ResponseR1b, + ResponseR2, + ResponseR3, + ResponseR4, + ResponseR5, + ResponseR5b, + ResponseR6, + ResponseR7 +} RESPONSE_TYPE; + +typedef enum { + NoData = 0, + InData, + OutData +} TRANSFER_TYPE; + +typedef enum { + Reset_Auto = 0, + Reset_DAT, + Reset_CMD, + Reset_DAT_CMD, + Reset_All +} RESET_TYPE; + + + +typedef enum { + SDMA = 0, + ADMA2, + PIO +} DMA_MOD; + +typedef struct { + UINT32 HighSpeedSupport: 1; //High speed supported + UINT32 V18Support: 1; //1.8V supported + UINT32 V30Support: 1; //3.0V supported + UINT32 V33Support: 1; //3.3V supported + UINT32 Reserved0: 4; + UINT32 BusWidth4: 1; // 4 bit width + UINT32 BusWidth8: 1; // 8 bit width + UINT32 Reserved1: 6; + UINT32 SDMASupport: 1; + UINT32 ADMA2Support: 1; + UINT32 DmaMode: 2; + UINT32 Reserved2: 12; + UINT32 BoundarySize; +}HOST_CAPABILITY; + + +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_IF_STANDARD_HOST_NO_DMA 0x00 +#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01 + +// +//MMIO Registers definition for MMC/SDIO controller +// +#define MMIO_DMAADR 0x00 +#define MMIO_BLKSZ 0x04 +#define MMIO_BLKCNT 0x06 +#define MMIO_CMDARG 0x08 +#define MMIO_XFRMODE 0x0C +#define MMIO_SDCMD 0x0E +#define MMIO_RESP 0x10 +#define MMIO_BUFDATA 0x20 +#define MMIO_PSTATE 0x24 +#define MMIO_HOSTCTL 0x28 +#define MMIO_PWRCTL 0x29 +#define MMIO_BLKGAPCTL 0x2A +#define MMIO_WAKECTL 0x2B +#define MMIO_CLKCTL 0x2C +#define MMIO_TOCTL 0x2E +#define MMIO_SWRST 0x2F +#define MMIO_NINTSTS 0x30 +#define MMIO_ERINTSTS 0x32 +#define MMIO_NINTEN 0x34 +#define MMIO_ERINTEN 0x36 +#define MMIO_NINTSIGEN 0x38 +#define MMIO_ERINTSIGEN 0x3A +#define MMIO_AC12ERRSTS 0x3C +#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2 +#define MMIO_CAP 0x40 +#define MMIO_CAP2 0x44 //hphang <- New in VLV2 +#define MMIO_MCCAP 0x48 +#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2 +#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2 +#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2 +#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2 +#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2 +#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2 +#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2 +#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2 +#define MMIO_SLTINTSTS 0xFC +#define MMIO_CTRLRVER 0xFE +#define MMIO_SRST 0x1FC + +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData OPTIONAL + ); + +/*++ + + Routine Description: + Set max clock frequency of the host, the actual frequency + may not be the same as MaxFrequency. It depends on + the max frequency the host can support, divider, and host + speed mode. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + MaxFrequency - Max frequency in HZ + + Returns: + EFI_SUCCESS + EFI_TIMEOUT +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT32 MaxFrequency + ); + +/*++ + + Routine Description: + Set bus width of the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BusWidth - Bus width in 1, 4, 8 bits + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT32 BusWidth + ); + +/*++ + + Routine Description: + Set Host mode in DDR + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + SetHostDdrMode - True for DDR Mode set, false for normal mode + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT32 DdrMode + ); + +/*++ + + Routine Description: + Set voltage which could supported by the host. + Support 0(Power off the host), 1.8V, 3.0V, 3.3V + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Voltage - Units in 0.1 V + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT32 Voltage + ); + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + ResetAll - TRUE to reset all + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN RESET_TYPE ResetType + ); + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Enable - TRUE to enable, FALSE to disable + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN BOOLEAN Enable + ); + +/*++ + + Routine Description: + Find whether these is a card inserted into the slot. If so + init the host. If not, return EFI_NOT_FOUND. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + + Returns: + EFI_SUCCESS + EFI_NOT_FOUND + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) ( + IN PEI_SD_CONTROLLER_PPI *This + ); + +/*++ + + Routine Description: + Set the Block length + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BlockLength - card supportes block length + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) ( + IN PEI_SD_CONTROLLER_PPI *This, + IN UINT32 BlockLength + ); + +/*++ + + Routine Description: + Set the Block length + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BlockLength - card supportes block length + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ + +typedef EFI_STATUS +(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)( + IN PEI_SD_CONTROLLER_PPI *This + ); + +// +// Interface structure for the EFI SD Host I/O Protocol +// +struct _PEI_SD_CONTROLLER_PPI { + UINT32 Revision; + HOST_CAPABILITY HostCapability; + EFI_SD_CONTROLLER_PPI_SEND_COMMAND SendCommand; + EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY SetClockFrequency; + EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH SetBusWidth; + EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE SetHostVoltage; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode; + EFI_SD_CONTROLLER_PPI_RESET_SD_HOST ResetSdHost; + EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd; + EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost; + EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH SetBlockLength; + EFI_SD_CONTROLLER_PPI_SETUP_DEVICE SetupDevice; +}; +// Extern the GUID for PPI users. +// +extern EFI_GUID gPeiSdhcPpiGuid; + + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h new file mode 100644 index 0000000000..c4eba99449 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h @@ -0,0 +1,46 @@ +// +// + +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmbusPolicy.h + +Abstract: + + Smbus Policy PPI as defined in EFI 2.0 + +--*/ +#ifndef _PEI_SMBUS_POLICY_PPI_H +#define _PEI_SMBUS_POLICY_PPI_H + +#define PEI_SMBUS_POLICY_PPI_GUID \ + { \ + 0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \ + } + +typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI; + +typedef struct _PEI_SMBUS_POLICY_PPI { + UINTN BaseAddress; + UINT32 PciAddress; + UINT8 NumRsvdAddress; + UINT8 *RsvdAddress; +} PEI_SMBUS_POLICY_PPI; + +extern EFI_GUID gPeiSmbusPolicyPpiGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h new file mode 100644 index 0000000000..7c8afec0bf --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h @@ -0,0 +1,48 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + Spi.h + + @brief + This file defines the EFI SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +**/ +#ifndef _PEI_SPI_H_ +#define _PEI_SPI_H_ + + +#include + + +// +#define PEI_SPI_PPI_GUID \ + { \ + 0xa38c6898, 0x2b5c, 0x4ff6, 0x93, 0x26, 0x2e, 0x63, 0x21, 0x2e, 0x56, 0xc2 \ + } +// Extern the GUID for PPI users. +// +extern EFI_GUID gPeiSpiPpiGuid; + +/// +/// Reuse the EFI_SPI_PROTOCOL definitions +/// This is possible becaues the PPI implementation does not rely on a PeiService pointer, +/// as it uses EDKII Glue Lib to do IO accesses +/// +typedef EFI_SPI_PROTOCOL PEI_SPI_PPI; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h new file mode 100644 index 0000000000..4f45d8b661 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h @@ -0,0 +1,129 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + ActiveBios.h + + @brief + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + + This protocol is EFI compatible. + + E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped + to PCI, SPI, or FWH. + +**/ +#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_ +#define _EFI_ACTIVE_BIOS_PROTOCOL_H_ + + + + +// +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { \ + 0xebbe2d1b, 0x1647, 0x4bda, 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \ + } +extern EFI_GUID gEfiActiveBiosProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL; + +/// +/// Protocol definitions +/// +typedef enum { + ActiveBiosStateSpi, + ActiveBiosStatePci, /// Obsolete since VLV + ActiveBiosStateLpc, + ActiveBiosStateMax +} EFI_ACTIVE_BIOS_STATE; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN EFI_ACTIVE_BIOS_STATE DesiredState, + IN UINTN Key + ) +/** + + @brief + Change the current active BIOS settings to the requested state. + The caller is responsible for requesting a supported state from + the EFI_ACTIVE_BIOS_STATE selections. + This will fail if someone has locked the interface and the correct key is + not provided. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] DesiredState The requested state to configure the system for. + @param[in] Key If the interface is locked, Key must be the Key + returned from the LockState function call. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_ACCESS_DENIED The interface is currently locked. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN BOOLEAN Lock, + IN OUT UINTN *Key + ); + +/** + + @brief + Lock the current active BIOS state from further changes. This allows a + caller to implement a critical section. This is optionally supported + functionality. Size conscious implementations may choose to require + callers cooperate without support from this protocol. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] Lock TRUE to lock the current state, FALSE to unlock. + @param[in] Key If Lock is TRUE, then a key will be returned. If + Lock is FALSE, the key returned from the prior call + to lock the protocol must be provided to unlock the + protocol. The value of Key is undefined except that + it cannot be 0. + + @retval EFI_SUCCESS Command succeed. + @exception EFI_UNSUPPORTED The function is not supported. + @retval EFI_ACCESS_DENIED The interface is currently locked. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. + +**/ + +/// +/// Protocol definition +/// +/// Note that some functions are optional. This means that they may be NULL. +/// Caller is required to verify that an optional function is defined by checking +/// that the value is not NULL. +/// +struct _EFI_ACTIVE_BIOS_PROTOCOL { + EFI_ACTIVE_BIOS_STATE State; + EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; + EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h new file mode 100644 index 0000000000..e59cfc09f5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h @@ -0,0 +1,131 @@ +/** + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + + This protocol is EFI compatible. + + E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped + to PCI, SPI, or FWH. + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + + +#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_ +#define _EFI_ACTIVE_BIOS_PROTOCOL_H_ + +// +// Define the protocol GUID +// +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { 0xebbe2d1b, 0x1647, 0x4bda, {0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a} } + +typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL; + +// +// Protocol definitions +// +typedef enum { + ActiveBiosStateSpi, + ActiveBiosStatePci, + ActiveBiosStateLpc, + ActiveBiosStateMax +} EFI_ACTIVE_BIOS_STATE; + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL *This, + IN EFI_ACTIVE_BIOS_STATE DesiredState, + IN UINTN Key + ); +/*++ + +Routine Description: + + Change the current active BIOS settings to the requested state. + The caller is responsible for requesting a supported state from + the EFI_ACTIVE_BIOS_STATE selections. + + This will fail if someone has locked the interface and the correct key is + not provided. + +Arguments: + + This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + DesiredState The requested state to configure the system for. + Key If the interface is locked, Key must be the Key + returned from the LockState function call. + +Returns: + + EFI_SUCCESS Command succeed. + EFI_ACCESS_DENIED The interface is currently locked. + EFI_DEVICE_ERROR Device error, command aborts abnormally. + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL *This, + IN BOOLEAN Lock, + IN OUT UINTN *Key + ); +/*++ + +Routine Description: + + Lock the current active BIOS state from further changes. This allows a + caller to implement a critical section. This is optionally supported + functionality. Size conscious implementations may choose to require + callers cooperate without support from this protocol. + +Arguments: + + This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + Lock TRUE to lock the current state, FALSE to unlock. + Key If Lock is TRUE, then a key will be returned. If + Lock is FALSE, the key returned from the prior call + to lock the protocol must be provided to unlock the + protocol. The value of Key is undefined except that it + will never be 0. + +Returns: + + EFI_SUCCESS Command succeed. + EFI_UNSUPPORTED The function is not supported. + EFI_ACCESS_DENIED The interface is currently locked. + EFI_DEVICE_ERROR Device error, command aborts abnormally. + +--*/ + +// +// Protocol definition +// +// Note that some functions are optional. This means that they may be NULL. +// Caller is required to verify that an optional function is defined by checking +// that the value is not NULL. +// +struct _EFI_ACTIVE_BIOS_PROTOCOL { + EFI_ACTIVE_BIOS_STATE State; + EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; + EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; +}; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiActiveBiosProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h new file mode 100644 index 0000000000..25dbb502ac --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h @@ -0,0 +1,57 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + DxePchPolicyUpdateProtocol.h + +Abstract: + + PCH policy update protocol. This protocol is consumed by the PchDxePolicyInit driver + +--*/ +#ifndef _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_ +#define _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_ + +#include "PchRegs.h" + + +#ifdef ECP_FLAG +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \ + { \ + 0x1a819e49, 0xd8ee, 0x48cb, 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \ + } +#else +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \ + { \ + 0x1a819e49, 0xd8ee, 0x48cb, \ + { \ + 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \ + } \ + } +#endif + +extern EFI_GUID gDxePchPolicyUpdateProtocolGuid; +#define DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1 1 + +// +// ------------ General PCH policy Update protocol definition ------------ +// +struct _DXE_PCH_POLICY_UPDATE_PROTOCOL { + UINT8 Revision; +}; + +typedef struct _DXE_PCH_POLICY_UPDATE_PROTOCOL DXE_PCH_POLICY_UPDATE_PROTOCOL; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h new file mode 100644 index 0000000000..718ddbcc7f --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h @@ -0,0 +1,48 @@ +/*++ + +Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ +Module Name: + + EmmcCardInfoProtocol.h + +Abstract: + + Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL + +--*/ + + +#ifndef _EMMC_CARD_INFO_H_ +#define _EMMC_CARD_INFO_H_ + +#define EFI_EMMC_CARD_INFO_PROTOCOL_GUID \ + { \ + 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd } \ + } + +typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL; + + +// +// EMMC Card info Structures +// +struct _EFI_EMMC_CARD_INFO_PROTOCOL { + CARD_DATA *CardData; +}; + +extern EFI_GUID gEfiEmmcCardInfoProtocolGuid; +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h new file mode 100644 index 0000000000..030fb83d74 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h @@ -0,0 +1,167 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + Gpio.h + +Abstract: + +EFI 2.0 PEIM to provide platform specific information to other +modules and to do some platform specific initialization. + +--*/ + +#ifndef _PEI_GPIO_H +#define _PEI_GPIO_H + +//#include "Efi.h" +//#include "EfiCommonLib.h" +//#include "Pei.h" +//#include "Numbers.h" + +//// +//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint) +//// +//// Field Descriptions: +//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode. +//// I/O: Defines whether GPIOs are inputs (I) or outputs (O). +//// (Note: Only meaningful for pins used as GPIOs.) +//// LVL: This field gives you the initial value for "output" GPIO's. +//// (Note: The output level is dependent upon whether the pin is inverted.) +//// INV: Defines whether Input GPIOs activation level is inverted. +//// (Note: Only affects the level sent to the GPE logic and does not +//// affect the level read through the GPIO registers.) +//// +//// Notes: +//// 1. BoardID is GPIO [8:38:34] +//// +////Signal UsedAs USE I/O LVL INV +////-------------------------------------------------------------------------- +////GPIO0 Nonfunction G O H - +////GPIO1 SMC_RUNTIME_SCI# G I - I +////PIRQE#/GPIO2 Nonfunction G O H - +////PIRQF#/GPIO3 Nonfunction G O H - +////PIRQG#/GPIO4 Nonfunction G O H - +////PIRQH#/GPIO5 Nonfunction G O H - +////GPIO6 unused G O L - +////GPIO7 unused G O L - +////GPIO8 BOARD ID2 G I - - +////GPIO9 unused G O L - +////GPIO10 SMC_EXTSMI# G I - I +////GPIO11 Nonfunction G O H - +////GPIO12 unused G O L - +////GPIO13 SMC_WAKE_SCI# G I - I +////GPIO14 unused G O L - +////GPIO15 unused G O L - +////GPIO16 PM_DPRSLPVR N - - - +////GNT5#/GPIO17 GNT5# N - - - +////STPPCI#/GPIO18 PM_STPPCI# N - - - +////STPCPU#/GPIO20 PM_STPCPU# N - - - +////GPIO22 CRT_RefClk G I - - +////GPIO23 unused G O L - +////GPIO24 unused G O L - +////GPIO25 DMI strap G O L - +////GPIO26 unused G O L - +////GPIO27 unused G O L - +////GPIO28 RF_KILL# G O H - +////OC5#/GPIO29 OC N - - - +////OC6#/GPIO30 OC N - - - +////OC7#/GPIO31 OC N - - - +////CLKRUN#/GPIO32 PM_CLKRUN# N - - - +////GPIO33 NC G O L - +////GPIO34 BOARD ID0 G I - - +////GPIO36 unused G O L - +////GPIO38 BOARD ID1 G I - - +////GPIO39 unused G O L - +////GPIO48 unused G O L - +////CPUPWRGD/GPIO49 H_PWRGD N - - - +// +//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal +//#define GPIO_USE_SEL2_VAL 0x000100D6 +//#define GPIO_IO_SEL_VAL 0x00402502 +//#define GPIO_IO_SEL2_VAL 0x00000044 +//#define GPIO_LVL_VAL 0x1800083D +//#define GPIO_LVL2_VAL 0x00000000 +//#define GPIO_INV_VAL 0x00002402 +//#define GPIO_BLNK_VAL 0x00000000 +//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1)) + +// +// GPIO Register Settings for CedarRock and CedarFalls platforms +// +// GPIO Register Settings for NB10_CRB +//--------------------------------------------------------------------------------- +//Signal Used As USE I/O LVL +//--------------------------------------------------------------------------------- +// +// GPIO0 FP_AUDIO_DETECT G I +// GPIO1 SMC_RUNTIME_SCI# G I +// GPIO2 INT_PIRQE_N N I +// GPIO3 INT_PIRQF_N N I +// GPIO4 INT_PIRQG_N N I +// GPIO5 INT_PIRQH_N N I +// GPIO6 +// GPIO7 +// GPIO8 +// GPIO9 LPC_SIO_PME G I +// GPIO10 SMC_EXTSMI_N G I +// GPIO11 SMBALERT- pullup N +// GPIO12 ICH_GP12 G I +// GPIO13 SMC_WAKE_SCI_N G I +// GPIO14 LCD_PID0 G O H +// GPIO15 CONFIG_MODE_N G I +// GPIO16 PM_DPRSLPVR N +// GPIO17 SPI_SELECT_STRAP1 +// /L_BKLTSEL0_N G I +// GPIO18 PM_STPPCI_N N +// GPIO19 +// GPIO20 PM_STPCPU_N N +// GPIO21 +// GPIO22 REQ4B G I +// GPIO23 L_DRQ1_N N +// GPIO24 CRB_SV_DET_N G O H +// GPIO25 DMI strap +// / L_BKLTSEL1_N G O H +// GPIO26 LCD_PID1 G O H +// GPIO27 TPEV_DDR3L_DETECT G O H +// GPIO28 RF_KILL G O H:enable +// GPIO29 OC N +// GPIO30 OC N +// GPIO31 OC N +// GPIO32 PM_CLKRUN_N Native +// GPIO33 MFG_MODE_N G I +// GPIO34 BOARD ID0 G I +// GPIO35 +// GPIO36 SV_SET_UP G O H +// GPIO37 +// GPIO38 BOARD ID1 G I +// GPIO39 BOARD ID2 G I +// GPIO48 FLASH_SEL0 N +// GPIO49 H_PWRGD N + +#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2)))) +#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2)))) + +#define GPIO_USE_SEL_VAL 0X1F42F7C3 +#define GPIO_USE_SEL2_VAL 0X000000D6 +#define GPIO_IO_SEL_VAL 0X1042B73F +#define GPIO_IO_SEL2_VAL 0X000100C6 +#define GPIO_LVL_VAL 0X1F15F601 +#define GPIO_LVL2_VAL 0X000200D7 +#define GPIO_INV_VAL 0x00002602 +#define GPIO_BLNK_VAL 0x00040000 +#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1)) + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h new file mode 100644 index 0000000000..61cde2f3dc --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h @@ -0,0 +1,300 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + HwWatchdogTimer.h + +Abstract: + + +--*/ + +#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ +#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__ + +#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \ + { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } + +#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \ + { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf } + + +#include + +// +// General Purpose Constants +// +#define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48. +#define B_INSTAFLUSH BIT4 +// +// Other Watchdog timer values +// +#define WDT_COUNTDOWN_VALUE 0x14 +#define BDS_WDT_COUNTDOWN_VALUE 0x35 + + +// +// Prototypes for the Watchdog Timer Driver Protocol +// + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_START_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service begins the Watchdog Timer countdown. If the countdown completes prior to + Stop Timer or Restart Timer the system will reset. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_RESET_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service resets the Watchdog Timer countdown and should only be called after the + Start Timer function. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service restarts the Watchdog Timer countdown and should only be called after the + Start Timer function. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_STOP_TIMER) ( + VOID + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) ( + OUT HW_WATCHDOG_TIMEOUT *WatchdogTimeout + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. + + Arguments: + None + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) ( + IN BOOLEAN ForceTimeout, + IN UINT8 ResetType + ); +/*++ + + Routine Description: + This service forces a reboot of the system due to a reset of the POWERGOOD_PS, + POWERGOOD_CLK, and the BSEL Override + + Arguments: + None + + Returns: + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +--*/ + + + +typedef +EFI_STATUS +(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) ( + IN BOOLEAN AllowReset + ); +/*++ + + Routine Description: + This service notifies the Watchdog Timer of the fact that a known reset is occuring. + + Arguments: + AllowReset - TRUE if a Reset is currently expected + FALSE if a Reset is not currently expected + + Returns: + This function should not return! + + EFI_DEVICE_ERROR - The command was unsuccessful and a reboot did not occur + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 *CountdownValue + ); +/*++ + + Routine Description: + This service reads the current Watchdog Timer countdown reload value. + + Arguments: + CountdownValue - pointer to UINT32 to return the value of the reload register. + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)( + OUT UINT32 CountdownValue + ); +/*++ + + Routine Description: + This service reads the current Watchdog Timer countdown reload value. + + Arguments: + CountdownValue - Value to set the reload register. + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) ( + ); +/*++ + + Routine Description: + This service clears the state that indicates the Watchdog Timer fired. + + Arguments: + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef +EFI_STATUS +(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) ( + IN BOOLEAN Stall + ); +/*++ + + Routine Description: + This service disables the Watchdog Timer countdown. It also closes the recurring restart event + if the event exists. + + Arguments: + Stall - TRUE = Stop the timer countdown + FALSE = Start the timer countdown + + Returns: + EFI_SUCCESS - Operation completed successfully + EFI_DEVICE_ERROR - The command was unsuccessful + +--*/ + +typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL { + EFI_WATCHDOG_START_TIMER StartWatchdogTimer; + PEI_WATCHDOG_RESET_TIMER ResetWatchdogTimeout; + EFI_WATCHDOG_RESTART_TIMER RestartWatchdogTimer; + EFI_WATCHDOG_STOP_TIMER StopWatchdogTimer; + EFI_WATCHDOG_CHECK_TIMEOUT CheckWatchdogTimeout; + EFI_WATCHDOG_FORCE_REBOOT ForceReboot; + EFI_WATCHDOG_KNOWN_RESET AllowKnownReset; + EFI_GET_TIMER_COUNT_DOWN_PERIOD GetCountdownPeriod; + EFI_SET_TIMER_COUNT_DOWN_PERIOD SetCountdownPeriod; + PEI_WATCHDOG_CLEAR_TIMER_STATE ClearTimerState; + EFI_STALL_WATCHDOG_COUNTDOWN StallWatchdogCountdown; +} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL; + +extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid; +extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h new file mode 100644 index 0000000000..685e563095 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h @@ -0,0 +1,170 @@ +/** @file + I2C bus interface + + This layer provides I/O access to an I2C device. + + Copyright (c) 2012, Intel Corporation + All rights reserved. This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __I2C_BUS_H__ +#define __I2C_BUS_H__ + +#include + +/// +/// I2C bus protocol +/// +typedef struct _EFI_I2C_BUS_PROTOCOL EFI_I2C_BUS_PROTOCOL; + + +/** + Perform an I2C operation on the device + + This routine must be called at or below TPL_NOTIFY. For synchronous + requests this routine must be called at or below TPL_CALLBACK. + + N.B. The typical consumers of this API are the third party I2C + drivers. Extreme care must be taken by other consumers of this + API to prevent confusing the third party I2C drivers due to a + state change at the I2C device which the third party I2C drivers + did not initiate. I2C platform drivers may use this API within + these guidelines. + + This routine queues an operation to the I2C controller for execution + on the I2C bus. + + As an upper layer driver writer, the following need to be provided + to the platform vendor: + + 1. ACPI CID value or string - this is used to connect the upper layer + driver to the device. + 2. Slave address array guidance when the I2C device uses more than one + slave address. This is used to access the blocks of hardware within + the I2C device. + + @param[in] This Address of an EFI_I2C_BUS_PROTOCOL + structure + @param[in] SlaveAddressIndex Index into an array of slave addresses for + the I2C device. The values in the array are + specified by the board designer, with the + I2C device driver writer providing the slave + address order. + + For devices that have a single slave address, + this value must be zero. If the I2C device + uses more than one slave address then the third + party (upper level) I2C driver writer needs to + specify the order of entries in the slave address + array. + + \ref ThirdPartyI2cDrivers "Third Party I2C Drivers" + section in I2cMaster.h. + @param[in] Event Event to set for asynchronous operations, + NULL for synchronous operations + @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET + structure describing the I2C operation + @param[out] I2cStatus Optional buffer to receive the I2C operation + completion status + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_ABORTED The request did not complete because the driver + was shutdown. + @retval EFI_ACCESS_DENIED Invalid SlaveAddressIndex value + @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large. + @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation. + This could indicate the slave device is not present. + @retval EFI_INVALID_PARAMETER RequestPacket is NULL + @retval EFI_INVALID_PARAMETER TPL is too high + @retval EFI_NO_RESPONSE The I2C device is not responding to the + slave address. EFI_DEVICE_ERROR may also be + returned if the controller can not distinguish + when the NACK occurred. + @retval EFI_NOT_FOUND I2C slave address exceeds maximum address + @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for + the event and then read status pointed to by + the request packet. + @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation + @retval EFI_TIMEOUT The transaction did not complete within an internally + specified timeout period. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_I2C_BUS_START_REQUEST) ( + IN CONST EFI_I2C_BUS_PROTOCOL *This, + IN UINTN SlaveAddressIndex, + IN EFI_EVENT Event OPTIONAL, + IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +/// +/// The I2C bus protocol enables access to a specific device on the I2C bus. +/// +/// Each I2C device is described as an ACPI node (HID, UID and CID) within the +/// platform layer. The I2C bus protocol enumerates the I2C devices in the +/// platform and creates a unique handle and device path for each I2C device. +/// +/// I2C slave addressing is abstracted to validate addresses and limit operation +/// to the specified I2C device. The third party providing the I2C device support +/// provides an ordered list of slave addresses for the I2C device to the team +/// building the platform layer. The platform team must preserve the order of the +/// supplied list. SlaveAddressCount is the number of entries in this list or +/// array within the platform layer. The third party device support references +/// a slave address using an index into the list or array in the range of zero +/// to SlaveAddressCount - 1. +/// +struct _EFI_I2C_BUS_PROTOCOL { + /// + /// Start an I2C operation on the bus + /// + EFI_I2C_BUS_START_REQUEST StartRequest; + + /// + /// The maximum number of slave addresses for the I2C device. The caller may + /// validate this value as a check on the platform layer's configuration. Slave + /// address selection uses an index value in the range of zero to SlaveAddressCount - 1. + /// + UINTN SlaveAddressCount; + + /// + /// Hardware revision - Matches the ACPI _HRV value + /// + /// The HardwareRevision value allows a single driver to support multiple hardware + /// revisions and implement the necessary workarounds for limitations within the + /// hardware. + /// + UINT32 HardwareRevision; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to receive from the I2C bus. + /// + UINT32 MaximumReceiveBytes; + + /// + /// The maximum number of bytes the I2C host controller + /// is able to send on the I2C bus. + /// + UINT32 MaximumTransmitBytes; + + /// + /// The maximum number of bytes in the I2C bus transaction. + /// + UINT32 MaximumTotalBytes; +}; + +/// +/// GUID for the I2C bus protocol +/// +extern EFI_GUID gEfiI2cBusProtocolGuid; + +#endif // __I2C_BUS_H__ diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h new file mode 100644 index 0000000000..574fc3e19c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h @@ -0,0 +1,90 @@ +/*++ + +Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + PchExtendedReset.h + +Abstract: + + PCH Extended Reset Protocol + +--*/ +#ifndef _EFI_PCH_EXTENDED_RESET_H_ +#define _EFI_PCH_EXTENDED_RESET_H_ + + + +// +#define EFI_PCH_EXTENDED_RESET_PROTOCOL_GUID \ + { \ + 0xf0bbfca0, 0x684e, 0x48b3, 0xba, 0xe2, 0x6c, 0x84, 0xb8, 0x9e, 0x53, 0x39 \ + } +extern EFI_GUID gEfiPchExtendedResetProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_PCH_EXTENDED_RESET_PROTOCOL EFI_PCH_EXTENDED_RESET_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Extended Reset Types +// +typedef struct { + UINT8 PowerCycle : 1; // 0: Disabled*; 1: Enabled + UINT8 GlobalReset : 1; // 0: Disabled*; 1: Enabled + UINT8 SusPwrDnAck : 1; // 0: Do Nothing; + // 1: GPIO[30](SUS_PWR_DN_ACK) level is set low prior to Global Reset(for systems with an embedded controller) + UINT8 RsvdBits : 5; // Reserved fields for future expansion w/o protocol change +} PCH_EXTENDED_RESET_TYPES; + +// +// Member functions +// +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_EXTENDED_RESET) ( + IN EFI_PCH_EXTENDED_RESET_PROTOCOL * This, + IN PCH_EXTENDED_RESET_TYPES PchExtendedResetTypes + ); + +/*++ + +Routine Description: + + Execute Pch Extended Reset from the host controller. + +Arguments: + + This - Pointer to the EFI_PCH_EXTENDED_RESET_PROTOCOL instance. + PchExtendedResetTypes - Pch Extended Reset Types which includes PowerCycle, Globalreset. + +Returns: + + Does not return if the reset takes place. + EFI_INVALID_PARAMETER - If ResetType is invalid. + +--*/ + +// +// Interface structure for the Pch Extended Reset Protocol +// +struct _EFI_PCH_EXTENDED_RESET_PROTOCOL { + EFI_PCH_EXTENDED_RESET Reset; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h new file mode 100644 index 0000000000..2a3e2b26da --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h @@ -0,0 +1,66 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchInfo.h + + @brief + This file defines the PCH Info Protocol. + +**/ +#ifndef _PCH_INFO_H_ +#define _PCH_INFO_H_ + + +#define EFI_PCH_INFO_PROTOCOL_GUID \ + { \ + 0xd31f0400, 0x7d16, 0x4316, 0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b \ + } +extern EFI_GUID gEfiPchInfoProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define PCH_INFO_PROTOCOL_REVISION_1 1 +#define PCH_INFO_PROTOCOL_REVISION_2 2 + +/// +/// RCVersion[7:0] is the release number. +/// For example: +/// VlvFramework 0.6.0-01 should be 00 06 00 01 (0x00060001) +/// VlvFramework 0.6.2 should be 00 06 02 00 (0x00060200) +/// +#define PCH_RC_VERSION 0x01000000 + +/// +/// Protocol definition +/// +struct _EFI_PCH_INFO_PROTOCOL { + UINT8 Revision; + UINT8 BusNumber; + UINT32 RCVersion; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h new file mode 100644 index 0000000000..0205c01b82 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h @@ -0,0 +1,556 @@ +/** +**/ +/** + +Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchPlatformPolicy.h + + @brief + PCH policy protocol produced by a platform driver specifying various + expected PCH settings. This protocol is consumed by the PCH drivers. + +**/ +#ifndef _PCH_PLATFORM_POLICY_H_ +#define _PCH_PLATFORM_POLICY_H_ + + +// +#include "PchRegs.h" +#ifndef ECP_FLAG +#include "Uefi.h" +#endif + +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \ + } +extern EFI_GUID gDxePchPlatformPolicyProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11 +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12 + +/// +/// Generic definitions for device enabling/disabling used by PCH code. +/// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +/// +/// ---------------------------- Device Enabling ------------------------------ +/// +/// PCH Device enablings +/// +typedef struct { + UINT8 Lan : 1; /// 0: Disable; 1: Enable + UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto + UINT8 Sata : 1; /// 0: Disable; 1: Enable + UINT8 Smbus : 1; /// 0: Disable; 1: Enable + UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode + UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change +} PCH_DEVICE_ENABLING; + +/// +/// ---------------------------- USB Config ----------------------------- +/// +/// +/// Overcurrent pins +/// +typedef enum { + PchUsbOverCurrentPin0 = 0, + PchUsbOverCurrentPin1, + PchUsbOverCurrentPin2, + PchUsbOverCurrentPin3, + PchUsbOverCurrentPin4, + PchUsbOverCurrentPin5, + PchUsbOverCurrentPin6, + PchUsbOverCurrentPin7, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinMax +} PCH_USB_OVERCURRENT_PIN; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled + UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port. + UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port. + UINT8 Rsvdbits : 5; +} PCH_USB_PORT_SETTINGS; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 7; +} PCH_USB20_CONTROLLER_SETTINGS; + +typedef struct { + UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode + UINT8 Rsvdbits : 6; +} PCH_USBOTG_CONTROLLER_SETTINGS; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 +#define PCH_XHCI_MODE_AUTO 2 +#define PCH_XHCI_MODE_SMARTAUTO 3 + +#define PCH_EHCI_DEBUG_OFF 0 +#define PCH_EHCI_DEBUG_ON 1 + +#define PCH_USB_FRONT_PANEL 1 +#define PCH_USB_BACK_PANEL 0 + +typedef struct { + UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto + UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available + UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 4; +} PCH_USB30_CONTROLLER_SETTINGS; + +typedef struct { + UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control + UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR + UINT8 RsvdBits : 6; + PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS]; + PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax]; + PCH_USB30_CONTROLLER_SETTINGS Usb30Settings; + PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings; + PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS]; + PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS]; + /// + /// The length of Usb Port to configure the USB transmitter, + /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point. + /// + UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS]; + UINT16 EhciDebug; + UINT16 UsbXhciLpmSupport; + +} PCH_USB_CONFIG; + +/// +/// ---------------------------- PCI Express Config ---------------------- +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCI_EXPRESS_ASPM_CONTROL; + +/// +/// Refer to PCH EDS for the PCH implementation values corresponding +/// to below PCI-E spec defined ranges +/// +typedef enum { + PchPciECompletionTO_Default, + PchPciECompletionTO_50_100us, + PchPciECompletionTO_1_10ms, + PchPciECompletionTO_16_55ms, + PchPciECompletionTO_65_210ms, + PchPciECompletionTO_260_900ms, + PchPciECompletionTO_1_3P5s, + PchPciECompletionTO_4_13s, + PchPciECompletionTO_17_64s, + PchPciECompletionTO_Disabled +} PCH_PCIE_COMPLETION_TIMEOUT; + +typedef struct { + UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable. + UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port + UINT8 SlotImplemented : 1; + UINT8 HotPlug : 1; + UINT8 PmSci : 1; + UINT8 ExtSync : 1; /// Extended Synch + UINT8 Rsvdbits : 2; + /// + /// Error handlings + /// + UINT8 UnsupportedRequestReport : 1; + UINT8 FatalErrorReport : 1; + UINT8 NoFatalErrorReport : 1; + UINT8 CorrectableErrorReport : 1; + UINT8 PmeInterrupt : 1; + UINT8 SystemErrorOnFatalError : 1; + UINT8 SystemErrorOnNonFatalError : 1; + UINT8 SystemErrorOnCorrectableError : 1; + + UINT8 AdvancedErrorReporting : 1; + UINT8 TransmitterHalfSwing : 1; + UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change + + UINT8 FunctionNumber; /// The function number this root port is mapped to. + UINT8 PhysicalSlotNumber; + PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout; + PCH_PCI_EXPRESS_ASPM_CONTROL Aspm; +} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG; + +typedef struct { + /** + VendorId + + The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + + DeviceId + + The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + + RevId + + The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + + BaseClassCode + + The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + + SubClassCode + + The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + + + EndPointAspm + + The override ASPM setting from End point + **/ + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevId; + UINT8 BaseClassCode; + UINT8 SubClassCode; + PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm; +} PCH_PCIE_DEVICE_ASPM_OVERRIDE; + +typedef struct { + UINT16 VendorId; ///< PCI configuration space offset 0 + UINT16 DeviceId; ///< PCI configuration space offset 2 + UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + **/ + UINT16 NonSnoopLatency; +} PCH_PCIE_DEVICE_LTR_OVERRIDE; + +typedef struct { + /// + /// Temp Bus Number range available to be assigned to + /// each root port and its downstream devices for initialization + /// of these devices before PCI Bus enumeration + /// + UINT8 TempRootPortBusNumMin; + UINT8 TempRootPortBusNumMax; + PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS]; + BOOLEAN RootPortClockGating; + UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override + PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override + UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318. +} PCH_PCI_EXPRESS_CONFIG; + + +/// +/// ---------------------------- SATA Config ----------------------------- +/// +typedef enum { + PchSataSpeedSupportGen1 = 1, + PchSataSpeedSupportGen2 +} PCH_SATA_SPEED_SUPPORT; + +typedef struct { + UINT8 Enable : 1; /// 0: Disable; 1: Enable + UINT8 HotPlug : 1; /// 0: Disable; 1: Enable + UINT8 MechSw : 1; /// 0: Disable; 1: Enable + UINT8 External : 1; /// 0: Disable; 1: Enable + UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change +} PCH_SATA_PORT_SETTINGS; + +typedef struct { + PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS]; + UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable + UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0 + UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1 + UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10 + UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5 + UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology + UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER + UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled + + UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports + UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management + UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode + UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support + /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2) + + UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change +} PCH_SATA_CONFIG; +/// +/// --------------------------- AZALIA Config ------------------------------ +/// +typedef struct { + UINT32 VendorDeviceId; + UINT16 SubSystemId; + UINT8 RevisionId; /// 0xFF applies to all steppings + UINT8 FrontPanelSupport; + UINT16 NumberOfRearJacks; + UINT16 NumberOfFrontJacks; +} PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 *VerbTableData; +} PCH_AZALIA_VERB_TABLE; + +typedef struct { + UINT8 Pme : 1; /// 0: Disable; 1: Enable + UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached + UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable + UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable + UINT8 Rsvdbits : 3; + UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform + PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds +} PCH_AZALIA_CONFIG; + +/// +/// --------------------------- Smbus Config ------------------------------ +/// +typedef struct { + UINT8 NumRsvdSmbusAddresses; + UINT8 *RsvdSmbusAddressTable; +} PCH_SMBUS_CONFIG; + +/// +/// --------------------------- Miscellaneous PM Config ------------------------------ +/// +typedef struct { + UINT8 MeWakeSts : 1; + UINT8 MeHrstColdSts : 1; + UINT8 MeHrstWarmSts : 1; + UINT8 MeHostPowerDn : 1; + UINT8 WolOvrWkSts : 1; + UINT8 Rsvdbits : 3; +} PCH_POWER_RESET_STATUS; + +typedef struct { + UINT8 PmeB0S5Dis : 1; + UINT8 WolEnableOverride : 1; + UINT8 Rsvdbits : 6; +} PCH_WAKE_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef struct { + /// + /// Specify which Power/Reset bits need to be cleared by + /// the PCH Init Driver. + /// Usually platform drivers take care of these bits, but if + /// not, let PCH Init driver clear the bits. + /// + PCH_POWER_RESET_STATUS PowerResetStatusClear; + /// + /// Specify Wake Policy + /// + PCH_WAKE_CONFIG WakeConfig; + /// + /// SLP_XX Minimum Assertion Width Policy + /// + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; + UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up + UINT8 SlpLanLowDc : 1; + UINT8 Rsvdbits : 6; +} PCH_MISC_PM_CONFIG; + +/// +/// --------------------------- Subsystem Vendor ID / Subsystem ID Config ----- +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} PCH_DEFAULT_SVID_SID; + +/// +/// --------------------------- Lock Down Config ------------------------------ +/// +typedef struct { + UINT8 GlobalSmi : 1; + UINT8 BiosInterface : 1; + UINT8 RtcLock : 1; + UINT8 BiosLock : 1; + UINT8 Rsvdbits : 4; + UINT8 PchBiosLockSwSmiNumber; +} PCH_LOCK_DOWN_CONFIG; +// +// --------------------------- Serial IRQ Config ------------------------------ +// +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// + +typedef struct { + BOOLEAN SirqEnable; /// Determines if enable Serial IRQ + PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select +} PCH_LPC_SIRQ_CONFIG; + +/// +/// --------------------------- Power Optimizer Config ------------------------------ +/// +typedef struct { + UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table + PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table +} PCH_PWR_OPT_CONFIG; + +/// +/// --------------------- Low Power Input Output Config ------------------------ +/// +typedef struct { + UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled + UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled + UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled + UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled + UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled + UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled + UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled + UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled + UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled + UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled + UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled + UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled + UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled + UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled + UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled + UINT8 Rsvdbits : 2; +} PCH_LPSS_CONFIG; + +/// +/// ----------------------------- SCC Config -------------------------------- +/// +typedef struct { + UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled + UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled + UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled + UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled + UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled + UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5 + UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5 + UINT8 Rsvdbits : 1; + UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card + UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card + UINT8 Rsvdbits1 : 6; + UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value. +} PCH_SCC_CONFIG; + +/// +/// ------------ General PCH Platform Policy protocol definition ------------ +/// +struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + UINT8 BusNumber; /// PCI Bus Number of the PCH device + PCH_DEVICE_ENABLING *DeviceEnabling; + PCH_USB_CONFIG *UsbConfig; + PCH_PCI_EXPRESS_CONFIG *PciExpressConfig; + + PCH_SATA_CONFIG *SataConfig; + PCH_AZALIA_CONFIG *AzaliaConfig; + PCH_SMBUS_CONFIG *SmbusConfig; + PCH_MISC_PM_CONFIG *MiscPmConfig; + PCH_DEFAULT_SVID_SID *DefaultSvidSid; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + PCH_PWR_OPT_CONFIG *PwrOptConfig; + PCH_LPSS_CONFIG *LpssConfig; + PCH_SCC_CONFIG *SccConfig; + UINT8 IdleReserve; + UINT8 EhciPllCfgEnable; + UINT8 AcpiHWRed; //Hardware Reduced Mode +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..45e2860fce --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h @@ -0,0 +1,120 @@ +/** +**/ +/** + +Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchReset.h + + @brief + PCH Reset Protocol + +**/ +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + + +// +#define PCH_RESET_PROTOCOL_GUID \ + { \ + 0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \ + } +#define PCH_RESET_CALLBACK_PROTOCOL_GUID \ + { \ + 0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \ + } +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// PCH Reset Types +/// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc +} PCH_RESET_TYPE; + +/// +/// Member functions +/// +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL * This, + IN PCH_RESET_TYPE PchResetType + ) +/** + + @brief + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ) +/** + + @brief + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH + +**/ +; + +/// +/// Interface structure for the Pch Reset Protocol +/// +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; +}; + +/// +/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition +/// +struct _PCH_RESET_CALLBACK_PROTOCOL { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h new file mode 100644 index 0000000000..ca263c66e7 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h @@ -0,0 +1,138 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + PchS3Support.h + + @brief + This file defines the PCH S3 support Protocol. + +**/ +#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_ +#define _PCH_S3_SUPPORT_PROTOCOL_H_ + +#ifndef ECP_FLAG +#include +#endif + +#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \ + { \ + 0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \ + } + +#include + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gEfiPchS3SupportProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL; + +typedef enum { + PchS3ItemTypeSendCodecCommand, + PchS3ItemTypePollStatus, + PchS3ItemTypeInitPcieRootPortDownstream, + PchS3ItemTypePcieSetPm, + PchS3ItemTypePmTimerStall, + PchS3ItemTypeMax +} EFI_PCH_S3_DISPATCH_ITEM_TYPE; + +/// +/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI +/// plug 4 to ParameterSize in PEIM if you really need it +/// +typedef struct { + UINT32 HdaBar; + UINT32 CodecCmdData; +} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND; + +typedef struct { + UINT64 MmioAddress; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT64 Mask; + UINT64 Value; + UINT32 Timeout; // us +} EFI_PCH_S3_PARAMETER_POLL_STATUS; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; +} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm; + UINT8 NumOfDevAspmOverride; + UINT32 DevAspmOverrideAddr; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; + UINT8 NumOfDevLtrOverride; + UINT32 DevLtrOverrideAddr; +} EFI_PCH_S3_PARAMETER_PCIE_SET_PM; + +typedef struct { + UINT32 DelayTime; // us +} EFI_PCH_S3_PARAMETER_PM_TIMER_STALL; + +typedef struct { + EFI_PCH_S3_DISPATCH_ITEM_TYPE Type; + VOID *Parameter; +} EFI_PCH_S3_DISPATCH_ITEM; + +/// +/// Member functions +/// +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL * This, + IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem, + OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint + ); + +/** + + @brief + Set an item to be dispatched at S3 resume time. At the same time, the entry point + of the PCH S3 support image is returned to be used in subsequent boot script save + call + + @param[in] This Pointer to the protocol instance. + @param[in] DispatchItem The item to be dispatched. + @param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. + +**/ + +/// +/// Protocol definition +/// +struct _EFI_PCH_S3_SUPPORT_PROTOCOL { + EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h new file mode 100644 index 0000000000..6f6dd342cd --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h @@ -0,0 +1,415 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +--*/ + + +/*++ +Module Name: + + SdHostIo.h + +Abstract: + + Interface definition for EFI_SD_HOST_IO_PROTOCOL + +--*/ + +#ifndef _SD_HOST_IO_H +#define _SD_HOST_IO_H + + +// Global ID for the EFI_SD_HOST_IO_PROTOCOL +// {B63F8EC7-A9C9-4472-A4C0-4D8BF365CC51} +// +#define EFI_SD_HOST_IO_PROTOCOL_GUID \ + { 0xb63f8ec7, 0xa9c9, 0x4472, { 0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51 } } + +typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL; + +// +// TODO: Move to Pci22.h +// +#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 +#define PCI_IF_STANDARD_HOST_NO_DMA 0x00 +#define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01 + +// +// TODO: Retire +// +#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01 + +// +// TODO: Do these belong in an Industry Standard include file? +// +// MMIO Registers definition for MMC/SDIO controller +// +#define MMIO_DMAADR 0x00 +#define MMIO_BLKSZ 0x04 +#define MMIO_BLKCNT 0x06 +#define MMIO_CMDARG 0x08 +#define MMIO_XFRMODE 0x0C +#define MMIO_SDCMD 0x0E +#define MMIO_RESP 0x10 +#define MMIO_BUFDATA 0x20 +#define MMIO_PSTATE 0x24 +#define MMIO_HOSTCTL 0x28 +#define MMIO_PWRCTL 0x29 +#define MMIO_BLKGAPCTL 0x2A +#define MMIO_WAKECTL 0x2B +#define MMIO_CLKCTL 0x2C +#define MMIO_TOCTL 0x2E +#define MMIO_SWRST 0x2F +#define MMIO_NINTSTS 0x30 +#define MMIO_ERINTSTS 0x32 +#define MMIO_NINTEN 0x34 +#define MMIO_ERINTEN 0x36 +#define MMIO_NINTSIGEN 0x38 +#define MMIO_ERINTSIGEN 0x3A +#define MMIO_AC12ERRSTS 0x3C +#define MMIO_HOST_CTL2 0x3E //hphang <- New in VLV2 +#define MMIO_CAP 0x40 +#define MMIO_CAP2 0x44 //hphang <- New in VLV2 +#define MMIO_MCCAP 0x48 +#define MMIO_FORCEEVENTCMD12ERRSTAT 0x50 //hphang <- New in VLV2 +#define MMIO_FORCEEVENTERRINTSTAT 0x52 //hphang <- New in VLV2 +#define MMIO_ADMAERRSTAT 0x54 //hphang <- New in VLV2 +#define MMIO_ADMASYSADDR 0x58 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE0 0x60 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE1 0x64 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE2 0x68 //hphang <- New in VLV2 +#define MMIO_PRESETVALUE3 0x6C //hphang <- New in VLV2 +#define MMIO_BOOTTIMEOUTCTRL 0x70 //hphang <- New in VLV2 +#define MMIO_DEBUGSEL 0x74 //hphang <- New in VLV2 +#define MMIO_SHAREDBUS 0xE0 //hphang <- New in VLV2 +#define MMIO_SPIINTSUP 0xF0 //hphang <- New in VLV2 +#define MMIO_SLTINTSTS 0xFC +#define MMIO_CTRLRVER 0xFE + +typedef enum { + ResponseNo = 0, + ResponseR1, + ResponseR1b, + ResponseR2, + ResponseR3, + ResponseR4, + ResponseR5, + ResponseR5b, + ResponseR6, + ResponseR7 +} RESPONSE_TYPE; + +typedef enum { + NoData = 0, + InData, + OutData +} TRANSFER_TYPE; + +typedef enum { + Reset_Auto = 0, + Reset_DAT, + Reset_CMD, + Reset_DAT_CMD, + Reset_All, + Reset_HW +} RESET_TYPE; + + +typedef enum { + SDMA = 0, + ADMA2, + PIO +} DMA_MOD; + +typedef struct { + UINT32 HighSpeedSupport: 1; //High speed supported + UINT32 V18Support: 1; //1.8V supported + UINT32 V30Support: 1; //3.0V supported + UINT32 V33Support: 1; //3.3V supported + UINT32 SDR50Support: 1; + UINT32 SDR104Support: 1; + UINT32 DDR50Support: 1; + UINT32 Reserved0: 1; + UINT32 BusWidth4: 1; // 4 bit width + UINT32 BusWidth8: 1; // 8 bit width + UINT32 Reserved1: 6; + UINT32 SDMASupport: 1; + UINT32 ADMA2Support: 1; + UINT32 DmaMode: 2; + UINT32 ReTuneTimer: 4; + UINT32 ReTuneMode: 2; + UINT32 Reserved2: 6; + UINT32 BoundarySize; +} HOST_CAPABILITY; + +/*++ + + Routine Description: + The main function used to send the command to the card inserted into the SD host + slot. + It will assemble the arguments to set the command register and wait for the command + and transfer completed until timeout. Then it will read the response register to fill + the ResponseData + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + CommandIndex - The command index to set the command index field of command register + Argument - Command argument to set the argument field of command register + DataType - TRANSFER_TYPE, indicates no data, data in or data out + Buffer - Contains the data read from / write to the device + BufferSize - The size of the buffer + ResponseType - RESPONSE_TYPE + TimeOut - Time out value in 1 ms unit + ResponseData - Depending on the ResponseType, such as CSD or card status + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + EFI_OUT_OF_RESOURCES + EFI_TIMEOUT + EFI_DEVICE_ERROR + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT16 CommandIndex, + IN UINT32 Argument, + IN TRANSFER_TYPE DataType, + IN UINT8 *Buffer, OPTIONAL + IN UINT32 BufferSize, + IN RESPONSE_TYPE ResponseType, + IN UINT32 TimeOut, + OUT UINT32 *ResponseData OPTIONAL + ); + +/*++ + + Routine Description: + Set max clock frequency of the host, the actual frequency + may not be the same as MaxFrequency. It depends on + the max frequency the host can support, divider, and host + speed mode. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + MaxFrequency - Max frequency in HZ + + Returns: + EFI_SUCCESS + EFI_TIMEOUT +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 MaxFrequency + ); + +/*++ + + Routine Description: + Set bus width of the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BusWidth - Bus width in 1, 4, 8 bits + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BusWidth + ); + +/*++ + + Routine Description: + Set voltage which could supported by the host. + Support 0(Power off the host), 1.8V, 3.0V, 3.3V + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Voltage - Units in 0.1 V + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 Voltage + ); + +/*++ + + Routine Description: + Set Host High Speed + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + HighSpeed - True for High Speed Mode set, false for normal mode + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 HighSpeed + ); + +/*++ + + Routine Description: + Set High Speed Mode + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + SetHostDdrMode - True for DDR Mode set, false for normal mode + + Returns: + EFI_SUCCESS + EFI_INVALID_PARAMETER + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 DdrMode + ); + + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + ResetAll - TRUE to reset all + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN RESET_TYPE ResetType + ); + +/*++ + + Routine Description: + Reset the host + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + Enable - TRUE to enable, FALSE to disable + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN BOOLEAN Enable + ); + +/*++ + + Routine Description: + Find whether these is a card inserted into the slot. If so + init the host. If not, return EFI_NOT_FOUND. + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + + Returns: + EFI_SUCCESS + EFI_NOT_FOUND + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) ( + IN EFI_SD_HOST_IO_PROTOCOL *This + ); + +/*++ + + Routine Description: + Set the Block length + + Arguments: + This - Pointer to EFI_SD_HOST_IO_PROTOCOL + BlockLength - card supportes block length + + Returns: + EFI_SUCCESS + EFI_TIMEOUT + +--*/ +typedef +EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) ( + IN EFI_SD_HOST_IO_PROTOCOL *This, + IN UINT32 BlockLength + ); + +typedef EFI_STATUS +(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)( + IN EFI_SD_HOST_IO_PROTOCOL *This + ); + + + +// +// Interface structure for the EFI SD Host I/O Protocol +// +struct _EFI_SD_HOST_IO_PROTOCOL { + UINT32 Revision; + HOST_CAPABILITY HostCapability; + EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand; + EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency; + EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode; + EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost; + EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd; + EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost; + EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength; + EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice; + EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode; +}; + +extern EFI_GUID gEfiSdHostIoProtocolGuid; + +#endif + diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h new file mode 100644 index 0000000000..7ba9ea3d25 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h @@ -0,0 +1,53 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmbiosSlotPopulation.h + +Abstract: + + EFI SMBIOS slot structure control code. + +GUID: + {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0} + 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 + +Revision History + +--*/ + +#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_ +#define _EFI_SMBIOS_SLOT_POPULATION_H_ + +// +// Slot Population Protocol GUID +// +#define EFI_SMBIOS_SLOT_POPULATION_GUID \ + { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } + +typedef struct { + UINT16 SmbiosSlotId; // SMBIOS Slot ID + BOOLEAN InUse; // Does the slot have a card in it + BOOLEAN Disabled; // Should the slot information be in SMBIOS +} EFI_SMBIOS_SLOT_ENTRY; + +typedef struct { + UINT32 NumberOfEntries; + EFI_SMBIOS_SLOT_ENTRY *SlotEntries; +} EFI_SMBIOS_SLOT_POPULATION_INFO; + +extern EFI_GUID gEfiSmbiosSlotPopulationGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h new file mode 100644 index 0000000000..840015653c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h @@ -0,0 +1,165 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + SmmIchnDispatchEx.h + + @brief + SmmIchnDispatch Extended Protocol + +**/ +#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_ +#define _EFI_SMM_ICHN_DISPATCH_EX_H_ + +#ifdef ECP_FLAG +#include +#else +#include +#endif + +#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \ + { \ + 0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \ + } +extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL; + +/// +/// Related Definitions +/// +/// +/// Ichn Dispatch Extended Types +/// +typedef enum { + IchnExPciExpress = NUM_ICHN_TYPES + 1, + IchnExMonitor, + IchnExSpi, + IchnExQRT, + IchnExGpioUnlock, + IchnExTmrOverflow, + IchnExPcie0Hotplug, + IchnExPcie1Hotplug, + IchnExPcie2Hotplug, + IchnExPcie3Hotplug, + IchnExPcie0LinkActive, + IchnExPcie1LinkActive, + IchnExPcie2LinkActive, + IchnExPcie3LinkActive, + /// + /// INSERT NEW ITEMS JUST BEFORE THIS LINE + /// + IchnExTypeMAX /// the maximum number of items in this enumeration +} EFI_SMM_ICHN_EX_SMI_TYPE; + +typedef struct { + EFI_SMM_ICHN_EX_SMI_TYPE Type; +} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT; + +/// +/// Member functions +/// +typedef +VOID +(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext + ); + +/** + + @brief + Dispatch function for a ICH n Extended specific SMI handler. + + @param[in] DispatchHandle Handle of this dispatch function. + @param[in] DispatchContext Pointer to the dispatch function's context. + The DispatchContext fields are filled in + by the dispatching driver prior to + invoking this dispatch function. + + @retval None + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext, + OUT EFI_HANDLE * DispatchHandle + ); + +/** + + @brief + Register a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] DispatchContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the ICHN SMI source for which the dispatch + function should be invoked. + @param[in] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this + child. + @retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value + is not within valid range. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + + @brief + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval Others TBD + +**/ + +/// +/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol +/// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL { + EFI_SMM_ICHN_EX_REGISTER Register; + EFI_SMM_ICHN_EX_UNREGISTER UnRegister; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h new file mode 100644 index 0000000000..3ee6a3a7a5 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h @@ -0,0 +1,45 @@ +/*++ + +Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + SmmSmbus.h + +Abstract: + + SmmSmbus Protocol + +--*/ +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +// +// GUID for the SmmSmbus Protocol +// +// EDK and EDKII have different GUID formats +// + +#define EFI_SMM_SMBUS_PROTOCOL_GUID \ + { \ + 0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \ + } + +// +// Resuse the DXE definition, and use another GUID. +// +typedef EFI_SMBUS_HC_PROTOCOL SMM_SMBUS_HC_PROTOCOL; + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h new file mode 100644 index 0000000000..f73ef65870 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h @@ -0,0 +1,266 @@ +/** +**/ +/** + +Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + + @file + Spi.h + + @brief + This file defines the EFI SPI Protocol which implements the + Intel(R) ICH SPI Host Controller Compatibility Interface. + +**/ +#ifndef _EFI_SPI_H_ +#define _EFI_SPI_H_ + + +// +#define EFI_SPI_PROTOCOL_GUID \ + { \ + 0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \ + } +#define EFI_SMM_SPI_PROTOCOL_GUID \ + { \ + 0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \ + } +extern EFI_GUID gEfiSpiProtocolGuid; +extern EFI_GUID gEfiSmmSpiProtocolGuid; + +/// +/// Forward reference for ANSI C compatibility +/// +typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL; + +/// +/// SPI protocol data structures and definitions +/// +/// +/// Number of Prefix Opcodes allowed on the SPI interface +/// +#define SPI_NUM_PREFIX_OPCODE 2 + +/// +/// Number of Opcodes in the Opcode Menu +/// +#define SPI_NUM_OPCODE 8 + +/// +/// Opcode Type +/// EnumSpiOpcodeCommand: Command without address +/// EnumSpiOpcodeRead: Read with address +/// EnumSpiOpcodeWrite: Write with address +/// +typedef enum { + EnumSpiOpcodeReadNoAddr, + EnumSpiOpcodeWriteNoAddr, + EnumSpiOpcodeRead, + EnumSpiOpcodeWrite, + EnumSpiOpcodeMax +} SPI_OPCODE_TYPE; + +typedef enum { + EnumSpiCycle20MHz, + EnumSpiCycle33MHz, + EnumSpiCycle66MHz, /// Not supported by VLV + EnumSpiCycle50MHz, + EnumSpiCycleMax +} SPI_CYCLE_FREQUENCY; + +typedef enum { + EnumSpiRegionAll, + EnumSpiRegionBios, + EnumSpiRegionSeC, + EnumSpiRegionDescriptor, + EnumSpiRegionPlatformData, + EnumSpiRegionMax +} SPI_REGION_TYPE; + +/// +/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware +/// Sequencing Commands and Opcode Requirements" +/// +typedef enum { + EnumSpiOperationWriteStatus, + EnumSpiOperationProgramData_1_Byte, + EnumSpiOperationProgramData_64_Byte, + EnumSpiOperationReadData, + EnumSpiOperationWriteDisable, + EnumSpiOperationReadStatus, + EnumSpiOperationWriteEnable, + EnumSpiOperationFastRead, + EnumSpiOperationEnableWriteStatus, + EnumSpiOperationErase_256_Byte, + EnumSpiOperationErase_4K_Byte, + EnumSpiOperationErase_8K_Byte, + EnumSpiOperationErase_64K_Byte, + EnumSpiOperationFullChipErase, + EnumSpiOperationJedecId, + EnumSpiOperationDualOutputFastRead, + EnumSpiOperationDiscoveryParameters, + EnumSpiOperationOther, + EnumSpiOperationMax +} SPI_OPERATION; + +/// +/// SPI Command Configuration +/// Frequency The expected frequency to be used (value to be programmed to the SSFC +/// Register) +/// Operation Which Hardware Sequencing required operation this opcode respoinds to. +/// The required operations are listed in EDS Table 5-55: "Hardware +/// Sequencing Commands and Opcode Requirements" +/// If the opcode does not corresponds to any operation listed, use +/// EnumSpiOperationOther, and provides TYPE and Code for it in +/// SpecialOpcodeEntry. +/// +typedef struct _SPI_OPCODE_MENU_ENTRY { + SPI_OPCODE_TYPE Type; + UINT8 Code; + SPI_CYCLE_FREQUENCY Frequency; + SPI_OPERATION Operation; +} SPI_OPCODE_MENU_ENTRY; + +// +// Initialization data table loaded to the SPI host controller +// VendorId Vendor ID of the SPI device +// DeviceId0 Device ID0 of the SPI device +// DeviceId1 Device ID1 of the SPI device +// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller +// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu +// BiosStartOffset The offset of the start of the BIOS image relative to the flash device. +// Please note this is a Flash Linear Address, NOT a memory space address. +// This value is platform specific and depends on the system flash map. +// This value is only used on non Descriptor mode. +// BiosSize The the BIOS Image size in flash. This value is platform specific +// and depends on the system flash map. Please note BIOS Image size may +// be smaller than BIOS Region size (in Descriptor Mode) or the flash size +// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be +// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash +// (in Non Descriptor Mode) +// +typedef struct _SPI_INIT_TABLE { + UINT8 VendorId; + UINT8 DeviceId0; + UINT8 DeviceId1; + UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE]; + SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE]; + UINTN BiosStartOffset; + UINTN BiosSize; +} SPI_INIT_TABLE; + +// +// Protocol member functions +// +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_INIT) ( + IN EFI_SPI_PROTOCOL * This, + IN SPI_INIT_TABLE * InitTable + ); + +/** + + @brief + Initializes the host controller to execute SPI commands. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] InitData Pointer to caller-allocated buffer containing the SPI + interface initialization table. + + @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed. + @retval EFI_ACCESS_DENIED The SPI configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + +**/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_LOCK) ( + IN EFI_SPI_PROTOCOL * This + ); +/** + + @brief + Initializes the host controller to execute SPI commands. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] InitData Pointer to caller-allocated buffer containing the SPI + interface initialization table. + + @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed. + @retval EFI_ACCESS_DENIED The SPI configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + +**/ + +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_EXECUTE) ( + IN EFI_SPI_PROTOCOL * This, + IN UINT8 OpcodeIndex, + IN UINT8 PrefixOpcodeIndex, + IN BOOLEAN DataCycle, + IN BOOLEAN Atomic, + IN BOOLEAN ShiftOut, + IN UINTN Address, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer, + IN SPI_REGION_TYPE SpiRegionType + ); +/** + + @brief + Execute SPI commands from the host controller. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] OpcodeIndex Index of the command in the OpCode Menu. + @param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence. + @param[in] DataCycle TRUE if the SPI cycle contains data + @param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed. + @param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in. + @param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform + Region, this value specifies the offset from the Region Base; for BIOS Region, + this value specifies the offset from the start of the BIOS Image. In Non + Descriptor Mode, this value specifies the offset from the start of the BIOS Image. + Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor + Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is + supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or + the flash (in Non Descriptor Mode) + @param[in] DataByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle. + @param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe, + EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in + Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode + and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative + to base of the 1st flash device (i.e., it is a Flash Linear Address). + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @exception EFI_UNSUPPORTED Command not supported. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. + +**/ + +/// +/// Protocol definition +/// +struct _EFI_SPI_PROTOCOL { + EFI_SPI_INIT Init; + EFI_SPI_LOCK Lock; + EFI_SPI_EXECUTE Execute; +}; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h new file mode 100644 index 0000000000..4cb7dba1d4 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h @@ -0,0 +1,94 @@ +/*++ + +Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + TcoReset.h + +Abstract: + + Protocol to communicate with ICH TCO. + +GUID Info: + {A6A79162-E325-4c30-BCC3-59373064EFB3} + 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3); + + +--*/ + +#ifndef _TCO_RESET_H_ +#define _TCO_RESET_H_ + + +#define EFI_TCO_RESET_PROTOCOL_GUID \ + {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3} + +typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) ( + IN UINT32 *RcrbGcsSaveValue + ) +/*++ + +Routine Description: + + Enables the TCO timer to reset the system in case of a system hang. This is + used when writing the clock registers. + +Arguments: + + RcrbGcsSaveValue - This is the value of the RCRB GCS register before it is + changed by this procedure. This will be used to restore + the settings of this register in PpiDisableTcoReset. + +Returns: + + EFI_STATUS + +--*/ +; + +typedef +EFI_STATUS +(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) ( + OUT UINT32 RcrbGcsRestoreValue + ) +/*++ + +Routine Description: + + Disables the TCO timer. This is used after writing the clock registers. + +Arguments: + + RcrbGcsRestoreValue - Value saved in PpiEnableTcoReset so that it can + restored. + +Returns: + + EFI_STATUS + +--*/ +; + +typedef struct _EFI_TCO_RESET_PROTOCOL { + EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET EnableTcoReset; + EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET DisableTcoReset; +} EFI_TCO_RESET_PROTOCOL; + +extern EFI_GUID gEfiTcoResetProtocolGuid; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h new file mode 100644 index 0000000000..f914233660 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h @@ -0,0 +1,34 @@ +/*++ +Copyright (c) 1996 - 2014, Intel Corporation. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + + +Module Name: + + + +Abstract: + + + +--*/ + +#ifndef _RSCI_H +#define _RSCI_H + +typedef enum { + NOT_APPLICABLE_RESET = 0, + WARM_RESET = 1, + COLD_RESET = 2, + GLOBAL_RESET = 7, +}ANDROID_RESET_TYPE; + +#endif diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h new file mode 100644 index 0000000000..c73c68d907 --- /dev/null +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h @@ -0,0 +1,67 @@ +/*++ + +Copyright (c) 2004, Intel Corporation +All rights reserved. This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Module Name: + + TianoApi.h + +Abstract: + + Tiano intrinsic definitions. + + +--*/ + +#ifndef _TIANO_API_H_ +#define _TIANO_API_H_ + +// +// Pointer to internal runtime function +// +#define EFI_INTERNAL_FUNCTION 0x00000002 + +// +// Pointer to internal runtime pointer +// +#define EFI_INTERNAL_POINTER 0x00000004 + +// +// Pointer to internal runtime pointer +// +#define EFI_IPF_GP_POINTER 0x00000008 + +#define EFI_TPL_DRIVER 6 + +// +// EFI Event Types +// +#define EFI_EVENT_TIMER 0x80000000 +#define EFI_EVENT_RUNTIME 0x40000000 +#define EFI_EVENT_RUNTIME_CONTEXT 0x20000000 + +#define EFI_EVENT_NOTIFY_WAIT 0x00000100 +#define EFI_EVENT_NOTIFY_SIGNAL 0x00000200 + +#define EFI_EVENT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201 +#define EFI_EVENT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202 + +#define EFI_EVENT_EFI_SIGNAL_MASK 0x000000FF +#define EFI_EVENT_EFI_SIGNAL_MAX 4 + +// +// Task priority level +// +#define EFI_TPL_APPLICATION 4 +#define EFI_TPL_CALLBACK 8 +#define EFI_TPL_NOTIFY 16 +#define EFI_TPL_HIGH_LEVEL 31 + +#endif diff --git a/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec b/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec new file mode 100644 index 0000000000..38b975498c --- /dev/null +++ b/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec @@ -0,0 +1,121 @@ +## @file Vlv2DeviceRefCodePkg.dec +# +# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Vlv2DeviceRefCodePkg + PACKAGE_GUID = E4FA0DCA-91A3-4957-9344-C10BAA0BFE5F + PACKAGE_VERSION = 0.1 + +[Ppis] + gVlvPolicyPpiGuid = { 0x7D84B2C2, 0x22A1, 0x4372, {0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3}} + gVlvMmioPolicyPpiGuid = { 0xE767BF7F, 0x4DB6, 0x5B34, {0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2}} + gPeiSmbusPolicyPpiGuid = { 0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} + gSeCfTPMPpiGuid = { 0x10e26df1, 0x8775, 0x4ee1, {0xb5, 0x0a, 0x3a, 0xe8, 0x28, 0x93, 0x70, 0x3a}} + gPchUsbPolicyPpiGuid = { 0xc02b0573, 0x2b4e, 0x4a31, {0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c}} + gPchInitPpiGuid = { 0x09ea894a, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95}} + gPchPlatformPolicyPpiGuid = { 0x15344673, 0xD365, 0x4BE2, {0x85, 0x13, 0x14, 0x97, 0xCC, 0x07, 0x61, 0x1D}} + gPeiSpiPpiGuid = { 0xA38C6898, 0x2B5C, 0x4FF6, {0x93, 0x26, 0x2E, 0x63, 0x21, 0x2E, 0x56, 0xC2}} + gVlvPeiInitPpiGuid = { 0x09ea8911, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11}} + gSeCUmaPpiGuid = { 0xcbd86677, 0x362f, 0x4c04, {0x94, 0x59, 0xa7, 0x41, 0x32, 0x6e, 0x05, 0xcf}} + gPeiSeCPlatformPolicyPpiGuid = { 0x7ae3ceb7, 0x2ee2, 0x48fa, {0xaa, 0x49, 0x35, 0x10, 0xbc, 0x83, 0xca, 0xbf}} + gPeiHeciPpiGuid = { 0xEE0EA811, 0xFBD9, 0x4777, {0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74}} + gPeiSdhcPpiGuid = { 0xf4ef9d7a, 0x98c5, 0x4c1a, {0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0x0c}} + gPeiBlockIoPpiGuid = { 0xbc5fa650, 0xedbb, 0x4d0d, {0xb3, 0xa3, 0xd9, 0x89, 0x07, 0xf8, 0x47, 0xdf}} + gSeCfTPMPolicyPpiGuid = { 0x4fd1ba49, 0x8f90, 0x471a, {0xa2, 0xc9, 0x17, 0x3c, 0x7a, 0x73, 0x2f, 0xd0}} + gEfiPeiReadOnlyVariable2PpiGuid = { 0x2ab86ef5, 0xecb5, 0x4134, {0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4}} + gPchPeiInitPpiGuid = { 0xACB93B08, 0x5CDC, 0x4A8F, {0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E}} + +[Protocols] + gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}} + gPpmPlatformPolicyProtocolGuid = { 0xddabfeac, 0xef63, 0x452c, {0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}} + gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}} + gMemInfoProtocolGuid = { 0x6f20f7c8, 0xe5ef, 0x4f21, {0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae}} + gEfiSdHostIoProtocolGuid = { 0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}} + gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}} + gEfiSmmSpiProtocolGuid = { 0xD9072C35, 0xEB8F, 0x43AD, {0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85}} + gEfiSmmIchnDispatchExProtocolGuid = { 0x3920405B, 0xC897, 0x44DA, {0x88, 0xF3, 0x4C, 0x49, 0x8A, 0x6F, 0xF7, 0x36}} + gEfiPchS3SupportProtocolGuid = { 0xE287D20B, 0xD897, 0x4E1E, {0xA5, 0xD9, 0x97, 0x77, 0x63, 0x93, 0x6A, 0x04}} + gPchResetProtocolGuid = { 0xDB63592C, 0xB8CC, 0x44C8, {0x91, 0x8C, 0x51, 0xF5, 0x34, 0x59, 0x8A, 0x5A}} + gPchResetCallbackProtocolGuid = { 0x3A3300AB, 0xC929, 0x487D, {0xAB, 0x34, 0x15, 0x9B, 0xC1, 0x35, 0x62, 0xC0}} + gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23, {0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5}} + gEfiPchInfoProtocolGuid = { 0xD31F0400, 0x7D16, 0x4316, {0xBF, 0x88, 0x60, 0x65, 0x88, 0x3B, 0x40, 0x2B}} + gEfiPchExtendedResetProtocolGuid = { 0xF0BBFCA0, 0x684E, 0x48B3, {0xBA, 0xE2, 0x6C, 0x84, 0xB8, 0x9E, 0x53, 0x39}} + gEfiActiveBiosProtocolGuid = { 0xEBBE2D1B, 0x1647, 0x4BDA, {0xAB, 0x9A, 0x78, 0x63, 0xE3, 0x96, 0xD4, 0x1A}} + gDxeIchPlatformPolicyProtocolGuid = { 0xf617b358, 0x12cf, 0x414a, {0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb3}} + gEfiIchInfoProtocolGuid = { 0xd31f0400, 0x7d16, 0x4316, {0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b}} + gEfiSmmIoTrapDispatchProtocolGuid = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0x0e, 0x29, 0x41, 0x8d, 0xf9, 0x30}} + gEfiSmmSmbusProtocolGuid = { 0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}} + gDxeVlvPlatformPolicyGuid = { 0x5bab88ba, 0xe0e2, 0x4674, {0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}} + gIgdOpRegionProtocolGuid = { 0xcdc5dddf, 0xe79d, 0x41ec, {0xa9, 0xb0, 0x65, 0x65, 0x49, 0x0d, 0xb9, 0xd3}} + gEfiHeciProtocolGuid = { 0xcfb33810, 0x6e87, 0x4284, {0xb2, 0x03, 0xa6, 0x6a, 0xbe, 0x07, 0xf6, 0xe8}} + gPlatformSeCHookProtocolGuid = { 0xbc52476e, 0xf67e, 0x4301, {0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}} + gEfiSeCRcInfoProtocolGuid = { 0x11fbfdfb, 0x10d2, 0x43e6, {0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a}} + gEfiTdtProtocolGuid = { 0x0bf70067, 0xd53b, 0x42df, {0xb7, 0x70, 0xe9, 0x2c, 0x91, 0xc6, 0x14, 0x11}} + gDxePlatformSeCPolicyGuid = { 0xf8bff014, 0x18fb, 0x4ef9, {0xb1, 0x0c, 0xae, 0x22, 0x73, 0x8d, 0xbe, 0xed}} + gLpssDummyProtocolGuid = { 0xaf4cc162, 0xd41c, 0x455a, {0xab, 0x45, 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3}} + gEfiEmmcCardInfoProtocolGuid = { 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd}} + gEfiTdtOperationProtocolGuid = {0xfd301ba4, 0x5e62, 0x4679,{ 0xa0, 0x6f, 0xe0, 0x9a, 0xab, 0xdd, 0x2a, 0x91}} + gEfiConfigFileNameGuid = { 0x98B8D59B, 0xE8BA, 0x48EE, { 0x98, 0xDD, 0xC2, 0x95, 0x39, 0x2F, 0x1E, 0xDB }} + gEfiDFUResultGuid = { 0x14a7c46f, 0xbc02, 0x4047, { 0x9f, 0x18, 0xa5, 0xd7, 0x25, 0xd8, 0xbd, 0x19 }} + +[Guids] + gEfiCPTokenSpaceGuid = { 0x918211ce, 0xa1d2, 0x43a0, {0xa0, 0x4e, 0x75, 0xb5, 0xbf, 0x44, 0x50, 0x0E}} + gEfiSmbusArpMapGuid = { 0x707BE83E, 0x0BF6, 0x40A5, {0xBE, 0x64, 0x34, 0xC0, 0x3A, 0xA0, 0xB8, 0xE2}} + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}} + gEfiVLVTokenSpaceGuid = { 0xca452c68, 0xdf0c, 0x45c9, {0x82, 0xfb, 0xea, 0xe4, 0x2b, 0x31, 0x29, 0x46}} + gSataControllerDriverGuid = { 0xbb929da9, 0x68f7, 0x4035, {0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55}} + gDxePchPolicyUpdateProtocolGuid = { 0x1a819e49, 0xd8ee, 0x48cb, {0x9a, 0x9c, 0x0a, 0xa0, 0xd2, 0x81, 0x0a, 0x38}} + gPowerManagementAcpiTableStorageGuid = { 0x161be597, 0xe9c5, 0x49db, {0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda}} + gEfiSetupVariableGuid = { 0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9}} + gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, {0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}} + gPchInitVariableGuid = { 0xe6c2f70a, 0xb604, 0x4877, {0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}} + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}} + gVlvRefCodePkgTokenSpaceGuid = { 0x85768E4A, 0x6CDC, 0x444E, {0x93, 0xDF, 0x93, 0x66, 0x85, 0xB5, 0xDF, 0xCC}} + gSeCPlatformReadyToBootGuid = { 0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}} + gAmtReadyToBootGuid = { 0x40b09b5a, 0xf0ef, 0x4627, {0x93, 0xd5, 0x27, 0xf0, 0x4b, 0x75, 0x4d, 0x05}} + # + # According to UEFI 2.3.1 Errata C, 3.2 Globally Defined Variables. + # To prevent name collisions with possible future globally defined variables, + # other internal firmware data variables that are not defined in Table.10 must be saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE. + # + gEfiVlv2VariableGuid = { 0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5}} + +[Includes.common] + . + ValleyView2Soc/NorthCluster/Include + ValleyView2Soc/SouthCluster/Include + ValleyView2Soc/CPU/Include + Include + +[PcdsFixedAtBuild] + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207 + +[PcdsDynamic, PcdsDynamicEx] + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207 + gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0|UINT8|0x10000208 + gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0|UINT32|0x10000209 + gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE|BOOLEAN|0x1000020A + gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE|BOOLEAN|0x1000020B + gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE|BOOLEAN|0x1000020C + gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0|UINT32|0x1000020D + gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0|UINT32|0x1000020E + gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE|BOOLEAN|0x1000020F + gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0|UINT32|0x10000210 + +[PcdsFeatureFlag] + gVlvRefCodePkgTokenSpaceGuid.PcdCeAtaSupport|FALSE|BOOLEAN|0x12 + gVlvRefCodePkgTokenSpaceGuid.PcdMmcSdMultiBlockSupport|TRUE|BOOLEAN|0x13 + -- cgit v1.2.3