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authorJacob Garber <jgarber1@ualberta.ca>2021-02-20 10:51:56 -0700
committerAngel Pons <th3fanbus@gmail.com>2021-02-28 11:24:33 +0000
commitb05c9b18452e3c73e80d0abd5194928d224c3d1b (patch)
tree0ac57d45ba434d845f30fc7a7ea257810e6e3359
parentf3359e50de810d506670f2efd7d6adc802e69876 (diff)
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chipset_enable: Mark Intel C216 as DEPHEADmaster
Tested reading and writing internal flash on HP Z220 SFF. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I97538577c32e6c40374c414f005eb3165ed2e11d Reviewed-on: https://review.coreboot.org/c/flashrom/+/50986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--chipset_enable.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 040b151b..138cb12c 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1849,7 +1849,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7},
{0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7},
{0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7},
- {0x8086, 0x1e53, B_FS, NT, "Intel", "C216", enable_flash_pch7},
+ {0x8086, 0x1e53, B_FS, DEP, "Intel", "C216", enable_flash_pch7},
{0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7},
{0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7},
{0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7},