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| author | Nico Huber <nico.h@gmx.de> | 2017-12-13 00:44:45 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-12-19 12:31:00 +0000 |
| commit | 078d24ef2feb59d1de3a0eb5f99010c999763758 (patch) | |
| tree | 955150f1512b27069313e73899d994326561723d | |
| parent | 60210dea9ed2a8b6349e95580487bf8195b144f8 (diff) | |
| download | flashrom-078d24ef2feb59d1de3a0eb5f99010c999763758.tar.gz flashrom-078d24ef2feb59d1de3a0eb5f99010c999763758.tar.bz2 flashrom-078d24ef2feb59d1de3a0eb5f99010c999763758.zip | |
ichspi: Fix 100 series PCH (Skylake) support
Pretty subtle missing `else` made flashrom treat Skylake like older
chipsets.
Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net>
Reviewed-on: https://review.coreboot.org/22832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
(cherry picked from commit 19eb0792b8439198d7ef0077b8f79f275fa39a9d)
Reviewed-on: https://review.coreboot.org/22944
| -rw-r--r-- | ichspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1715,7 +1715,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen) hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { + } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; |