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| author | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-21 12:50:07 +1100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-12-01 10:10:29 +0000 |
| commit | 327a82bbe88711cd6ba9503c988d7880aca67711 (patch) | |
| tree | d1b4cbcf3e038821620716cf3702365726876038 | |
| parent | 7955239b2cd5ba3397bc06353d7e60b37a7de6de (diff) | |
| download | flashrom-327a82bbe88711cd6ba9503c988d7880aca67711.tar.gz flashrom-327a82bbe88711cd6ba9503c988d7880aca67711.tar.bz2 flashrom-327a82bbe88711cd6ba9503c988d7880aca67711.zip | |
opaque_master: Mark Opaque chip as tested for WP
Opaque masters, by design, populate the flashchip structure during
the execution of their probe function. Therefore any opaque master
operation displays a message to the user:
"This flash part has status UNTESTED for operations: WP".
However, for all the other operations (read, write, erase) opaque
masters always mark them as tested. Thus, align WP as marked tested
inline with other opaque chip operations.
BUG=b:258755442
TEST=the following does not display untested message:
1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE
2) flashrom -p internal (on Intel device)
Original-Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
| -rw-r--r-- | dummyflasher.c | 2 | ||||
| -rw-r--r-- | ichspi.c | 2 | ||||
| -rw-r--r-- | nicintel_eeprom.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/dummyflasher.c b/dummyflasher.c index 110a88ce3..35cdfef0b 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -145,7 +145,7 @@ static int probe_variable_size(struct flashctx *flash) msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__, flash->chip->total_size); - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; if (emu_data->erase_to_zero) flash->chip->feature_bits |= FEATURE_ERASED_ZERO; @@ -1485,7 +1485,7 @@ static int ich_hwseq_probe(struct flashctx *flash) msg_cdbg("In that range are %d erase blocks with %d B each.\n", size_high / erase_size_high, erase_size_high); } - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; return 1; } diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ff2c3ce69..4d5ab6b91 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -115,7 +115,7 @@ static int nicintel_ee_probe_i210(struct flashctx *flash) /* Emulated eeprom has a fixed size of 4 KB */ flash->chip->total_size = 4; flash->chip->page_size = flash->chip->total_size * 1024; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; flash->chip->block_erasers->eraseblocks[0].count = 1; @@ -146,7 +146,7 @@ static int nicintel_ee_probe_82580(struct flashctx *flash) } flash->chip->page_size = EE_PAGE_MASK + 1; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1); flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1); |