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| author | Liam Flaherty <liamflaherty@chromium.org> | 2022-11-17 16:22:04 +1100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-12-06 21:23:11 +0000 |
| commit | f6e5dd94f86c6178e6fcb22e347a575eaeb83394 (patch) | |
| tree | bb8eb371e5ce49beb56b3d6d82f10bf072aa723b | |
| parent | e7b3ea3f5689b28ebeea6e5ed276d431b4d67eba (diff) | |
| download | flashrom-f6e5dd94f86c6178e6fcb22e347a575eaeb83394.tar.gz flashrom-f6e5dd94f86c6178e6fcb22e347a575eaeb83394.tar.bz2 flashrom-f6e5dd94f86c6178e6fcb22e347a575eaeb83394.zip | |
flashchips.c: Add 4BA write to XM25Qx256C
Flash chips XM25QH256C and XM25QU256C support the 4-byte program
command (0x12) according to their datasheets, but the feature flag is
not enabled in flashchips.c, so enable it to allow this feature to be
used.
TICKET: https://ticket.coreboot.org/issues/371
BUG=b:259493706
TEST=build
Original-Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713
Original-Reviewed-by: Felix Singer <felixsinger@posteo.net>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
| -rw-r--r-- | flashchips.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/flashchips.c b/flashchips.c index 6fc3a848d..76f3fbbfe 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19807,7 +19807,7 @@ const struct flashchip flashchips[] = { /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | - FEATURE_WRSR2, + FEATURE_4BA_WRITE | FEATURE_WRSR2, .tested = TEST_UNTESTED, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, @@ -19856,7 +19856,8 @@ const struct flashchip flashchips[] = { /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ + | FEATURE_4BA_WRITE, .tested = TEST_UNTESTED, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, |