summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2011-07-01 00:39:23 +0000
committerStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2011-07-01 00:39:23 +0000
commit10b3e228703c8d5b42555a60954daf3ea01c2f16 (patch)
treeeadb869d47a90613588c3d42d4344854622f34f4
parentbd649e450c8699b67747d76c81521fc704f105b1 (diff)
downloadflashrom-10b3e228703c8d5b42555a60954daf3ea01c2f16.tar.gz
flashrom-10b3e228703c8d5b42555a60954daf3ea01c2f16.tar.bz2
flashrom-10b3e228703c8d5b42555a60954daf3ea01c2f16.zip
ichspi.c: preserve reserved bits in address registers
Corresponding to flashrom svn r1362. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
-rw-r--r--ichspi.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/ichspi.c b/ichspi.c
index f35ea3786..19e52d23f 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -659,10 +659,11 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
return 1;
}
- /* Programm Offset in Flash into FADDR */
- REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
+ /* Program offset in flash into SPIA while preserving reserved bits. */
+ temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
+ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
- /* Program data into FDATA0 to N */
+ /* Program data into SPID0 to N */
if (write_cmd && (datalength != 0)) {
temp32 = 0;
for (a = 0; a < datalength; a++) {
@@ -803,8 +804,10 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
return 1;
}
- /* Programm Offset in Flash into FADDR */
- REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
+ /* Program offset in flash into FADDR while preserve the reserved bits
+ * and clearing the 25. address bit which is only useable in hwseq. */
+ temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
+ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
/* Program data into FDATA0 to N */
if (write_cmd && (datalength != 0)) {